AT89C51RC-24PU [ATMEL]
8-bit Microcontroller with 32K Bytes Flash; 8位微控制器，带有32K字节的闪存
| 型号： | AT89C51RC-24PU |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 32K Bytes Flash |
| 文件： | 总36页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Compatible with MCS®-51 Products
• 32K Bytes of Reprogrammable Flash Memory
• Endurance: 1000 Write/Erase Cycles
• 4V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 512 x 8-bit Internal RAM
• 32 Programmable I/O Lines
8-bit
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
Microcontroller
with 32K Bytes
Flash
• Programmable Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Hardware Watchdog Timer
• Dual Data Pointer
• Power-off Flag
• Green (Pb/Halide-free) Packaging Option
AT89C51RC
1. Description
The AT89C51RC is a low-power, high-performance CMOS 8-bit microcontroller with
32K bytes of Flash programmable read-only memory and 512 bytes of RAM. The
device is manufactured using Atmel’s high-density nonvolatile memory technology
and is compatible with the industry-standard 80C51 and 80C52 instruction set and
pinout. The on-chip Flash allows the program memory to be user programmed by a
conventional nonvolatile memory programmer. A total of 512 bytes of internal RAM
are available in the AT89C51RC. The 256-byte expanded internal RAM is accessed
via MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The
other 256-byte RAM segment is accessed the same way as the Atmel AT89-series
and other 8052-compatible products. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89C51RC is a powerful microcomputer which pro-
vides a highly-flexible and cost-effective solution to many embedded control
applications.
The AT89C51RC provides the following standard features: 32K bytes of Flash, 512
bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89C51RC is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops the
CPU while allowing the RAM, timer/counters, serial port, and interrupt system to con-
tinue functioning. The Power-down mode saves the RAM contents but freezes the
oscillator, disabling all other chip functions until the next external interrupt or hardware
reset.
1920C–MICRO–03/05
2. Pin Configurations
2.1
44A – 44-lead TQFP
P1.5
P1.6
1
2
3
4
5
6
7
8
9
33 P0.4 (AD4)
32 P0.5 (AD5)
31 P0.6 (AD6)
30 P0.7 (AD7)
29 EA/VPP
P1.7
RST
(RXD) P3.0
NC
28 NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
27 ALE/PROG
26 PSEN
25 P2.7 (A15)
24 P2.6 (A14)
23 P2.5 (A13)
(T0) P3.4 10
(T1) P3.5 11
2.2
44J – 44-lead PLCC
P1.5
P1.6
P1.7
7
8
9
39 P0.4 (AD4)
38 P0.5 (AD5)
37 P0.6 (AD6)
36 P0.7 (AD7)
35 EA/VPP
34 NC
RST 10
(RXD) P3.0 11
NC 12
(TXD) P3.1 13
(INT0) P3.2 14
(INT1) P3.3 15
(T0) P3.4 16
(T1) P3.5 17
33 ALE/PROG
32 PSEN
31 P2.7 (A15)
30 P2.6 (A14)
29 P2.5 (A13)
2.3
40P6 – 40-lead PDIP
(T2) P1.0
1
2
3
4
5
6
7
8
9
40 VCC
(T2EX) P1.1
P1.2
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0 10
(TXD) P3.1 11
(INT0) P3.2 12
(INT1) P3.3 13
(T0) P3.4 14
(T1) P3.5 15
(WR) P3.6 16
(RD) P3.7 17
XTAL2 18
30 ALE/PROG
29 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
XTAL1 19
GND 20
2
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
3. Block Diagram
P0.0 - P0.7
P2.0 - P2.7
VCC
PORT 0 DRIVERS
PORT 2 DRIVERS
GND
RAM ADDR.
REGISTER
PORT 2
LATCH
PORT 0
LATCH
FLASH
RAM
PROGRAM
ADDRESS
REGISTER
STACK
POINTER
B
ACC
REGISTER
BUFFER
TMP2
TMP1
PC
INCREMENTER
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PROGRAM
COUNTER
PSW
PSEN
ALE/PROG
EA / VPP
RST
TIMING
AND
CONTROL
DUAL
DPTR
INSTRUCTION
REGISTER
PORT 1
LATCH
PORT 3
LATCH
WATCH
DOG
OSC
PORT 1 DRIVERS
P1.0 - P1.7
PORT 3 DRIVERS
P3.0 - P3.7
3
1920C–MICRO–03/05
4. Pin Description
4.1
4.2
4.3
VCC
Supply voltage.
Ground.
GND
Port 0
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL
inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses
to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-
ing program verification. External pull-ups are required during program verification.
4.4
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low
will source current (IIL) because of the internal pull-ups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-
ing table.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin
P1.0
Alternate Functions
T2 (external count input to Timer/Counter 2), clock-out
T2EX (Timer/Counter 2 capture/reload trigger and direction control)
P1.1
4.5
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low
will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and dur-
ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special
Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash program-
ming and verification.
4
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
4.6
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low
will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89C51RC, as shown in the
following table.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
4.7
4.8
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO
bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit
DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG
Address Latch Enable is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be
used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-
ing each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
4.9
PSEN
Program Store Enable is the read strobe to external program memory.
When the AT89C51RC is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during each access to
external data memory.
5
1920C–MICRO–03/05
4.10 EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.
4.11 XTAL1
4.12 XTAL2
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier.
5. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1.
Table 5-1.
AT89C51RC SFR Map and Reset Values
0F8H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
B
0F0H
0E8H
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
00000000
ACC
00000000
PSW
00000000
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
AUXR1
XXXXXXX0
WDTRST
XXXXXXXX
SCON
00000000
SBUF
XXXXXXXX
P1
11111111
90H
97H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
AUXR
XXX00X00
88H
8FH
P0
11111111
SP
00000111
DP0L
00000000
DP0H
00000000
DP1L
00000000
DP1H
00000000
PCON
0XXX0000
80H
87H
6
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 5-
2) and T2MOD (shown in Table 13-1 and Table 5-4) for Timer 2. The register pair (RCAP2H,
RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-
reload mode.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can
be set for each of the six interrupt sources in the IP register.
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,
two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-
83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should always initialize the DPS bit to the appropriate value before accessing the
respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF
is set to “1” during power up. It can be set and reset under software control and is not affected by
reset.
7
1920C–MICRO–03/05
Table 5-2.
T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8H
Reset Value = 0000 0000B
Bit Addressable
TF2
EXF2
6
RCLK
5
TCLK
4
EXEN2
3
TR2
2
C/T2
1
CP/RL2
0
Bit
7
Function
Symbol
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK
= 1 or TCLK = 1.
TF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
EXF2
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
RCLK
TCLK
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
EXEN2
TR2
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
C/T2
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1.
When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
CP/RL2
8
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
Table 5-3.
AUXR: Auxiliary Register
Address = 8EH
AUXR
Reset Value = XXX00X00B
Not Bit Addressable
–
7
–
–
5
WDIDLE
4
DISRTO
3
–
2
EXTRAM
1
DISALE
0
Bit
6
–
Reserved for future expansion
Disable/Enable ALE
DISALE
DISALE
Operating Mode
0
1
ALE is emitted at a constant rate of 1/6 the oscillator frequency
ALE is active only during a MOVX or MOVC instruction
EXTRAM
DISRTO
WDIDLE
Internal/External RAM access using MOVX @ Ri/@DPTR
EXTRAM
Operating Mode
0
1
Internal ERAM (00H-FFH) access using MOVX @ Ri/@DPTR
External data memory access
Disable/Enable Reset out
DISRTO
Operating Mode
0
1
Reset pin is driven High after WDT times out
Reset pin is input only
Disable/Enable WDT in IDLE mode
WDIDLE
Operating Mode
0
1
WDT continues to count in IDLE mode
WDT halts counting in IDLE mode
Table 5-4.
AUXR1: Auxiliary Register 1
Address = A2H
AUXR1
Reset Value = XXXXXXX0B
Not Bit Addressable
–
7
–
6
–
5
–
4
–
3
–
2
–
1
DPS
0
Bit
–
Reserved for future expansion
Data Pointer Register Select
DPS
DPS
0
1
Selects DPTR Registers DP0L, DP0H
Selects DPTR Registers DP1L, DP1H
9
1920C–MICRO–03/05
6. Memory Organization
The MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.
7. Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89C51RC, if EA is connected to VCC, program fetches to addresses 0000H through
7FFFH are directed to internal memory and fetches to addresses 8000H through FFFFH are to
external memory.
7.1
Data Memory
The AT89C51RC has internal data memory that is mapped into four separate segments: the
lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes special function register (SFR) and
256 bytes expanded RAM (ERAM).
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly address-
able only.
4. The 256-byte expanded RAM (ERAM, 00H-FFH) is indirectly accessed by MOVX
instructions, and with the EXTRAM bit cleared.
The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128
bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same
address space as the SFR. This means they have the same address, but are physically sepa-
rate from the SFR space.
When an instruction accesses an internal location above address 7FH, the CPU knows whether
the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used
in the instruction. Instructions that use direct addressing access SFR space. For example:
MOV 0A0H, # data
accesses the SFR at location 0S0H (which is P2). Instructions that use indirect addressing
access the Upper 128 bytes of data RAM. For example:
MOV@R0, # data
where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data
RAM are available as stack space.
The 256 bytes of ERAM can be accessed by indirect addressing, with EXTRAM bit cleared and
MOVX instructions. This part of memory is physically located on-chip, logically occupying the
first 256 bytes of external data memory.
10
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in combina-
tion with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not
affect ports P0, P2, P3.6 (WR), and P3.7 (RD). For example, with EXTRAM = 0,
MOVX@R0, # data
where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external memory.
An access to external data memory locations higher than FFH (i.e. 0100H to FFFFH) will be per-
formed with the MOVX DPTR instructions in the same way as in the standard 80C51, i.e., with
P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals (see Figure
7-1).
Figure 7-1. Internal and External Data Memory Address (with EXTRAM = 0)
FF
FF
FF
FFFF
UPPER
SPECIAL
FUNCTION
REGISTER
EXTERNAL
DATA
MEMORY
128 BYTES
INTERNAL
RAM
ERAM
80
80
256 BYTES
LOWER
128 BYTES
INTERNAL
RAM
0100
0000
00
00
With EXTRAM = 1, MOVX @ Ri and MOVX@DPTR will be similar to the standard 80C51.
MOVX@Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins
can be used to output higher-order address bits. This is to provide the external paging capability.
MOVX@DPTR will generate a 16-bit address. Port 2 outputs the high-order 8 address bits (the
contents of DP0H), while Port 0 multiplexes the low-order 8 address bits (the contents of DP0L)
with data. MOVX@Ri and MOVX@DPTR will generate either read or write signals on P3.6 (WR)
and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)
internal data memory. The stack may not be located in the ERAM.
8. Hardware Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 13-bit counter and the WatchDog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT timeout period is dependent on the external clock frequency. There is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-
flows, it will drive an output RESET HIGH pulse at the RST pin.
11
1920C–MICRO–03/05
9. Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches
8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every
machine cycle while the oscillator is running. This means the user must re-initialize the WDT at
least every 8191 machine cycles. To re-initialize the WDT the user must write 01EH and 0E1H
to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written.
When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse
duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be
serviced in those sections of code that will periodically be executed within the time required to
prevent a WDT reset.
10. WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode, the user does not need to service the WDT. There are two methods of exiting
Power-down mode: by a hardware reset or via a level-activated external interrupt which is
enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89C51RC is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for
the interrupt used to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to
reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0)
as the default state. To prevent the WDT from resetting the AT89C51RC while in IDLE mode,
the user should always set up a timer that will periodically exit IDLE, service the WDT, and reen-
ter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.
11. UART
The UART in the AT89C51RC operates the same way as the UART in the AT89C51 and
AT89C52. For more detailed information on the UART operation, please click on the document
link below:
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
12
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
12. Timer 0 and 1
13. Timer 2
Timer 0 and Timer 1 in the AT89C51RC operate the same way as Timer 0 and Timer 1 in the
AT89C51 and AT89C52. For further information on the timers’ operation, please click on the
document link below:
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The
type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 5-2). Timer 2 has
three operating modes: capture, auto-reload (up or down counting), and baud rate generator.
The modes are selected by bits in T2CON, as shown in Table 13-1.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is
incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the
count rate is 1/12 of the oscillator frequency.
Table 13-1. Timer 2 Operating Modes
RCLK +TCLK
CP/RL2
TR2
1
MODE
0
0
1
X
0
1
16-bit Auto-reload
16-bit Capture
Baud Rate Generator
(Off)
1
X
X
1
0
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-
sponding external input pin, T2. In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one cycle and a low in the next cycle,
the count is incremented. The new count value appears in the register during S3P1 of the cycle
following the one in which the transition was detected. Since two machine cycles (24 oscillator
periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the
oscillator frequency. To ensure that a given level is sampled at least once before it changes, the
level should be held for at least one full machine cycle.
13.1 Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is
a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used
to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi-
tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into
RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illus-
trated in Figure 13-1.
13
1920C–MICRO–03/05
13.2 Auto-Reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload
mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR
T2MOD (see Table 13-2). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to
count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the
T2EX pin.
Figure 13-2 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options
are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets
the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the
16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture Mode RCAP2H and
RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit.
Both the TF2 and EXF2 bits can generate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 13-2. In this
mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count
up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit
value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2,
respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal
the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH
to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit
of resolution. In this operating mode, EXF2 does not flag an interrupt.
Figure 13-1. Timer in Capture Mode
÷12
OSC
C/T2 = 0
C/T2 = 1
TH2
TL2
TF2
OVERFLOW
CONTROL
TR2
CAPTURE
T2 PIN
RCAP2H RCAP2L
EXF2
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
T2EX PIN
CONTROL
EXEN2
14
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
Figure 13-2. Timer 2 Auto Reload Mode (DCEN = 0)
12
OSC
C/T2 = 0
TH2
TL2
OVERFLOW
CONTROL
TR2
C/T2 = 1
RELOAD
T2 PIN
TIMER 2
INTERRUPT
RCAP2H RCAP2L
TF2
TRANSITION
DETECTOR
EXF2
T2EX PIN
CONTROL
EXEN2
Table 13-2. T2MOD—Timer 2 Mode Control Register
T2MOD Address = 0C9H
Reset Value = XXXX XX00B
Not Bit Addressable
–
7
–
6
–
5
–
4
–
3
–
2
T2OE
1
DCEN
0
Bit
Symbol
–
Function
Not implemented, reserved for future
Timer 2 Output Enable bit
T2OE
DCEN
When set, this bit allows Timer 2 to be configured as an up/down counter
Figure 13-3. Timer 2 Auto Reload Mode (DCEN = 1)
TOGGLE
(DOWN COUNTING RELOAD VALUE)
0FFH 0FFH
EXF2
OSC
12
OVERFLOW
C/T2 = 0
TH2
TL2
TF2
CONTROL
TR2
TIMER 2
INTERRUPT
C/T2 = 1
T2 PIN
RCAP2H RCAP2L
(UP COUNTING RELOAD VALUE)
COUNT
DIRECTION
1=UP
0=DO
T2EX PIN
15
1920C–MICRO–03/05
14. Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table
5-2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the
receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK
puts Timer 2 into its baud rate generator mode, as shown in Figure 14-1.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2
causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and
RCAP2L, which are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the fol-
lowing equation.
Timer 2 Overflow Rate
Mdes 1 and 3 Baud Rates = -----------------------------------------------------------
16
Figure 14-1. Timer 2 in Baud Rate Generator Mode
TIMER 1 OVERFLOW
2
÷
"0"
"0"
"1"
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
SMOD1
RCLK
2
OSC
÷
C/T2 = 0
"1"
"1"
TH2
TL2
Rx
CLOCK
CONTROL
TR2
÷
16
C/T2 = 1
"0"
T2 PIN
TCLK
RCAP2H RCAP2L
Tx
CLOCK
TRANSITION
DETECTOR
16
÷
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
The Timer can be configured for either timer or counter operation. In most applications, it is con-
figured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is
used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12
the oscillator frequency). As a baud rate generator, however, it increments every state time (at
1/2 the oscillator frequency). The baud rate formula is given below.
Modes 1 and 3
Baud Rate 32 x [65536-RCAP2H,RCAP2L)]
Oscillator Frequency
--------------------------------------- = -------------------------------------------------------------------------------------
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned
integer.
Timer 2 as a baud rate generator is shown in Figure 14-1. This figure is valid only if RCLK or
TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter-
16
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
rupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a
reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate gen-
erator, T2EX can be used as an extra external interrupt.
Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or
TL2 should not be read from or written to. Under these conditions, the Timer is incremented
every state time, and the results of a read or write may not be accurate. The RCAP2 registers
may be read but should not be written to, because a write might overlap a reload and cause
write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer
2 or RCAP2 registers.
15. Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 15-1. This
pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input
the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to
4 MHz at a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and
bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2
capture registers (RCAP2H, RCAP2L), as shown in the following equation.
Oscillator Frequency
Clock-Out Frequency = ------------------------------------------------------------------------------------
4 x [65536-(RCAP2H,RCAP2L)]
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to
when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate gen-
erator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one another since they both use
RCAP2H and RCAP2L.
Figure 15-1. Timer 2 in Clock-Out Mode
TL2
TH2
÷2
OSC
(8-BITS) (8-BITS)
TR2
RCAP2L RCAP2H
C/T2 BIT
P1.0
(T2)
÷2
T2OE (T2MOD.1)
TRANSITION
DETECTOR
P1.1
(T2EX)
TIMER 2
INTERRUPT
EXF2
EXEN2
17
1920C–MICRO–03/05
16. Interrupts
The AT89C51RC has a total of six interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all
shown in Figure 16-1.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that Table 14-1 shows that bit position IE.6 is unimplemented. User software should not
write 1s to these bit positions, since they may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-
ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag,
TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Table 16-1. Interrupt Enable (IE) Register
(MSB)
EA
(LSB)
–
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol
Position
Function
Disables all interrupts. If EA = 0, no interrupt is
acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or clearing its
enable bit.
EA
IE.7
–
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
Reserved.
ET2
ES
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
ET1
EX1
ET0
EX0
User software should never write 1s to reserved bits, because they may be used in future AT89
products.
18
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
Figure 16-1. Interrupt Sources
0
1
INT0
IE0
TF0
0
1
INT1
IE1
TF1
TI
RI
TF2
EXF2
17. Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be
configured for use as an on-chip oscillator, as shown in Figure 19-1. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven, as shown in Figure 19-2. There are no
requirements on the duty cycle of the external clock signal, since the input to the internal clock-
ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low
time specifications must be observed.
18. Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special functions regis-
ters remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-
gram execution from where it left off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when idle mode is terminated by a reset, the instruction following the one that invokes
idle mode should not write to a port pin or to external memory.
19
1920C–MICRO–03/05
19. Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the Power-down mode is terminated. Exit from Power-down can be initiated either
by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not
change the on-chip RAM. The reset should not be activated before VCC is restored to its normal
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.
Figure 19-1. Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
Note:
C1, C2 = 30 pF 10 pF for Crystals
= 40 pF 10 pF for Ceramic Resonators
Figure 19-2. External Clock Drive Configuration
NC
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
Table 19-1. Status of External Pins During Idle and Power-down Modes
Program
Mode
Memory
Internal
External
Internal
External
ALE
PSEN
PORT0
Data
PORT1
Data
PORT2
Data
PORT3
Data
Idle
1
1
0
0
1
1
0
0
Idle
Float
Data
Data
Address
Data
Data
Power-down
Power-down
Data
Data
Float
Data
Data
Data
20
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
20. Program Memory Lock Bits
The AT89C51RC has three lock bits that can be left unprogrammed (U) or can be programmed
(P) to obtain the additional features listed in Table 20-1.
Table 20-1. Lock Bit Protection Modes
Program Lock Bits
LB1
LB2
LB3
Protection Type
1
2
U
U
U
No program lock features
MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further
P
U
U
programming of the Flash memory is disabled
3
4
P
P
P
P
U
P
Same as mode 2, but verify is also disabled
Same as mode 3, but external execution is also disabled
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset.
If the device is powered up without a reset, the latch initializes to a random value and holds that
value until reset is activated. The latched value of EA must agree with the current logic level at
that pin in order for the device to function properly.
21. Programming the Flash
The AT89C51RC is shipped with the on-chip Flash memory array ready to be programmed. The
programming interface needs a high-voltage (12-volt) program enable signal and is compatible
with conventional third-party Flash or EPROM programmers.
The AT89C51RC code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89C51RC, the address, data, and con-
trol signals should be set up according to Table 22-1 and Figures 22-1 and 22-2. To program the
AT89C51RC, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-
write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1
through 5, changing the address and data for the entire array or until the end of the
object file is reached.
21
1920C–MICRO–03/05
Chip Erase Sequence: Before the AT89C51RC can be reprogrammed, a Chip Erase operation
needs to be performed. To erase the contents of the AT89C51RC, follow this sequence:
1. Raise VCC to 6.5V.
2. Pulse ALE/PROG once (duration of 200 ns - 500 ns) and wait for 150 ms.
3. Power VCC down and up to 6.5V.
4. Pulse ALE/PROG once (duration of 200 ns - 500 ns) and wait for 150 ms.
5. Power VCC down and up.
Data Polling: The AT89C51RC features Data Polling to indicate the end of a write cycle. During
a write cycle, an attempted read of the last byte written will result in the complement of the writ-
ten data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output
signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is
pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code
data can be read back via the address and data lines for verification. The status of the individual
lock bits can be verified directly by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-
mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to
a logic low. The values returned are as follows:
(000H) = 1EH indicates manufactured by Atmel
(100H) = 51H
(200H) = 07H indicates 89C51RC
22
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
22. Programming Interface
Every code byte in the Flash array can be programmed by using the appropriate combination of
control signals. The write operation cycle is self-timed and once initiated, will automatically time
itself to completion.
Most major worldwide programming vendors offer support for the Atmel AT89 microcontroller
series. Please contact your local programming vendor for the appropriate software revision.
Table 22-1. Flash Programming Modes
P3.4
P2.5-0
P1.7-0
ALE/
EA/
VPP
P0.7-0
Data
Mode
VCC
RST
PSEN
PROG
P2.6
P2.7
P3.3
P3.6
P3.7
Address
(1)
Write Code Data
5V
H
L
12 V
L
H
H
H
H
DIN
DOUT
X
A14
A14
X
A13-8
A7-0
A7-0
X
H/12
V
Read Code Data
Write Lock Bit 1
Write Lock Bit 2
Write Lock Bit 3
5V
H
H
H
H
L
L
L
L
H
L
L
H
H
L
L
H
H
L
H
H
L
A13-8
(2)
6.5V
6.5V
6.5V
12 V
12 V
12 V
H
H
H
H
H
H
X
X
X
(2)
(2)
X
X
X
H
L
X
X
X
P0.2,
P0.3,
P0.4
Read Lock Bits
1, 2, 3
5V
H
H
L
L
H
H
H
H
H
L
L
H
L
L
L
X
X
X
X
X
X
(3)
Chip Erase
6.5V
12V
H
X
Read Atmel ID
Read Device ID
Read Device ID
5V
5V
5V
H
H
H
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1EH
51H
07H
X
X
X
XX 0000
XX 0001
XX 0010
00H
00H
00H
Notes: 1. Write Code Data requires a 200 ns PROG pulse.
2. Write Lock Bits requires a 100 µs PROG pulse.
3. Chip Erase requires a 200 ns - 500 ns PROG pulse.
4. RDY/BSY signal is output on P3.0 during programming.
23
1920C–MICRO–03/05
Figure 22-1. Programming the Flash Memory
4.5V to 5.5V
AT89C51RC
VCC
P1.0 - P1.7
A0 - A7
ADDR.
0000H/7FFFH
A8 - A13
PGM
DATA
P2.0 - P2.5
P3.4
P0
A14*
P2.6
P2.7
P3.3
P3.6
P3.7
SEE FLASH
PROGRAMMING
MODES TABLE
ALE
PROG
XTAL2
EA
VIH/VPP
3 - 33 MHz
RDY/
BSY
P3.0
XTAL1
GND
RST
VIH
PSEN
Figure 22-2. Verifying the Flash Memory
4.5V to 5.5V
AT89C51RC
A0 - A7
ADDR.
0000H/7FFFH
VCC
P1.0 - P1.7
A8 - A13
PGM DATA
(USE 10K
PULL-UPS)
P0
P2.0 - P2.5
P3.4
P2.6
P2.7
A14*
ALE
SEE FLASH
P3.3
P3.6
P3.7
PROGRAMMING
MODES TABLE
VIH
XTAL2
EA
3 - 33 MHz
VIH
XTAL1
GND
RST
PSEN
Note:
*Programming address line A14 (P3.4) is not the same as the external memory address line A14
(P2.6).
24
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
23. Flash Programming and Verification Characteristics
TA = 20°C to 30°C, VCC = 4.5V to 5.5V
Symbol
VPP
Parameter
Min
Max
12.5
10
Units
V
Programming Supply Voltage
Programming Supply Current
VCC Supply Current
11.5
IPP
mA
mA
MHz
ICC
30
1/tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tAVQV
tELQV
tEHQZ
tGHBL
tWC
Oscillator Frequency
3
33
Address Setup to PROG Low
Address Hold after PROG
Data Setup to PROG Low
Data Hold after PROG
P2.7 (ENABLE) High to VPP
VPP Setup to PROG Low
VPP Hold after PROG
48tCLCL
48tCLCL
48tCLCL
48tCLCL
48tCLCL
10
µs
µs
µs
10
PROG Width
0.2
1
Address to Data Valid
ENABLE Low to Data Valid
Data Float after ENABLE
PROG High to BUSY Low
Byte Write Cycle Time
48tCLCL
48tCLCL
48tCLCL
1.0
0
µs
µs
80
25
1920C–MICRO–03/05
24. Flash Programming and Verification Waveforms
PROGRAMMING
VERIFICATION
ADDRESS
P1.0 - P1.7
P2.0 - P2.5
ADDRESS
tAVQV
P3.4
PORT 0
DATA IN
DATA OUT
tDVGL tGHDX
tAVGL
tSHGL
tGHAX
tGHSL
ALE/PROG
tGLGH
VPP
LOGIC 1
LOGIC 0
EA/VPP
tEHSH
tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.0
(RDY/BSY)
BUSY
tWC
READY
25. Lock Bit Programming
Test Conditions
Setup
Lockbit_1, 2 or 3
Data Setup
100 µs
ALE/PROG
V
= 4.5V to 5.5V
CC
V
= 6.5V
CC
Wait 10 ms to reload
new lock bit status
26. Parallel Chip Erase Mode
Test Conditions
Setup
Test Conditions Setup
200 ns
200 ns
ALE/PROG
DC
Erase
DC
Erase
P3<0>
= 6.5V
Erase
Erase
V
= 4.5V to 5.5V
CC
V
CC
Wait 10 ms before
reprogramming
10 ms
26
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
27. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
DC Output Current...................................................... 15.0 mA
28. DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 4.0V to 5.5V, unless otherwise noted.
Symbol
VIL
Parameter
Condition
Min
-0.5
Max
0.2 VCC-0.1
0.2 VCC-0.3
VCC+0.5
VCC+0.5
0.45
Units
Input Low-voltage
(Except EA)
V
V
V
V
V
VIL1
Input Low-voltage (EA)
Input High-voltage
-0.5
VIH
(Except XTAL1, RST)
(XTAL1, RST)
0.2 VCC+0.9
0.7 VCC
VIH1
VOL
Input High-voltage
Output Low-voltage(1) (Ports 1,2,3)
IOL = 1.6 mA
Output Low-voltage(1)
(Port 0, ALE, PSEN)
VOL1
IOL = 3.2 mA
0.45
V
I
OH = -60 µA, VCC = 5V 10%
OH = -25 µA
2.4
V
V
V
V
V
V
Output High-voltage
(Ports 1,2,3, ALE, PSEN)
VOH
I
0.75 VCC
0.9 VCC
2.4
IOH = -10 µA
IOH = -800 µA, VCC = 5V 10%
Output High-voltage
(Port 0 in External Bus Mode)
VOH1
IOH = -300 µA
0.75 VCC
0.9 VCC
IOH = -80 µA
VIN = 0.45V
Logical 0 Input Current (Ports
1,2,3)
IIL
-50
µA
µA
Logical 1 to 0 Transition Current
(Ports 1,2,3)
ITL
VIN = 2V, VCC = 5V 10%
-650
ILI
Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC
Reset Pull-down Resistor
10
30
µA
kΩ
pF
RRST
CIO
10
Pin Capacitance
Test Freq. = 1 MHz, TA = 25°C
10
Active Mode, 12 MHz
Idle Mode, 12 MHz
VCC = 5.5V
25
mA
mA
µA
Power Supply Current
Power-down Mode(1)
ICC
6.5
100
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.
27
1920C–MICRO–03/05
29. AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
29.1 External Program and Data Memory Characteristics
12 MHz Oscillator
Variable Oscillator
Symbol
1/tCLCL
tLHLL
Parameter
Min
Max
Min
0
Max
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator Frequency
33
ALE Pulse Width
127
43
2tCLCL-40
tCLCL-25
tCLCL-25
tAVLL
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
tLLAX
tLLIV
48
233
4tCLCL-65
tLLPL
43
tCLCL-25
tPLPH
tPLIV
205
3tCLCL-45
PSEN Low to Valid Instruction In
Input Instruction Hold after PSEN
Input Instruction Float after PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
145
59
3tCLCL-60
tCLCL-25
tPXIX
0
0
tPXIZ
tPXAV
tAVIV
75
tCLCL-8
312
10
5tCLCL-80
10
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
400
400
6tCLCL-100
6tCLCL-100
WR Pulse Width
RD Low to Valid Data In
Data Hold after RD
252
5tCLCL-90
0
0
Data Float after RD
97
2tCLCL-28
8tCLCL-150
9tCLCL-165
3tCLCL+50
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold after WR
517
585
300
200
203
23
3tCLCL-50
4tCLCL-75
tCLCL-30
433
33
7tCLCL-130
tCLCL-25
RD Low to Address Float
RD or WR High to ALE High
0
0
43
123
tCLCL-25
tCLCL+25
28
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
30. External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL
tLLIV
tPLIV
tLLPL
PSEN
tPXAV
tPLAZ
tPXIZ
tPXIX
INSTR IN
tLLAX
A0 - A7
tAVIV
A0 - A7
PORT 0
PORT 2
A8 - A15
A8 - A15
31. External Data Memory Read Cycle
tLHLL
ALE
tWHLH
PSEN
tLLDV
tRLRH
tLLWL
RD
tLLAX
tRHDZ
tRHDX
tRLDV
tAVLL
tRLAZ
A0 - A7 FROM RI OR DPL
DATA IN
A0 - A7 FROM PCL
INSTR IN
PORT 0
tAVWL
tAVDV
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
PORT 2
29
1920C–MICRO–03/05
32. External Data Memory Write Cycle
tLHLL
ALE
tWHLH
PSEN
tLLWL
tWLWH
WR
tLLAX
tQVWX
tWHQX
tAVLL
tQVWH
A0 - A7 FROM RI OR DPL
DATA OUT
A0 - A7 FROM PCL
INSTR IN
PORT 0
PORT 2
tAVWL
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
33. External Clock Drive Waveforms
tCHCX
tCHCX
tCLCH
tCHCL
VCC - 0.5V
0.7 VCC
0.2 VCC - 0.1V
0.45V
tCLCX
tCLCL
34. External Clock Drive
Symbol
1/tCLCL
tCLCL
Parameter
Oscillator Frequency
Clock Period
High Time
Min
0
Max
Units
33
MHz
ns
30
12
12
tCHCX
tCLCX
ns
Low Time
ns
tCLCH
Rise Time
5
5
ns
tCHCL
Fall Time
ns
30
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
35. Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF.
12 MHz Osc
Variable Oscillator
Symbol
tXLXL
Parameter
Min
Max
Min
12tCLCL
Max
Units
µs
Serial Port Clock Cycle Time
1.0
700
50
0
tQVXH
tXHQX
tXHDX
tXHDV
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
10tCLCL - 133
2tCLCL - 80
0
ns
ns
ns
700
10tCLCL - 133
ns
36. Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
tXHQX
WRITE TO SBUF
0
1
2
3
4
5
6
7
tXHDX
SET TI
tXHDV
OUTPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
INPUT DATA
37. AC Testing Input/Output Waveforms(1)
VCC - 0.5V
0.2 VCC + 0.9V
TEST POINTS
0.2 VCC - 0.1V
0.45V
Note:
1. AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1
and VIL max. for a logic 0.
38. Float Waveforms(1)
+ 0.1V
- 0.1V
- 0.1V
+ 0.1V
VOL
VLOAD
Timing Reference
Points
VLOAD
VLOAD
VOL
Note:
1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage
occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level
occurs.
31
1920C–MICRO–03/05
39. Ordering Information
39.1 Standard Package
Speed
(MHz)
Power
Supply
Ordering Code
Package
Operation Range
AT89C51RC-24AC
AT89C51RC-24JC
AT89C51RC-24PC
44A
44J
Commercial
(0°C to 70°C)
40P6
24
33
4.0V to 5.5V
4.5V to 5.5V
AT89C51RC-24AI
AT89C51RC-24JI
AT89C51RC-24PI
44A
44J
Industrial
(-40°C to 85°C)
40P6
AT89C51RC-33AC
AT89C51RC-33JC
AT89C51RC-33PC
44A
44J
Commercial
(0°C to 70°C)
40P6
39.2 Green Package Option (Pb/Halide-free)
Speed
(MHz)
Power
Supply
Ordering Code
Package
Operation Range
AT89C51RC-24AU
AT89C51RC-24JU
AT89C51RC-24PU
44A
44J
Industrial
24
4.0V to 5.5V
(-40°C to 85°C)
40P6
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
44J
40P6
40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
40. Package Information
40.1 44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
33
1920C–MICRO–03/05
40.2 44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
44J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
34
AT89C51RC
1920C–MICRO–03/05
AT89C51RC
40.3 40P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
52.070
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
52.578 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
40P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
35
1920C–MICRO–03/05
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not
intended, authorized, or warranted for use as components in applications intended to support or sustain life.
© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, and others, are registered trademarks, and
Everywhere You AreSM and others are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be
trademarks of others.
Printed on recycled paper.
1920C–MICRO–03/05
xM
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明