AT87F55-24JC [ATMEL]
Microcontroller, 8-Bit, FLASH, 8051 CPU, 24MHz, CMOS, PQCC44, PLASTIC, LCC-44;
| 型号： | AT87F55-24JC |
| 厂家： | 
ATMEL |
| 描述： | Microcontroller, 8-Bit, FLASH, 8051 CPU, 24MHz, CMOS, PQCC44, PLASTIC, LCC-44 时钟 微控制器 外围集成电路 |
| 文件： | 总27页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Compatible with MCS-51™ Products
• 20K Bytes of One-time Programmable QuickFlash™ Memory
• 4V to 6V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Programmable Serial Channel
• Low-power Idle and Power Down Modes
• Interrupt Recovery from Power Down
• Hardware Watchdog Timer
8-bit
Microcontroller
with 20K Bytes
QuickFlash™
• Dual Data Pointer
• Power-off Flag
Description
The AT87F55 is a low-power, high-performance CMOS 8-bit microcomputer with 20K
bytes of QuickFlash one-time programmable (OTP) read only memory and 256 bytes
of RAM. The device is manufactured using Atmel’s high-density nonvolatile memory
technology and is compatible with the industry standard 80C51 and 80C52 instruction
set and pinout. The on-chip QuickFlash allows the program memory to be user pro-
(continued)
AT87F55
Preliminary
Pin Configurations
PDIP
(T2) P1.0
(T2EX) P1.1
P1.2
1
2
3
4
5
6
7
8
9
40 VCC
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
P1.3
P1.4
P1.5
TQFP
P1.6
P1.7
RST
(RXD) P3.0 10
(TXD) P3.1 11
(INT0) P3.2 12
(INT1) P3.3 13
(T0) P3.4 14
(T1) P3.5 15
(WR) P3.6 16
(RD) P3.7 17
XTAL2 18
30 ALE/PROG
29 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
P1.5
P1.6
1
2
3
4
5
6
7
8
9
33 P0.4 (AD4)
32 P0.5 (AD5)
31 P0.6 (AD6)
30 P0.7 (AD7)
29 EA/VPP
P1.7
RST
(RXD) P3.0
NC
XTAL1 19
28 NC
GND 20
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
27 ALE/PROG
26 PSEN
25 P2.7 (A15)
24 P2.6 (A14)
23 P2.5 (A13)
PLCC
(T0) P3.4 10
(T1) P3.5 11
P1.5
P1.6
P1.7
7
8
9
39 P0.4 (AD4)
38 P0.5 (AD5)
37 P0.6 (AD6)
36 P0.7 (AD7)
35 EA/VPP
34 NC
RST 10
(RXD) P3.0 11
NC 12
(TXD) P3.1 13
(INT0) P3.2 14
(INT1) P3.3 15
(T0) P3.4 16
(T1) P3.5 17
33 ALE/PROG
32 PSEN
31 P2.7 (A15)
30 P2.6 (A14)
29 P2.5 (A13)
Rev. 1147B–02/00
grammed by a conventional nonvolatile memory program-
mer. By combining a versatile 8-bit CPU with QuickFlash
on a monolithic chip, the Atmel AT87F55 is a powerful
microcomputer which provides a highly flexible and cost
effective solution to many embedded control applications.
Block Diagram
P0.0 - P0.7
P2.0 - P2.7
VCC
PORT 0 DRIVERS
PORT 2 DRIVERS
GND
RAM ADDR.
PORT 0
PORT 2
LATCH
QUICK
FLASH
RAM
REGISTER
LATCH
PROGRAM
ADDRESS
REGISTER
STACK
POINTER
B
ACC
REGISTER
BUFFER
TMP2
TMP1
PC
INCREMENTER
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PROGRAM
COUNTER
PSW
PSEN
ALE/PROG
EA / VPP
RST
TIMING
AND
CONTROL
DUAL
DPTR
INSTRUCTION
REGISTER
PORT 1
LATCH
PORT 3
LATCH
WATCH
DOG
OSC
PORT 1 DRIVERS
P1.0 - P1.7
PORT 3 DRIVERS
P3.0 - P3.7
AT87F55
2
AT87F55
The AT87F55 provides the following standard features:
20K bytes of QuickFlash, 256 bytes of RAM, 32 I/O lines,
three 16-bit timer/counters, a six-vector, two-level interrupt
architecture, a full-duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT87F55 is designed with
static logic for operation down to zero frequency and sup-
ports two software selectable power saving modes. The
Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue
functioning. The Power Down Mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip func-
tions until the next external interrupt or hardware reset.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pul-
lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
Pin Description
VCC
Supply voltage.
Port 2 also receives the high-order address bits and some
control signals during QuickFlash programming and verifi-
cation.
GND
Ground.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pullups.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode, P0 has internal pul-
lups.
Port 3 also serves the functions of various special features
of the AT87F55, as shown in the following table.
Port 3 also receives some control signals for QuickFlash
programming and verification.
Port 0 also receives the code bytes during QuickFlash pro-
gramming and outputs the code bytes during program veri-
fication. External pullups are required during program
verification.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
Port 1
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device. This pin drives
High for 96 oscillator periods after the Watchdog times out.
The DISRTO bit in SFR AUXR (address 8EH) can be used
to disable this feature. In the default state of bit DISTRO,
the RESET HIGH out feature is enabled.
Port 1 also receives the low-order address bytes during
QuickFlash programming and verification.
Port Pin
Alternate Functions
T2 (external count input to Timer/Counter 2),
clock-out
P1.0
ALE/PROG
T2EX (Timer/Counter 2 capture/reload trigger
and direction control)
P1.1
Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem-
3
ory. This pin is also the program pulse input (PROG) during
QuickFlash programming.
cycle, except that two PSEN activations are skipped during
each access to external data memory.
In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data mem-
ory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
EA should be strapped to VCC for internal program execu-
tions.
This pin also receives the 12-volt programming enable volt-
age (VPP) during QuickFlash programming.
PSEN
XTAL1
Program Store Enable is the read strobe to external pro-
gram memory.
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
When the AT87F55 is executing code from external pro-
gram memory, PSEN is activated twice each machine
XTAL2
Output from the inverting oscillator amplifier.
Table 1. AT87F55 SFR Map and Reset Values
0F8H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
B
0F0H
00000000
0E8H
ACC
0E0H
00000000
0D8H
PSW
0D0H
00000000
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
AUXR1
XXXXXXX0
WDTRST
XXXXXXXX
SCON
00000000
SBUF
XXXXXXXX
P1
11111111
90H
97H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
AUXR
XXX00XX0
88H
8FH
P0
11111111
SP
00000111
DP0L
00000000
DP0H
00000000
DP1L
00000000
DP1H
00000000
PCON
0XXX0000
80H
87H
AT87F55
4
AT87F55
Special Function Registers
A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.
new features. In that case, the reset or inactive values of
the new bits will always be 0.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.
Timer 2 Registers: Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L)
are the Capture/Reload registers for Timer 2 in 16-bit cap-
ture mode or 16-bit auto-reload mode.
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
Interrupt Registers: The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.
Table 2. T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H
Reset Value = 0000 0000B
Bit Addressable
Bit
TF2
7
EXF2
6
RCLK
5
TCLK
4
EXEN2
3
TR2
2
C/T2
1
CP/RL2
0
Symbol Function
TF2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1
or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK
TCLK
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer
2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
CP/RL2
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
5
Table 3a. AUXR: Auxiliary Register
AUXR
Address = 8EH
Not Bit Addressable
—
Reset Value = XXX00XX0B
—
—
WDIDLE
4
DISRTO
3
—
—
DISALE
0
Bit
7
6
5
2
1
—
Reserved for future expansion
Disable/Enable ALE
DISALE
DISALE
Operating Mode
0
1
ALE is emitted at a constant rate of 1/6 the oscillator frequency
ALE is active only during a MOVX or MOVC instruction
DISTRO
WDIDLE
Disable/Enable Reset out
DISRTO
0
1
Reset pin is driven High after WDT times out
Reset pin is input only
Disable/Enable WDT in IDLE mode
WDIDLE
0
1
WDT continues to count in IDLE mode
WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both
internal and external data memory, two banks of 16-bit
Data Pointer Registers are provided: DP0 at SFR address
locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in
SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The
user should always initialize the DPS bit to the appropriate
value before accessing the respective Data Pointer Regis-
ter.
Power Off Flag: The Power Off Flag (POF) is located at bit
4 (PCON.4) in the PCON SFR. POF is set to “1” during
power up. It can be set and rest under software control and
is not affected by reset.
AT87F55
6
AT87F55
Table 3b. AUXR1: Auxiliary Register 1
AUXR1
Address = A2H
Not Bit Addressable
—
Reset Value = XXXXXXX0B
—
—
—
—
—
—
DPS
0
Bit
7
6
5
4
3
2
1
—
Reserved for future expansion
Data Pointer Register Select
DPS
DPS
0
1
Selects DPTR Registers DP0L, DP0H
Selects DPTR Registers DP1L, DP1H
7
Memory Organization
MCS-51 devices have a separate address space for Pro-
gram and Data Memory. Up to 64 Kbytes each of external
Program and Data Memory can be addressed.
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.
Program Memory
If the EA pin is connected to GND, all program fetches are
directed to external memory.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
On the AT87F55, if EA is connected to VCC, program
fetches to addresses 0000H through 4FFFH are directed to
internal memory and fetches to addresses 5000H through
FFFFH are to external memory.
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).
Data Memory
The AT87F55 implements 256 bytes of on-chip RAM. The
upper 128 bytes occupy a parallel address space to the
Special Function Registers. That means the upper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.
MOV @R0, #data
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail-
able as stack space.
AT87F55
8
AT87F55
To ensure that the WDT does not overflow within a few
states of exiting Power Down, it is best to reset the WDT
just before entering Power Down.
Hardware Watchdog Timer
(One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations
where the CPU may be subjected to software upsets. The
WDT consists of a 14-bit counter and the WatchDog Timer
Reset (WDTRST) SFR. The WDT is defaulted to disable
from exiting reset. To enable the WDT, a user must write
01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, it will
increment every machine cycle while the oscillator is run-
ning. There is no way to disable the WDT except through
reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse
at the RST pin.
Before going into the IDLE mode, the WDIDLE bit in SFR
AUXR is used to determine whether the WDT continues to
count if enabled. The WDT keeps counting during IDLE
(WDIDLE bit = 0) as the default state. To prevent the WDT
from resetting the AT87F55 while in IDLE mode, the user
should always set up a timer that will periodically exit IDLE,
service the WDT, and reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in
IDLE mode and resumes the count upon exit from IDLE.
UART
The UART in the AT87F55 operates the same way as the
UART in the AT87F51 and AT87F52. For further informa-
tion, see the December 1997 Microcontroller Data Book,
page 2-48, section titled, “Serial Interface”.
Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in
sequence to the WDTRST register (SFR location 0A6H).
When the WDT is enabled, the user needs to service it by
writing 01EH and 0E1H to WDTRST to avoid a WDT over-
flow. The 14-bit counter overflows when it reaches 16383
(3FFFH), and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the
oscillator is running. This means the user must reset the
WDT at least every 16383 machine cycles. To reset the
WDT the user must write 01EH and 0E1H to WDTRST.
WDTRST is a write-only register. The WDT counter cannot
be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST pin. The RESET pulse
duration is 98xTOSC, where TOSC=1/FOSC. To make the
best use of the WDT, it should be serviced in those sec-
tions of code that will periodically be executed within the
time required to prevent a WDT reset.
Timer 0 and 1
Timer 0 and Timer 1 in the AT87F55 operate the same way
as Timer 0 and Timer 1 in the AT87F51 and AT87F52.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 4.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12 oscil-
lator periods, the count rate is 1/12 of the oscillator fre-
quency.
WDT During Power Down and Idle
In Power Down mode the oscillator stops, which means the
WDT also stops. While in Power Down mode, the user
does not need to service the WDT. There are two methods
of exiting Power Down mode: by a hardware reset or via a
level-activated external interrupt which is enabled prior to
entering Power Down mode. When Power Down is exited
with hardware reset, servicing the WDT should occur as it
normally does whenever the AT87F55 is reset. Exiting
Power Down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabi-
lize. When the interrupt is brought high, the interrupt is ser-
viced. To prevent the WDT from resetting the device while
the interrupt pin is held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the WDT be
reset during the interrupt service for the interrupt used to
exit Power Down.
Table 4. Timer 2 Operating Modes
RCLK +TCLK
CP/RL2
TR2
1
MODE
0
0
1
X
0
1
16-bit Auto-Reload
16-bit Capture
Baud Rate Generator
(Off)
1
X
X
1
0
In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
9
the transition was detected. Since two machine cycles (24
oscillator periods) are required to recognize a 1-to-0 transi-
tion, the maximum count rate is 1/24 of the oscillator fre-
quency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least
one full machine cycle.
rent value in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, respectively. In addition, the transition at T2EX
causes bit EXF2 in T2CON to be set. The EXF2 bit, like
TF2, can generate an interrupt. The capture mode is illus-
trated in Figure 5.
Auto-reload (Up or Down Counter)
Capture Mode
Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 5). Upon reset, the DCEN bit
is set to 0 so that timer 2 will default to count up. When
DCEN is set, Timer 2 can count up or down, depending on
the value of the T2EX pin.
In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 performs the same operation, but a 1-
to-0 transition at external input T2EX also causes the cur-
Figure 5. Timer in Capture Mode
÷12
OSC
C/T2 = 0
C/T2 = 1
TH2
TL2
TF2
OVERFLOW
CONTROL
TR2
CAPTURE
T2 PIN
RCAP2H RCAP2L
EXF2
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
T2EX PIN
CONTROL
EXEN2
Figure 6 shows Timer 2 automatically counting up when
DCEN=0. In this mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The
overflow also causes the timer registers to be reloaded with
the 16-bit value in RCAP2H and RCAP2L. The values in
Timer in Capture ModeRCAP2H and RCAP2L are preset
by software. If EXEN2 = 1, a 16-bit reload can be triggered
either by an overflow or by a 1-to-0 transition at external
input T2EX. This transition also sets the EXF2 bit. Both the
TF2 and EXF2 bits can generate an interrupt if enabled.
the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overflow also causes the 16-bit value in
RCAP2H and RCAP2L to be reloaded into the timer regis-
ters, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal the values stored in
RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or
underflows and can be used as a 17th bit of resolution. In
this operating mode, EXF2 does not flag an interrupt.
Setting the DCEN bit enables Timer 2 to count up or down,
as shown in Figure 6. In this mode, the T2EX pin controls
AT87F55
10
AT87F55
Figure 6. Timer 2 Auto Reload Mode (DCEN = 0)
12
OSC
C/T2 = 0
TH2
TL2
OVERFLOW
CONTROL
TR2
C/T2 = 1
RELOAD
T2 PIN
TIMER 2
INTERRUPT
RCAP2H RCAP2L
TF2
TRANSITION
DETECTOR
EXF2
T2EX PIN
CONTROL
EXEN2
Table 5. T2MOD—Timer 2 Mode Control Register
T2MOD Address = 0C9H
Not Bit Addressable
Reset Value = XXXX XX00B
—
—
—
—
—
—
T2OE
1
DCEN
0
Bit
7
6
5
4
3
2
Symbol
—
Function
Not implemented, reserved for future
Timer 2 Output Enable bit.
T2OE
DCEN
When set, this bit allows Timer 2 to be configured as an up/down counter.
11
Figure 7. Timer 2 Auto Reload Mode (DCEN = 1)
TOGGLE
(DOWN COUNTING RELOAD VALUE)
0FFH 0FFH
EXF2
OSC
12
OVERFLOW
C/T2 = 0
TH2
TL2
TF2
CONTROL
TR2
TIMER 2
INTERRUPT
C/T2 = 1
T2 PIN
RCAP2H RCAP2L
(UP COUNTING RELOAD VALUE)
COUNT
DIRECTION
1=UP
0=DO
T2EX PIN
Figure 8. Timer 2 in Baud Rate Generator Mode
TIMER 1 OVERFLOW
2
÷
"0"
"0"
"1"
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
SMOD1
RCLK
2
OSC
÷
C/T2 = 0
"1"
"1"
TH2
TL2
Rx
CLOCK
CONTROL
TR2
÷
16
C/T2 = 1
"0"
T2 PIN
TCLK
RCAP2H RCAP2L
Tx
CLOCK
TRANSITION
DETECTOR
16
÷
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
AT87F55
12
AT87F55
Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON (Table 2). Note that the
baud rates for transmit and receive can be different if Timer
2 is used for the receiver or transmitter and Timer 1 is used
for the other function. Setting RCLK and/or TCLK puts
Timer 2 into its baud rate generator mode, as shown in Fig-
ure 8.
increments every state time (at 1/2 the oscillator fre-
quency). The baud rate formula is given below.
Modes 1 and 3
Oscillator Frequency
--------------------------------------- = -------------------------------------------------------------------------------------
Baud Rate 32 x [65536-RCAP2H,RCAP2L)]
The baud rate generator mode is similar to the auto-reload
mode, in that a rollover in TH2 causes the Timer 2 registers
to be reloaded with the 16-bit value in registers RCAP2H
and RCAP2L, which are preset by software.
where (RCAP2H, RCAP2L) is the content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 8. This
figure is valid only if RCLK or TCLK = 1 in T2CON. Note
that a rollover in TH2 does not set TF2 and will not gener-
ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0
transition in T2EX will set EXF2 but will not cause a reload
from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer
2 is in use as a baud rate generator, T2EX can be used as
an extra external interrupt.
The baud rates in Modes 1 and 3 are determined by Timer
2’s overflow rate according to the following equation.
Timer 2 Overflow Rate
Mdes 1 and 3 Baud Rates = -----------------------------------------------------------
16
Note that when Timer 2 is running (TR2 = 1) as a timer in
the baud rate generator mode, TH2 or TL2 should not be
read from or written to. Under these conditions, the Timer is
incremented every state time, and the results of a read or
write may not be accurate. The RCAP2 registers may be
read but should not be written to, because a write might
overlap a reload and cause write and/or reload errors. The
timer should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.
The Timer can be configured for either timer or counter
operation. In most applications, it is configured for timer
operation (CP/T2 = 0). The timer operation is different for
Timer 2 when it is used as a baud rate generator. Normally,
as a timer, it increments every machine cycle (at 1/12 the
oscillator frequency). As a baud rate generator, however, it
Figure 9. Timer 2 in Clock-Out Mode
TL2
TH2
2
OSC
(8-BITS) (8-BITS)
TR2
RCAP2L RCAP2H
C/T2 BIT
P1.0
(T2)
2
T2OE (T2MOD.1)
TRANSITION
DETECTOR
P1.1
(T2EX)
TIMER 2
INTERRUPT
EXF2
EXEN2
13
Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on
P1.0, as shown in Figure 9. This pin, besides being a regu-
lar I/O pin, has two alternate functions. It can be pro-
grammed to input the external clock for Timer/Counter 2 or
to output a 50% duty cycle clock ranging from 61 Hz to 4
MHz at a 16 MHz operating frequency.
Table 6. Interrupt Enable (IE) Register
(MSB)
(LSB)
EX0
EA
—
ET2
ES
ET1
EX1
ET0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
To configure the Timer/Counter 2 as a clock generator, bit
C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)
must be set. Bit TR2 (T2CON.2) starts and stops the timer.
Symbol
Position
Function
EA
IE.7
Disables all interrupts. If EA = 0,
no interrupt is acknowledged. If
EA = 1, each interrupt source is
individually enabled or disabled
by setting or clearing its enable
bit.
The clock-out frequency depends on the oscillator fre-
quency and the reload value of Timer 2 capture registers
(RCAP2H, RCAP2L), as shown in the following equation.
Oscillator Frequency
Clock-Out Frequency = ------------------------------------------------------------------------------------
4 x [65536-(RCAP2H,RCAP2L)]
—
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
Reserved.
ET2
ES
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
In the clock-out mode, Timer 2 roll-overs will not generate
an interrupt. This behavior is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2
as a baud-rate generator and a clock generator simulta-
neously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.
ET1
EX1
ET0
EX0
User software should never write 1s to unimplemented bits,
because they may be used in future AT87 products.
Interrupts
The AT87F55 has a total of six interrupt vectors: two exter-
nal interrupts (INT0 and INT1), three timer interrupts (Tim-
ers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 10.
Figure 10. Interrupt Sources
0
INT0
IE0
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
1
Note that Table 5 shows that bit position IE.6 is unimple-
mented. In the AT87F55, bit position IE.5 is also unimple-
mented. User software should not write 1s to these bit
positions, since they may be used in future AT89 products.
TF0
0
1
Timer 2 interrupt is generated by the logical OR of bits TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
INT1
IE1
TF1
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.
TI
RI
TF2
EXF2
AT87F55
14
AT87F55
its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier that can be configured for use as
an on-chip oscillator, as shown in Figure 11. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven, as shown in Figure 12.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
Figure 11. Oscillator Connections
C2
XTAL2
C1
XTAL1
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
GND
Note:
C1, C2 = 30 pF 10 pF for Crystals
Note that when idle mode is terminated by a hardware
reset, the device normally resumes program execution
from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when idle mode is termi-
nated by a reset, the instruction following the one that
invokes idle mode should not write to a port pin or to exter-
nal memory.
= 40 pF 10 pF for Ceramic Resonators
Figure 12. External Clock Drive Configuration
NC
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
Power Down Mode
In the power down mode, the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. Exit from power down can be initiated either by a
hardware reset or by an enabled external interrupt. Reset
redefines the SFRs but does not change the on-chip RAM.
The reset should not be activated before VCC is restored to
Table 7. Status of External Pins During Idle and Power Down Modes
Mode
Program Memory
Internal
ALE
PSEN
PORT0
Data
PORT1
Data
PORT2
Data
PORT3
Data
Idle
1
1
0
0
1
1
0
0
Idle
External
Float
Data
Data
Address
Data
Data
Power Down
Power Down
Internal
Data
Data
External
Float
Data
Data
Data
15
set up according to the QuickFlash programming mode
table and Figure 13 and Figure 14. To program the
AT87F55, take the following steps:
Program Memory Lock Bits
The AT87F55 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the following table.
1. Input the desired memory location on the address
lines.
Table 8. Lock Bit Protection Modes
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
Program Lock Bits
LB1
LB2
LB3
Protection Type
1
2
U
U
U
No program lock features.
5. Pulse ALE/PROG once to program a byte in the
QuickFlash array or the lock bits. The byte-write
cycle is self-timed and typically takes no more than
50 µs. Repeat steps 1 through 5, changing the
address and data for the entire array or until the end
of the object file is reached.
MOVC instructions executed
from external program
memory are disabled from
fetching code bytes from
internal memory, EA is
sampled and latched on reset,
and further programming of
the QuickFlash memory is
disabled.
P
U
U
Data Polling: The AT87F55 features Data Polling to indi-
cate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on P0.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Same as mode 2, but verify is
also disabled.
3
4
P
P
P
P
U
P
Same as mode 3, but external
execution is also disabled.
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.0 is pulled
low after ALE goes high during programming to indicate
BUSY. P3.0 is pulled high again when programming is
done to indicate READY.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level
at that pin in order for the device to function properly.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is
achieved by observing that their features are enabled.
Programming the QuickFlash
The AT87F55 is shipped with the on-chip QuickFlash mem-
ory array ready to be programmed. The programming inter-
face needs a high-voltage (12-volt) program enable signal
and is compatible with conventional third-party Flash or
EPROM programmers.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 000H, 100H, and 200H, except that P3.6 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
The AT87F55 code memory array is programmed byte-by-
byte.
(000H) = 1EH indicates manufactured by Atmel
(100H) = 87H indicates 87F family
(200H) = 07H indicates 87F55
Programming Algorithm: Before programming the
AT87F55, the address, data, and control signals should be
AT87F55
16
AT87F55
Programming Interface
Every code byte in the QuickFlash array can be pro-
grammed by using the appropriate combination of control
signals. The write operation cycle is self-timed and once
initiated, will automatically time itself to completion.
All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.
Table 9. QuickFlash Programming Modes
P3.4
P2.5-0
Address
A13-8
A13-8
X
P1.7-0
ALE/
EA/
VPP
P0.7-0
Data
Mode
VCC
5V
RST
H
PSEN
PROG
P2.6
L
P2.7
H
P3.3
H
P3.6
H
P3.7
H
Write Code Data
Read Code Data
Write Lock Bit 1
Write Lock Bit 2
Write Lock Bit 3
Read Lock Bits
1, 2, 3
L
L
L
L
L
12V
H/12V
12V
DIN
DOUT
X
A14
A14
X
A7-0
A7-0
X
5V
H
H
L
L
L
H
H
6.5V
6.5V
6.5V
H
H
H
H
H
H
H
12V
H
H
H
L
L
X
X
X
X
H
12V
H
L
H
H
L
X
X
X
X
5V
5V
5V
5V
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
D2, 3, 4
1EH
X
X
X
X
X
X
X
X
X
Read Atmel ID
Read Device ID
Read Device ID
000H
100H
200H
87H
07H
Notes: 1. Each Prog/pulse is 200 ns for Write Code Data and 100 µs for Write Lock Bits.
2. RDY/BSY signal is output on P3.0 during programming.
17
Figure 13. Programming the QuickFlash Memory
Figure 14. Verifying the QuickFlash Memory
+5V
+5V
AT87F55
AT87F55
A0 - A7
A8 - A13
A0 - A7
A8 - A13
VCC
P0
VCC
P0
ADDR.
0000H/4FFFH
P1.0-P1.7
ADDR.
0000H/4FFFH
P1.0-P1.7
PGM DATA
(USE 10K
PULLUPS)
PGM
DATA
P2.0 - P2.5
P3.4
P2.6
P2.7
P2.0 - P2.5
P3.4
A14*
A14*
P2.6
P2.7
P3.3
P3.6
P3.7
ALE
EA
SEE FLASH
PROGRAMMING
MODES TABLE
SEE FLASH
PROGRAMMING
MODES TABLE
ALE
PROG
P3.3
P3.6
P3.7
VIH
XTAL2
XTAL2
EA
VIH/VPP
3-33 MHz
3-33 MHz
RDY/
BSY
P3.0
VIH
XTAL1
GND
RST
XTAL1
GND
RST
VIH
PSEN
PSEN
*Programming address line A14 (P3.4) is not the same as the external memory address line A14 (P2.6).
QuickFlash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 10%
Symbol
VPP
Parameter
Min
Max
12.0
10
Units
V
Programming Supply Voltage
Programming Supply Current
VCC Supply Current
11.5
IPP
mA
mA
MHz
ICC
30
1/tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tAVQV
tELQV
tEHQZ
tGHBL
tWC
Oscillator Frequency
3
33
Address Setup to PROG Low
Address Hold After PROG
Data Setup to PROG Low
Data Hold After PROG
P2.7 (ENABLE) High to VPP
VPP Setup to PROG Low
VPP Hold After PROG
PROG Width
48tCLCL
48tCLCL
48tCLCL
48tCLCL
48tCLCL
10
µs
µs
µs
10
0.2
1
Address to Data Valid
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to BUSY Low
Byte Write Cycle Time
48tCLCL
48tCLCL
48tCLCL
1.0
0
µs
µs
80
AT87F55
18
AT87F55
QuickFlash Programming and Verification Waveforms
PROGRAMMING
VERIFICATION
ADDRESS
P1.0 - P1.7
P2.0 - P2.5
ADDRESS
tAVQV
P3.4
PORT 0
DATA IN
DATA OUT
tDVGL tGHDX
tAVGL
tSHGL
tGHAX
tGHSL
ALE/PROG
tGLGH
VPP
LOGIC 1
LOGIC 0
EA/VPP
tEHSH
tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.0
(RDY/BSY)
BUSY
tWC
READY
19
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
DC Output Current...................................................... 15.0 mA
DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V 20%, unless otherwise noted.
Symbol
VIL
Parameter
Condition
Min
-0.5
Max
Units
Input Low Voltage
(Except EA)
0.2 VCC-0.1
0.2 VCC-0.3
VCC+0.5
VCC+0.5
0.45
V
V
V
V
V
VIL1
Input Low Voltage (EA)
Input High Voltage
-0.5
VIH
(Except XTAL1, RST)
(XTAL1, RST)
0.2 VCC+0.9
0.7 VCC
VIH1
VOL
Input High Voltage
Output Low Voltage(1) (Ports 1,2,3)
IOL = 1.6 mA
Output Low Voltage(1)
(Port 0, ALE, PSEN)
VOL1
IOL = 3.2 mA
0.45
V
I
OH = -60 µA, VCC = 5V 10%
OH = -25 µA
2.4
V
V
Output High Voltage
(Ports 1,2,3, ALE, PSEN)
VOH
I
0.75 VCC
0.9 VCC
2.4
IOH = -10 µA
V
IOH = -800 µA, VCC = 5V 10%
V
Output High Voltage
(Port 0 in External Bus Mode)
VOH1
I
OH = -300 µA
0.75 VCC
0.9 VCC
V
IOH = -80 µA
V
IIL
Logical 0 Input Current (Ports 1,2,3)
VIN = 0.45V
-50
µA
Logical 1 to 0 Transition Current
(Ports 1,2,3)
ITL
VIN = 2V, VCC = 5V 10%
0.45 < VIN < VCC
-650
µA
ILI
Input Leakage Current (Port 0, EA)
Reset Pulldown Resistor
Pin Capacitance
10
300
10
µA
KΩ
pF
RRST
CIO
50
Test Freq. = 1 MHz, TA = 25°C
Active Mode, 12 MHz
Idle Mode, 12 MHz
VCC = 6V
25
mA
mA
µA
µA
Power Supply Current
Power Down Mode(1)
6.5
100
40
ICC
VCC = 3V
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power Down is 2V.
AT87F55
20
AT87F55
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
External Program and Data Memory Characteristics
12 MHz Oscillator
Variable Oscillator
Symbol
1/tCLCL
tLHLL
Parameter
Min
Max
Min
0
Max
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator Frequency
33
ALE Pulse Width
127
43
2tCLCL-40
tCLCL-13
tCLCL-20
tAVLL
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
tLLAX
tLLIV
48
233
4tCLCL-65
tLLPL
43
tCLCL-13
tPLPH
tPLIV
205
3tCLCL-20
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
145
59
3tCLCL-45
tCLCL-10
tPXIX
0
0
tPXIZ
tPXAV
tAVIV
75
tCLCL-8
312
10
5tCLCL-55
10
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
400
400
6tCLCL-100
6tCLCL-100
WR Pulse Width
RD Low to Valid Data In
Data Hold After RD
252
5tCLCL-90
0
0
Data Float After RD
97
2tCLCL-28
8tCLCL-150
9tCLCL-165
3tCLCL+50
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold After WR
517
585
300
200
203
23
3tCLCL-50
4tCLCL-75
tCLCL-20
433
33
7tCLCL-120
tCLCL-20
RD Low to Address Float
RD or WR High to ALE High
0
0
43
123
tCLCL-20
tCLCL+25
21
External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL
tLLIV
tPLIV
tLLPL
PSEN
tPXAV
tPLAZ
tPXIZ
tPXIX
INSTR IN
tLLAX
A0 - A7
tAVIV
A0 - A7
PORT 0
PORT 2
A8 - A15
A8 - A15
External Data Memory Read Cycle
tLHLL
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tLLAX
tRLAZ
tRHDZ
tRHDX
tRLDV
tAVLL
A0 - A7 FROM RI OR DPL
DATA IN
A0 - A7 FROM PCL
INSTR IN
PORT 0
PORT 2
tAVWL
tAVDV
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
AT87F55
22
AT87F55
External Data Memory Write Cycle
tLHLL
ALE
tWHLH
PSEN
tLLWL
tWLWH
WR
tLLAX
tQVWX
tWHQX
tAVLL
tQVWH
A0 - A7 FROM RI OR DPL
DATA OUT
A0 - A7 FROM PCL
INSTR IN
PORT 0
PORT 2
tAVWL
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
External Clock Drive Waveforms
tCHCX
tCHCX
tCLCH
tCHCL
VCC - 0.5V
0.7 VCC
0.2 VCC - 0.1V
0.45V
tCLCX
tCLCL
External Clock Drive
Symbol
1/tCLCL
tCLCL
Parameter
Oscillator Frequency
Clock Period
High Time
Min
0
Max
Units
33
MHz
ns
30
12
12
tCHCX
tCLCX
ns
Low Time
ns
tCLCH
Rise Time
20
20
ns
tCHCL
Fall Time
ns
23
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 5.0V 20% and Load Capacitance = 80 pF.
12 MHz Osc
Variable Oscillator
Symbol
tXLXL
Parameter
Min
1.0
700
50
Max
Min
12tCLCL
10tCLCL-133
2tCLCL-117
0
Max
Units
µs
Serial Port Clock Cycle Time
tQVXH
tXHQX
tXHDX
tXHDV
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
ns
ns
0
ns
700
10tCLCL-133
ns
Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
tXHQX
WRITE TO SBUF
0
1
2
3
4
5
6
7
tXHDX
SET TI
tXHDV
OUTPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
INPUT DATA
AC Testing Input/Output Waveforms(1)
Float Waveforms(1)
+ 0.1V
- 0.1V
VCC - 0.5V
VOL
VLOAD
0.2 VCC + 0.9V
Timing Reference
Points
VLOAD
TEST POINTS
- 0.1V
0.2 VCC - 0.1V
0.45V
VLOAD
+ 0.1V
VOL
Note:
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded VOH/VOL level occurs.
Note:
1. AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing mea-
surements are made at VIH min. for a logic 1 and VIL
max. for a logic 0.
AT87F55
24
AT87F55
Ordering Information
Speed
Power
(MHz)
Supply
Ordering Code
Package
Operation Range
16
24
33
5V 20%
5V 20%
5V 10%
AT87F55-16AC
AT87F55-16JC
AT87F55-16PC
44A
44J
Commercial
(0°C to 70°C)
40P6
AT87F55-16AI
AT87F55-16JI
AT87F55-16PI
44A
44J
Industrial
(-40°C to 85°C)
40P6
AT87F55-24AC
AT87F55-24JC
AT87F55-24PC
44A
44J
Commercial
(0°C to 70°C)
40P6
AT87F55-24AI
AT87F55-24JI
AT87F55-24PI
44A
44J
Industrial
(-40°C to 85°C)
40P6
AT87F55-33AC
AT87F55-33JC
AT87F55-33PC
44A
44J
Commercial
(0°C to 70°C)
40P6
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
44J
40P6
40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
25
Packaging Information
44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad
Flat Package (TQFP)
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
Dimensions in Millimeters and (Inches)*
.045(1.14) X 30° - 45°
12.21(0.478)
11.75(0.458)
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.012(.305)
.008(.203)
SQ
PIN 1 ID
.630(16.0)
.590(15.0)
.656(16.7)
.650(16.5)
0.45(0.018)
0.30(0.012)
SQ
0.80(0.031) BSC
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.695(17.7)
.685(17.4)
SQ
.043(1.09)
.020(.508)
.120(3.05)
.050(1.27) TYP
.500(12.7) REF SQ
.090(2.29)
.180(4.57)
.165(4.19)
10.10(0.394)
9.90(0.386)
SQ
1.20(0.047) MAX
0
7
0.20(.008)
0.09(.003)
.022(.559) X 45° MAX (3X)
0.75(0.030) 0.15(0.006)
0.45(0.018) 0.05(0.002)
*Controlling dimension: millimeters
40P6, 40-pin, 0.600" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AC
2.07(52.6)
2.04(51.8)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
1.900(48.26) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.161(4.09)
.125(3.18)
.022(.559)
.014(.356)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
0
15
REF
.012(.305)
.008(.203)
.690(17.5)
.610(15.5)
AT87F55
26
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Europe
Atmel Rousset
Zone Industrielle
13106 Rousset Cedex
France
Atmel U.K., Ltd.
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
TEL (44) 1276-686-677
FAX (44) 1276-686-697
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 2000.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-
erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
®
™
Marks bearing and/or
are registered trademarks and trademarks of Atmel Corporation.
Printed on recycled paper.
Terms and product names in this document may be trademarks of others.
1147B–02/00/xM
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