AT87C5112_技术文档

Features

• 80C51 Compatible

– Five I/O Ports

– Two 16-bit Timer/Counters

– 256 Bytes RAM

• 8K Bytes ROM/OTP Program Memory with 64 Bytes Encryption Array and 3 Security

Levels

• High-Speed Architecture

– 33 MHz at 5V (66 MHz Equivalent)

– X2 Speed Improvement Capability (6 Clocks/Machine Cycle)

• 10-bit, 8 Channels A/D Converter

• Hardware Watchdog Timer with Reset-out

• Programmable I/O Mode: Standard C51, Input Only, Push-pull, Open Drain

• Asynchronous Port Reset

8-bit

Microcontroller

with A/D

• Full Duplex Enhanced UART with Baud Rate Generator

• SPI, Master Mode

• Dual System Clock

Converter

– Crystal or Ceramic Oscillator (33/40 MHz)

– Internal RC Oscillator (12 MHz)

– Programmable Prescaler

• Programmable Counter Array with High-speed Output, Compare/Capture, Pulse Width

Modulation and Watchdog Timer Capabilities

• Interrupt Structure

– 8 Interrupt Sources

– 4 Interrupt Priority Levels

• Power Control Modes

AT80C5112

AT83C5112

AT87C5112

– Idle Mode

– Power-down Mode

– Power-off Flag

• Power Supply: 2.7 - 5.5V

• Temperature Range: Industrial (-40 To 85°C)

• Package: LQFP48 (Body 7*7*1.4 mm), PLCC52

Description

The AT8xC5112 is a high performance ROM/OTP version of the 80C51 8-bit

microcontroller.

The AT8xC5112 retains all the features of the standard 80C51 with 8 Kbytes

ROM/OTP program memory, 256 bytes of internal RAM, a 8-source, 4-level interrupt

system, an on-chip oscillator and two timer/counters.

The AT8xC5112 is dedicated for analog interfacing applications. For this, it has a 10-

bit, 8 channels A/D converter and a five channels Programmable Counter Array.

In addition, the AT8xC5112 has a Hardware Watchdog Timer, a versatile serial chan-

nel that facilitates multiprocessor communication (EUART) with an independent baud

rate generator, a SPI serial bus controller and a X2 speed improvement mechanism.

The X2 feature allows to keep the same CPU power at a divided by two oscillator

frequency.

The fully static design of the AT8xC5112 allows to reduce system power consumption

by bringing the clock frequency down to any value, even DC, without loss of data.

Rev. 4191B–8051–04/03

The AT8xC5112 has 3 software-selectable modes of reduced activity for further reduc-

tion in power consumption. In the idle mode, the CPU is frozen while the peripherals are

still operating. In the quiet mode, the A/D converter is only operating. In the Power-down

mode, the RAM is saved and all other functions are inoperative. Two oscillators source,

crystal and RC, provide a versatile power management.

The AT8xC5112 is proposed in 48-/52-pin count packages with Port 0 and Port 2

(address/

data buses).

Block Diagram

(3)(3) (3) (3)

(1)

(2) (2)

(2)

XTAL1

(2)

Xtal

Osc

ROM /OTP

8 K *8

RAM

256

x8

Watch

Dog

PCA

SPI

EUART

BRG

XTAL2

C51

CORE

IB-bus

RC

Osc

CPU

RST

EA

Timer 0

Timer 1

INT

Ctrl

Parallel I/O Ports

Port 3 Port 4

A/D

Converter

ALE

PSEN

Port 2

Port 0

Port 1

(3)

(2) (3)

(2)

Notes: 1. Alternate function of Port 1.

2. Alternate function of Port 3.

3. Alternate function of Port 4.

2

AT8xC5112

4191B–8051–04/03

AT8xC5112

SFR Mapping

The Special Function Registers (SFRs) of the AT8xC5112 belongs to the following

categories:

•

C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

I/O port registers: P1, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2

Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1

Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON

Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON,

CKRL

•

Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1

WatchDog Timer: WDTRST, WDTPRG

SPI: SPCON, SPSTA, SPDAT

PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H,

CCAP2H, CCAP3H, CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3,

CCAPM4, CL, CH, CMOD, CCON

•

ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF

3

4191B–8051–04/03

Table 1. SFR Addresses and Reset Values

0/8

1/9

72/A

3/B

4/C

5/D

6/E

7/F

CH

0000 0000

CCAP0H

XXXX XXXX

CCAP1H

XXXX XXXX

CCAP2H

XXXX XXXX

CCAP3H

XXXX XXXX

CCAP4H

XXXX XXXX

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

A0h

98h

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A7h

9Fh

ADCLK

ADCON

B

ADDL

XXXXXX00

ADDH

0000 0000

ADCF

0000 0000

CL

0000 0000

CCAP0L

XXXX XXXX

CCAP1L

XXXX XXXX

CCAP2L

XXXX XXXX

CCAP3L

XXXX XXXX

CCAP4L

XXXX XXXX

CONF

ACC

0000 0000

P1M2

0000 0000

P3M2

0000 0000

P4M2

0000 0000

CCON

00X0 0000

CMOD

X000 0000

CCAPM0

00XX X000

CCAPM1

X000 0000

CCAPM2

X000 0000

CCAPM3

X000 0000

CCAPM4

X000 0000

P1M1

PSW

0000 0000

P3M1

0000 0000

P4M1

0000 0000

SPSTA

SPDAT

P4

1111 1111

SPCON

0001 0100

XXXXXXXX

XXXX XXXX

IPL0

0000 0000

SADEN

0000 0000

IE1

P3

1111 1111

IPL1

0000 0000

IPH1

0000 0000

IPH0

X000 0000

0000 0000

IE0

0000 0000

SADDR

0000 0000

CKCON1

XXXX XXX0

AUXR1

XXXXXXX0

WDRST

0000 0000

WDTPRG

0000 0000

BDRCON

0000 0000

SCON

0000 0000

SBUF

XXXX XXXX

BRL

0000 0000

P1

CKRL

90h

88h

80h

97h

8Fh

87h

1111 1111

TCON

0000 0000

TMOD

0000 0000

TL0

0000 0000

TL1

0000 0000

TH0

0000 0000

TH1

0000 0000

CKCON0

X000X000

PCON

SP

0000 0111

DPL

0000 0000

DPH

0000 0000

CKSEL

XXXX XXX1

OSCCON

XXXX XX01

00X1 0000

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

Reserved

4

AT8xC5112

4191B–8051–04/03

AT8xC5112

Pin Configurations

37

38

48 47 46 45 44 43 42 41 40 39

P3.0/RxD

P3.1/TxD

P0.0

36

35

VREF

VSS + AVSS

P2.7

1

2

34

3

4

P0.1

33

32

31

30

P2.6

P0.2

P2.5

5

LQFP48

7*7*1.4 mm

P0.3

P2.4

6

7

8

P0.4

P2.3

P0.5

29

28

27

26

V2.2

P0.6

VCC + AVCC

P2.1

9

10

11

P0.7

P1.2/ECI

P2.0

P3.7

P1.3/CEX0

25

12

13 14 15 16 17 18 19 20 21 22 23 24

48 47

50 49

6 5 4 3 2

1 52 51

7

NIC

46

45

8

9

VSS

P3.0/RxD

P3.1/TxD

P0.0

AVSS

P2.7

44

10

11

43

42

41

40

P2.6

P0.1

12

13

14

P2.5

P0.2

PLCC52

P2.4

P0.3

P0.4

P2.3

39

38

37

36

15

16

17

P2.2

P0.5

AVCC + VCC

P0.6

P2.1

P0.7

P2.0 18

P1.2/ECI

35

34

19

20

P3.7

VPP

P1.3/CEX0

21 22 23 24 25 26 27 28 29 30 31 32 33

*NIC: No Internal Connection

5

4191B–8051–04/03

Table 2. Pin Description

PIN NUMBER

TYPE

LQFP PLCC

Mnemonic

VSS

48

52

Name and Function

X

I

Ground: 0V reference.

VCC

X

Power Supply: This is the power supply voltage for normal, idle and power-down operation.

Analog Ground: 0V reference.

AVSS

AVCC

VREF

X

Analog Power Supply: This is the power supply voltage for normal and idle operation of the A/D

VREF : A/D converter positive reference input.

Vpp : Programming Supply Voltage:

X

VPP

I

This pin also receives the 12V programming pulse which will start the EPROM programming and the

manufacturer test modes.

I/O

Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are

pulled high by the internal pull-ups and can be used as inputs.

P1.0 - P1.7

X

Alternate functions for Port 1 include:

I/O

WR (P1.0): External data memory write strobe

RD (P1.1): External data memory readstrobe

ECI (P1.2): External Clock for the PCA

CEX0 (P1.3): Capture/Compare External I/O for PCA module 0

CEX1 (P1.4): Capture/Compare External I/O for PCA module 1

CEX2 (P1.5): Capture/Compare External I/O for PCA module 2

CEX3 (P1.6): Capture/Compare External I/O for PCA module 3

CEX4 (P1.7): Capture/Compare External I/O for PCA module 4

P3.0 - P3.7

Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are

pulled high by the internal pull-ups and can be used as inputs.

X

P3.6 is an input only pin.

Port 3 also serves the special features of the 80C51 family, as listed below.

I/O

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

INT0 (P3.2): External interrupt 0

T0 (P3.3): Timer 0 external input

Port 4: Port 4 is an 8-bit bi-directional I/O port. Each bit can be set as pure CMOS input or as push-pull output.

I/O

Port 4 is also the input port of the analog-to-digital converter and used for oscillator and reset.

AIN0 (P4.0): A/D converter input 0

AIN1 (P4.1): A/D converter input 1

T1: Timer 1 external input

P4.0-P4.7

X

AIN2 (P4.2): A/D converter input 2

I/O

SS: Slave select input of the SPI controller

AIN3 (P4.3): A/D converter input 3

INT1: External interrupt 1

6

AT8xC5112

4191B–8051–04/03

AT8xC5112

Table 2. Pin Description (Continued)

PIN NUMBER

TYPE

LQFP PLCC

Mnemonic

48

52

Name and Function

AIN4 (P4.4): A/D converter input 4

I/O

MISO: Master IN, Slave OUT of the SPI controller

AIN5 (P4.5): A/D converter input 5

MOSI: Master OUT, Slave IN of the SPI controller

AIN6 (P4.6): A/D converter input 6

SPSCK: Clock I/O of the SPI controller

I/O

AIN7 (P4.7): A/D converter input 7

P0.0-P0.7

P2.0-P2.7

X

Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s written to them float and can be

used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during access to

external program and data memory. In this application, it uses strong internal pull-up when emitting 1s.

I/O

Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1s written to them

are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally

pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during

fetches from external program memory and during accesses to external data memory that use 16-bit

addresses (MOVX atDPTR). In this application, it uses strong internal pull-ups emitting 1s. During accesses to

external data memory that use 8-bit addresses (MOVX atRi), port 2 emits the contents of the P2 SFR.

RST

ALE

X

I

RST: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal

diffused resistor to V_SSpermits a power-on reset using only an external capacitor to V_CC.If the hardware

watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated.

O

Address Latch Enable: Output pulse for latching the low byte of the address during an access to external

memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,

and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to

external data memory. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive

during internal fetches.

PSEN

EA

X

O

I

Program Store Enable: The read strobe to external program memory. When executing code from the external

program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped

during each access to external data memory. PSEN is not activated during fetches from internal program

memory.

External Access Enable: EA must be externally held low to enable the device to fetch code from external

program memory locations 0000H and 1FFFH . If EA is held high, the device executes from internal program

memory unless the program counter contains an address greater than 1FFFH. EA must be held low for

ROMless devices. If security level 1 is programmed, EA will be internally latched on Reset.

XTAL1

XTAL2

X

I

XTAL1 : Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

XTAL2 : Output from the inverting oscillator amplifier.

O

7

4191B–8051–04/03

Clock System

The AT8xC5112 oscillator system provides a reliable clocking system with full mastering

of speed versus CPU power trade off. Several clock sources are possible:

•

External clock input

High speed crystal or ceramic oscillator

Integrated high speed RC oscillator

The selected clock source can be divided by 2-512 before clocking the CPU and the

peripherals. When X2 function is set, the CPU needs 6 clock periods per cycle.

Clocking is controlled by several SFR registers: OSCON, CKCON0, CKCON1, CKRL.

Blocks Description

The AT8xC5112 includes the following oscillators:

•

Crystal oscillator

Integrated high speed RC oscillator, with typical frequency of 12 MHz

Crystal Oscillator: OSCA

The crystal oscillator uses two external pins, XTAL1 for input and XTAL2 for output.

Both crystal and ceramic resonators can be used. In oscillator source an XTAL1 is man-

datory to start the product.

OSCAEN in OSCCON register is an enable signal for the crystal oscillator or the exter-

nal oscillator input.

Integrated High Speed RC

Oscillator: OSCB

The high speed RC oscillator typical frequency is 12 MHz. Note that the on chip oscilla-

tor has a ±50% frequency tolerance and may not be suitable for use in some

applications.

OSCBEN in OSCCON register is an enable signal for the high speed RC oscillator.

Clock Selector

Clock Prescaler

CKS bit in CKS register is used to select from crystal to RC oscillator.

OSCBEN bit in OSCCON register is used to enable the RC oscillator.

OSCAEN bit in OSCCON register is used to enable the crystal oscillator or the external

oscillator input.

Before supplying the CPU and the peripherals, the main clock is divided by a factor of 2

to 512, as defined by the CKRL register. The CPU needs from 12 to 256*12 clock peri-

ods per instruction. This allows:

•

to accept any cyclic ratio to be accepted on XTAL1 input.

to reduce the CPU power consumption.

The X2 bit allows to bypass the clock prescaler; in this case, the CPU needs only 6 clock

periods per machine cycle. In X2 mode, as this divider is bypassed, the signals on

XTAL1 must have a cyclic ratio between 40 to 60%.

8

AT8xC5112

4191B–8051–04/03

AT8xC5112

Functional Block Diagram

Timer 0 clock

Sub Clock

: 128

Reload

ResetB

WD clock

Ckrl

Xtal1

A/D clock

CkAdc

Xtal_Osc

OSCA

1

0

OscOut

Xtal2

Mux

+

8-bit

Prescaler-Divider

0

1

Filter

OSCAEN

OSCBEN

Peripherals clock

CkIdle

PwdOsc

CkOut

CKS

RC_Osc

OSCB

CPU clock

Ck

X2

PwdRC

Idle

Quiet Pwd

Operating Modes

Functional Modes

Normal Modes

•

CPU and Peripheral clocks depend on the software selection using CKCON0,

CKCON1, CKSEL and CKRL registers.

•

CKS bit selects either Xtal_Osc or RC_Osc.

CKRL register determines the frequency of the selected clock, unless X2 bit is set.

In this case the prescaler/divider is not used, so CPU core needs only 6-clock

periods per machine cycle. According to the value of the peripheral X2 individual bit,

each peripheral needs 6 or 12 clock period per instructions.

•

It is always possible to switch dynamically by software from Xtal_Osc to RC_Osc,

and vice versa by changing CKS bit, a synchronization cell allowing to avoid any

spike during transition.

Idle Modes

•

IDLE modes are achieved by using any instruction that writes into PCON.0 sfr

IDLE modes A and B depend on previous software sequence, prior to writing into

PCON.0 register:

•

IDLE MODE A: Xtal_Osc is running (OSCAEN = 1) and selected (CKS = 1)

IDLE MODE B: RC_Osc is running (OSCBEN = 1) and selected (CKS = 0)

The unused oscillator Xtal_Osc or RC_Osc can be stopped by software by clearing

OSCAEN or OSCBEN respectively.

•

Exit from IDLE mode is achieved by Reset, or by activation of an enabled interrupt.

In both cases, PCON.0 is cleared by hardware.

9

4191B–8051–04/03

•

Exit from IDLE modes will leave the oscillator control bits OSCAEN, OSCBEN and

CKS unchanged.

Power Down Modes

•

POWER DOWN modes are achieved by using any instruction that writes into

PCON.1 sfr

Exit from POWER DOWN mode is achieved either by a hardware Reset, or by an

external interruption.

•

By RST signal: The CPU will restart on OSCA.

By INT0 or INT1 interruptions, if enabled. The oscillators control bits OSCAEN,

OSCBEN and CKS will not be changed, so the selected oscillator before entering

into Power-down will be activated.

Table 3. Power Modes

PD IDLE CKS

OSCBEN OSCAEN Selected Mode

Comment

0

X

0

X

0

1

0

X

1

0

1

0

NORMAL MODE A OSCA: XTAL clock

INVALID

no active clock

X

NORMAL MODE B OSCB: high speed RC clock

INVALID

X

The CPU is off, OSCA supplies the

0

1

0

X

1

X

IDLE MODE A

peripherics

The CPU is off, OSCB supplies the

IDLE MODE B

peripherics

TOTAL POWER

DOWN

The CPU is off, OSCA and OSCB are

stopped OSCC is stopped

X

Prescaler Divider

•

An hardware RESET selects the prescaler divider:

CKRL = FFh: internal clock = OscOut/2 (Standard C51 feature)

X2 = 0,

After Reset, any value between FFh down to 00h can be written by software into

CKRL sfr in order to divide frequency of the selected oscillator:

•

CKRL = 00h: minimum frequency = OscOut/512

CKRL = FFh: maximum frequency = OscOut/2

The frequency of the CPU and peripherals clock CkOut is related to the frequency of the

main oscillator OscOut by the following formula:

F

_CkOut= F_OscOut/(512 - 2*CKRL)

Some examples can be found in the table below:

F_OscOut

MHz

X2

0

CKRL

FF

F_CkOut(Mhz)

12

6

3

12

0

FE

12

1

x

12

10

AT8xC5112

4191B–8051–04/03

AT8xC5112

•

A software instruction which sets X2 bit de-activates the prescaler/divider, so the

internal clock is either Xtal_Osc or RC_Osc depending on SEL_OSC bit.

Timer 0: Clock Inputs

CkIdle

T0 pin

Sub Clock

: 6

0

1

Timer 0

0

Control

1

C/T

TMOD

SCLKT0

OSCCON

Gate

INT0

TR0

The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. This

allow to perform a Real Time Clock function.

SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode)

SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input.

When the subclock input is selected for Timer 0 and the crystal oscillator is selected for

CPU and peripherals, the CKRL prescaler must be set to FF (division factor 2) in order

to assure a proper count on Timer 0

With an external a 32 kHz oscillator, the timer interrupt can be set from 1/256 to 256

seconds to perform a Real Time Clock (RTC) function. The power consumption will be

very low as the CPU is in idle mode at 32 KHz most of the time. When more CPU power

is needed, the internal RC oscillator is activated and used by the CPU and the others

peripherals.

Registers

Clock Control Register

The clock control register is used to define the clock system behavior.

Table 4. OSCCON - Clock Control Register (8Fh)

7

-

6

-

5

-

4

-

3

-

2

1

0

SCLKT0

OSCBEN

OSCAEN

Bit

Number

Mnemonic

Description

Reserved

7

6

5

4

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

11

4191B–8051–04/03

Bit

Number

Mnemonic

Description

Reserved

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

Sub Clock Timer0

SCLKT0

Cleared by software to select T0 pin

Set by software to select T0 Sub Clock

Enable RC oscillator

This bit is used to enable the high speed RC oscillator

1

0

OSCBEN

OSCAEN

0: The oscillator is disabled

1: The oscillator is enabled.

Enable crystal oscillator

This bit is used to enable the crystal oscillator

0: The oscillator is disabled

1: The oscillator is enabled.

Reset value = 0XXX X001b

Not bit addressable

Clock Selection Register

The clock selection register is used to define the clock system behavior

Table 5. CKSEL - Clock Selection Register (85h)

7

6

-

5

-

4

-

3

-

2

-

1

-

0

CKS

Bit

Number

Mnemonic

Description

Reserved

7

6

5

4

3

2

1

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Active oscillator selection

This bit is used to select the active oscillator

0

CKS

1: The crystal oscillator is selected

0: The high speed RC oscillator is selected.

Reset value = XXXX XXX 1 b

Not bit addressable

12

AT8xC5112

4191B–8051–04/03

AT8xC5112

Clock Prescaler Register

This register is used to reload the clock prescaler of the CPU and peripheral clock.

Table 6. CKRL - Clock prescaler Register (97h)

7

6

5

4

3

2

1

0

M

Bit

Mnemonic Description

Number

0000 0000b: Division factor equal 512

1111 1111b: Division factor equal 2

M: Division factor equal 2*(256-M)

7: 0

CKRL

Reset value = 1111 1111b

Not bit addressable

Clock Control Register

This register is used to control the X2 mode of the CPU and peripheral clock.

Table 7. CKCON0 Register (8Fh)

7

-

6

5

4

3

-

2

1

0

WDX2

PCAX2

SIX2

T1X2

T0X2

X2

Bit

Number Mnemonic Description

7

6

-

Reserved

Watchdog clock (This control bit is validated when the CPU clock X2 is set; when

X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

WdX2

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array clock (This control bit is validated when the CPU

clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

5

PcaX2

Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the

CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

4

3

2

SiX2

-

Set to select 12 clock periods per peripheral clock cycle.

Reserved

Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2

is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

T1X2

Set to select 12 clock periods per peripheral clock cycle

Timer0 clock (This control bit is validated when the CPU clock X2 is set; when X2

is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

1

T0X2

Set to select 12 clock periods per peripheral clock cycle

13

4191B–8051–04/03

Bit

Number Mnemonic Description

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the

peripherals.

0

X2

Set to select 6clock periods per machine cycle (X2 mode) and to enable the

individual peripherals "X2" bits.

Reset value = X000 0000b

Not bit addressable

Table 8. CKCON1 Register (AFh)

7

-

6

-

5

-

4

-

3

-

2

-

1

0

BRGX2

SPIX2

Bit

Number

Mnemonic

Description

7

6

5

4

3

2

-

Reserved

BRG clock (This control bit is validated when the CPU clock X2 is set; when

X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

1

0

BRGX2

SPIX2

Set to select 12 clock periods per peripheral clock cycle

SPI clock (This control bit is validated when the CPU clock X2 is set; when X2

is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

Reset value = XXXX XX00b

Not bit addressable

14

AT8xC5112

4191B–8051–04/03

AT8xC5112

Reset and Power

Management

The power monitoring and management can be used to supervise the Power Supply

(VDD) and to start up properly when AT8xC5112 is powered up.

It consists of the features listed below and explained hereafter:

•

Power-off flag

Idle mode

Power-down mode

Reduced EMI mode

All these features are controlled by several registers, the Power Control register (PCON)

and the Auxiliary register (AUXR) detailed at the end of this section.

AUX register not available on all versions.

Functional Description

Figure 1 shows the block diagram of the possible sources of microcontroller reset.

Figure 1. Reset Sources

RST pin⁽¹⁾

Hardware WD

Reset

RST pin⁽²⁾

PCA WD

Notes: 1. RST pin available only on 48 and 52 pins versions.

2. RST pin available only on LPC versions.

Power-off Flag

When the power is turned off or fails, the data retention is not guaranteed. A Power-off

Flag (POF, Table 9 on page 16) allows to detect this condition. POF is set by hardware

during a reset which follows a power-up or a power-fail. This is a cold reset. A warm

reset is an external or a watchdog reset without power failure, hence which preserves

the internal memory content and POF. To use POF, test and clear this bit just after

reset. Then it will be set only after a cold reset.

15

4191B–8051–04/03

Registers

PCON: Power Configuration

Register

Table 9. PCON Register (87h)

7

6

5

4

3

2

1

0

SMOD1

SMOD0

–

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Double Baud Rate bit

7

6

SMOD1

SMOD0

Set to double the Baud Rate when Timer 1 is used and mode 1, 2 or 3 is

selected in SCON register.

SCON Select bit

When cleared, read/write accesses to SCON.7 are to SM0 bit and read/write

accesses to SCON.6 are to SM1 bit.

When set, read/write accesses to SCON.7 are to FE bit and read/write

accesses to SCON.6 are to OVR bit. SCON is Serial Port Control register.

Reserved

Must be cleared.

5

4

–

Power-off flag

Set by hardware when VDD rises above V_RET+to indicate that the Power

Supply has been set off.

POF

Must be cleared by software.

General Purpose flag 1

3

2

GF1

GF0

One use is to indicate wether an interrupt occurred during normal operation or

during Idle mode.

General Purpose flag 0

One use is to indicate wether an interrupt occurred during normal operation or

during Idle mode.

Power-down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-down mode.

If IDL and PD are both set, PD takes precedence.

1

0

PD

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

IDL

If IDL and PD are both set, PD takes precedence.

Reset value = 0000 0000b

Port Pins

The value of port pins in the different operating modes is shown on the figure below.

Table 10. Pin Conditions in Special Operating Modes

Mode

Program Memory Port 1 pins

Port 3 pins

Weak High

Data

Port 4 pins

Weak High

Data

Reset

Don’t care

Internal

Weak High

Data

Idle

Power-down

Internal

Data

16

AT8xC5112

4191B–8051–04/03

AT8xC5112

Reduced EMI Mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with

external program or data memory. Nevertheless, during internal code execution, ALE

signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting

AO bit.

The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no

longer output but remains active during MOVX and MOVC instructions and external

fetches. During ALE disabling, ALE pin is weakly pulled high.

Table 11. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

AO

Bit

Number

Mnemonic

Description

Reserved

7

6

5

4

3

2

1

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

ALE Output bit

0

AO

Clear to restore ALE operation during internal fetches.

Set to disable ALE operation during internal fetches.

Reset value = XXXX XXX0b

Not bit addressable

17

4191B–8051–04/03

Hardware Watchdog

Timer

The WDT is intended as a recovery method in situations where the CPU may be sub-

jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer

Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable

the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca-

tion 0A6H. When WDT is enabled, it will increment every machine cycle (6 internal clock

periods) and there is no way to disable the WDT except through reset (either hardware

reset or WDT overflow reset). The T0 bit of the WDTPRG register is used to select the

overflow after 10 or 14 bits. When WDT overflows, it will generate an internal reset. It

will also drive an output RESET HIGH pulse at the emulator RST-pin. The length of the

reset pulse is 24 clock periods of the WD clock.

Using the WDT

To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST,

SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to

01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when

it reaches 16383 (3FFFH) or 1024 (1FFFH) and this will reset the device. When WDT is

enabled, it will increment every machine cycle while the oscillator is running. This means

the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the

user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The

WDT counter cannot be read or written. When WDT overflows, it will generate an output

RESET pulse at the RST-pin. The RESET pulse duration is 96 x T_OSC, where T_OSC

=

1/F_OSC. To make the best use of the WDT, it should be serviced in those sections of

code that will periodically be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 2⁷counter has been added to extend the Time-out

capability, ranking from 16ms to 2s at F_OSC= 12 MHz and T0=0. To manage this fea-

ture, refer to WDTPRG register description, Table 13. (SFR0A7h).

Table 12. WDTRST Register

WDTRST Address (0A6h)

7

6

5

4

3

2

1

Reset value

X

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in

sequence.

18

AT8xC5112

4191B–8051–04/03

AT8xC5112

Table 13. WDTPRG Register

WDTPRG Address (0A7h)

7

6

5

4

3

2

1

0

T4

T3

T2

T1

T0

S2

S1

S0

Bit

Number

Mnemonic

Description

7

6

5

4

T4

T3

T2

T1

Reserved

Do not try to set this bit.

WDT overflow select bit

0: Overflow after 14 bits

1: Overflow after 10 bits

3

T0

2

1

0

S2

S1

S0

WDT Time-out select bit 2

WDT Time-out select bit 1

WDT Time-out select bit 0

S2 S1 S0

Selected Time-out with T0=0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(2¹⁴- 1) machine cycles, 16.3 ms at 12 MHz

(2¹⁵- 1) machine cycles, 32.7 ms at 12 MHz

(2¹⁶- 1) machine cycles, 65.5 ms at 12 MHz

(2¹⁷- 1) machine cycles, 131 ms at 12 MHz

(2¹⁸- 1) machine cycles, 262 ms at 12 MHz

(2¹⁹- 1) machine cycles, 542 ms at 12 MHz

(2²⁰- 1) machine cycles, 1.05 s at 12 MHz

(2²¹- 1) machine cycles, 2.09 s at 12 MHz

Reset value = XXX0 0000

Write only register

WDT During Power Down and

Idle

Power Down

In Power Down mode the oscillator stops, which means the WDT also stops. While in

Power Down mode the user does not need to service the WDT. There are 2 methods of

exiting Power Down mode: by a hardware reset or via a level activated external interrupt

which is enabled prior to entering Power Down mode. When Power Down is exited with

hardware reset, servicing the WDT should occur as normal whenever the AT8xC5112 is

reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held

low long enough for the oscillator to stabilize. When the interrupt is brought high, the

interrupt is serviced. To prevent the WDT from resetting the device while the interrupt

pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested

that the WDT be reset during the interrupt service routine.

To ensure that the WDT does not overflow within a few states of exiting of powerdown, it

is best to reset the WDT just before entering powerdown.

Idle Mode

In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the

AT8xC5112 while in Idle mode, the user should always set up a timer that will periodi-

cally exit Idle, service the WDT, and re-enter Idle mode.

19

4191B–8051–04/03

Ports

All port 1, port 3 and port 4 I/O port pins on the AT8xC5112 may be software configured

to one of four types on a bit-by-bit basis, as shown in Table 14. These are: Quasi bi-

directional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two

configuration registers for each port choose the output type for each port pin.

Table 14. Port Output Configuration settings using PxM1 and PxM2 registers

PxM1.y Bit

PxM2.y Bit

Port Output Mode

Quasi bi-directional

Push-pull

0

1

0

1

0

1

Input-only (High Impedance)

Open Drain

Port Types

Quasi bi-directional Output

Configuration

The default port output configuration for standard AT8xC5112 I/O ports is the Quasi bi-

directional output that is common on the 80C51 and most of its derivatives. This output

type can be used as both an input and output without the need to reconfigure the port.

This is possible because when the port outputs a logic high, it is weakly driven, allowing

an external device to pull the pin low. When the pin is pulled low, it is driven strongly and

able to sink a fairly large current. These features are somewhat similar to an open drain

output except that there are three pull-up transistors in the Quasi bi-directional output

that serve different purposes. One of these pull-ups, called the "very weak" pull-up, is

turned on whenever the port latch for the pin contains a logic 1. The very weak pull-up

sources a very small current that will pull the pin high if it is left floating. A second pull-

up, called the "weak" pull-up, is turned on when the port latch for the pin contains a logic

1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source cur-

rent for a Quasi bi-directional pin that is outputting a 1. If a pin that has a logic 1 on it is

pulled low by an external device, the weak pull-up turns off, and only the very weak pull-

up remains on. In order to pull the pin low under these conditions, the external device

has to sink enough current to overpower the weak pull-up and take the voltage on the

port pin below its input threshold.

The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up

low-to-high transitions on a Quasi bi-directional port pin when the port latch changes

from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time,

two CPU clocks, in order to pull the port pin high quickly. Then it turns off again.

The Quasi bi-directional port configuration is shown in Figure 2.

20

AT8xC5112

4191B–8051–04/03

AT8xC5112

Figure 2. Quasi bi-directional Output

2 CPU

CLOCK DELAY

P

Very

Weak

Strong

Weak

Port latch

Data

N

Input

Data

Open Drain Output

Configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port configured in this manner must have an external pull-up, typically a resis-

tor tied to V_DD. The pull-down for this mode is the same as for the Quasi bi-directional

mode. The open-drain port configuration is shown in Figure 3.

Figure 3. Open-drain Output

Port latch

Data

N

Input

Data

Push-pull Output

Configuration

The push-pull output configuration has the same pull-down structure as both the open

drain and the Quasi bi-directional output modes, but provides a continuous strong pull-

up when the port latch contains a logic 1. The push-pull mode may be used when more

source current is needed from a port output. The push-pull port configuration is shown in

Figure 4.

21

4191B–8051–04/03

Figure 4. Push-pull Output

P

Strong

Port Latch

Data

N

Input

Data

Input-only Configuration

The input-only configuration is a pure input with neither pull-up nor pull-down.

The input-only configuration is shown in Figure 4.

Figure 5. Input-only

Input

Data

Ports Description

Ports P1, P3 and P4

Every output on the AT8xC5112 may potentially be used as a 20 mA sink LED drive out-

put. However, there is a maximum total output current for all ports which must not be

exceeded. All ports pins of the AT8xC5112 have slew rate controlled outputs. This is to

limit noise generated by quickly switching output signals. The slew rate is factory set to

approximately 10 ns rise and fall times.

The inputs of each I/O port of the AT8xC5112 are TTL level Schmitt triggers with

hysteresis.

Ports P0 and P2

High pin-count version of the AT8xC5112 has standard address and data ports P0 and

P2. These ports are standard C51 ports (Quasi bi-directional I/O). The control lines are

provided on the pins: ALE, PSEN, EA, Reset; RD and WR signals are on the bits P1.1

and P1.0.

22

AT8xC5112

4191B–8051–04/03

AT8xC5112

Registers

Table 15. P1M1 Register

P1M1 Address (D4h)

7

6

5

4

3

2

1

0

P1M1.7

P1M1.6

P1M1.5

P1M1.4

P1M1.3

P1M1.2

P1M1.1

P1M1.0

Bit

Number

Mnemonic

Description

Port Output configuration bit

See Table 10 for configuration definition

7: 0

P1M1.x

Reset value = 0000 00XX

Table 16. P1M2 Register

P1M2 Address (E2h)

7

6

5

4

3

2

1

0

P1M2.7

P1M2.6

P1M2.5

P1M2.4

P1M2.3

P1M2.2

P1M2.1

P1M2.0

Bit

Number

Mnemonic

Description

Port Output configuration bit

See Table 10 for configuration definition

7: 0

P1M2.x

Reset value = 0000 00XX

Table 17. P3M1 Register

P3M1 Address (D5h)

7

6

5

4

3

2

1

0

P3M1.7

P3M1.6

P3M1.5

P3M1.4

P3M1.3

P3M1.2

P3M1.1

P3M1.0

Bit

Number

Mnemonic

Description

Port Output configuration bit

See Table 10 for configuration definition

7: 0

P3M1.x

Reset value = 0000 0000

23

4191B–8051–04/03

Table 18. P3M2 Register

P3M2 Address (E4h)

7

6

5

4

3

2

1

0

P3M2.7

P3M2.6

P3M2.5

P3M2.4

P3M2.3

P3M2.2

P3M2.1

P3M2.0

Bit

Number

Mnemonic

Description

Port Output configuration bit

See Table 10 for configuration definition

7: 0

P3M2.x

Reset value = 0000 0000

Table 19. P4M1 Register

P4M1 Address (D6h)

7

6

5

4

3

2

1

0

P4M1.7

P4M1.6

P4M1.5

P4M1.4

P4M1.3

P4M1.2

P4M1.1

P4M1.0

Bit

Number

Mnemonic

Description

Port Output configuration bit

See Table 10 for configuration definition

7: 0

P4M1.x

Reset value = 0000 0000

Table 20. P4M2 Register

P4M2 Address (E5h)

7

6

5

4

3

2

1

0

P4M2.7

P4M2.6

P4M2.5

P4M2.4

P4M2.3

P4M2.2

P4M2.1

P4M2.0

Bit

Number

Mnemonic

Description

Port Output configuration bit

See Table 10 for configuration definition

7: 0

P4M2.x

Reset value = 0000 0000

24

AT8xC5112

4191B–8051–04/03

AT8xC5112

Dual Data Pointer

Register

The additional data pointer can be used to speed up code execution and reduce code

size in a number of ways.

The dual DPTR structure is a way by which the chip will specify the address of an exter-

nal data memory location. There are two 16-bit DPTR registers that address the external

memory, and a single bit called DPS = AUXR1/bit0 (see Table 21) that allows the pro-

gram code to switch between them (Refer to Figure 6).

Figure 6. Use of Dual Pointer

External Data Memory

7

0

DPS

DPTR1

DPTR0

AUXR1(A2H)

DPH(83H) DPL(82H)

Table 21. AUXR1: Auxiliary Register 1

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

DPS

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Clear to select DPTR0.

Set to select DPTR1.

0

DPS

Note:

User software should not write 1s to reserved bits. These bits may be used in future 8051

family products to invoke new feature. In that case, the reset value of the new bit will be

0, and its active value will be 1. The value read from a reserved bit is indeterminate.

25

4191B–8051–04/03

Application

Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare, search...) are well

served by using one data pointer as a ’source’ pointer and the other one as a "destina-

tion" pointer.

ASSEMBLY LANGUAGE

; Block move using dual data pointers

; Destroys DPTR0, DPTR1, A and PSW

; note: DPS exits opposite of entry state

; unless an extra INC AUXR1 is added

;

00A2

;

AUXR1 EQU 0A2H

0000 909000MOV DPTR,#SOURCE ; address of SOURCE

0003 05A2 INC AUXR1 ; switch data pointers

0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1

000A E0 MOVX A,atDPTR ; get a byte from SOURCE

; switch data pointers

000B A3 INC DPTR

000C 05A2 INC AUXR1

; increment SOURCE address

; switch data pointers

000E F0 MOVX atDPTR,A ; write the byte to DEST

000F A3 INC DPTR

0010 70F6JNZ LOOP

0012 05A2 INC AUXR1

; increment DEST address

; check for 0 terminator

; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1

SFR. However, note that the INC instruction does not directly force the DPS bit to a par-

ticular state, but simply toggles it. In simple routines, such as the block move example,

only the fact that DPS is toggled in the proper sequence matters, not its actual value. In

other words, the block move routine works the same whether DPS is '0' or '1' on entry.

Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in

the opposite state.

26

AT8xC5112

4191B–8051–04/03

AT8xC5112

Serial I/O Ports

Enhancements

The serial I/O ports in the AT8xC5112 are compatible with the serial I/O port in the

80C52.

They provide both synchronous and asynchronous communication modes. They oper-

ate as Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex

modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-

taneously and at different baud rates

Serial I/O ports include the following enhancements:

•

Framing error detection

Automatic address recognition

Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2

and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-

ter (See Figure 7).

Figure 7. Framing Error Block Diagram

SCON for UART (98h) (SCON_1 for UART_1 (C0h))

SM2

REN

TI

RI

SM0/FE

SM1

TB8

RB8

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1 for UART)

SM0 to UART mode control (SMOD0 = 0 for UART)

GF1

POF

GF0

SMOD1 SMOD0

-

PD

IDL PCON for UART (87h) (SMOD bits for UART_1

are located in BDRCON_1)

To UART framing error control

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register (See Table 27) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a reset can clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the

last data bit (See Figure 8. and Figure 9.).

Figure 8. UART Timings in Mode 1

D0

D1

D2

D3

D4

D5

D6

D7

RXD

Start

bit

Data byte

Stop

bit

RI

SMOD0=X

FE

SMOD0=1

27

4191B–8051–04/03

Figure 9. UART Timings in Modes 2 and 3

D0

D1

D2

D3

D4

D5

D6

D7

D8

RXD

Start

bit

Data byte

Ninth Stop

bit bit

RI

SMOD0=0

RI

SMOD0=1

FE

SMOD0=1

Automatic Address

Recognition

The automatic address recognition feature is enabled for each UART when the multipro-

cessor communication feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor

communication feature by allowing the serial port to examine the address of each

incoming command frame. Only when the serial port recognizes its own address, the

receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU

is not interrupted by command frames addressed to other devices.

If desired, you may enable the automatic address recognition feature in mode 1. In this

configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the

received command frame address matches the device’s address and is terminated by a

valid stop bit.

To support automatic address recognition, a device is identified by a given address and

a broadcast address.

Note:

The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).

Given Address

Each UART has an individual address that is specified in SADDR register; the SADEN

register is a mask byte that contains don’t-care bits (defined by zeros) to form the

device’s given address. The don’t-care bits provide the flexibility to address one or more

slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Slave C:SADDR1111 0010b

SADEN1111 1101b

Given1111 00X1b

28

AT8xC5112

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The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com-

municate with slave A only, the master must send an address where bit 0 is clear (e.g.

1111 0000b).

For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both

set (e.g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0

set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e.g.:

SADDR 0101 0110b

SADEN 1111 1100b

Broadcast =SADDR OR SADEN1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however

in most applications, a broadcast address is FFh. The following is an example of using

broadcast addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Broadcast1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Broadcast1111 1X11B,

Slave C:SADDR=1111 0010b

SADEN1111 1101b

Broadcast1111 1111b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the slaves, the master must send an address FFh. To communicate with slaves A

and B, but not slave C, the master can send and address FBh.

Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and

broadcast addresses are XXXX XXXXb(all don’t-care bits). This ensures that the serial

port will reply to any address, and so, that it is backwards compatible with the 80C51

microcontrollers that do not support automatic address recognition.

Baud Rate Selection for

UART for mode 1 and 3

The Baud Rate Generator for transmit and receive clocks can be selected separately via

the T2CON and BDRCON registers.

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4191B–8051–04/03

Figure 10. Baud Rate Selection

TIMER1_BRG

0

1

/ 16

Rx Clock

INT_BRG

RBCK

TIMER1_BRG

0

/ 16

1

Tx Clock

INT_BRG

TBCK

Table 22. Baud Rate Selection Table for UART

Clock Source

UART Rx

TBCK

RBCK

Clock Source for UART Tx

Timer 1

0

1

0

1

0

1

Timer 1

INT_BRG

Timer 1

INT_BRG

Internal Baud Rate Generator When the internal Baud Rate Generator is used, the Baud Rates are determined by the

(BRG)

BRG overflow depending on the BRL reload value, the X2 bit in CKON0 register, the

value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in

PCON register (for UART) :

Figure 11. Internal Baud Rate Generator

SMOD1

/2

0

INT_BRG

1

auto reload counter

Peripheral clock

0

1

/6

BRG

overflow

BRL

SPD

BRR

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for UART:

2

^SMOD1x 2^X2x F_XTAL

Baud_Rate =

2 x 2 x 6^(1-SPD)x 16 x [256 - (BRL)]

2^SMOD1x 2^X2x F_XTAL

(BRL) = 256 -

2 x 2 x 6^(1-SPD)x 16 x Baud_Rate

Example of computed value when X2=1, SMOD1=1, SPD=1

Baud Rates

F_XTAL= 16.384 MHz

F_XTAL= 24 MHz

BRL

Error (%)

1.23

BRL

243

230

217

204

178

100

-

Error (%)

0.16

-

115200

57600

38400

28800

19200

9600

247

238

229

220

203

149

43

1.23

0.63

0.31

4800

1.23

Example of computed value when X2=0, SMOD1=0, SPD=0

Baud Rates

F

BRL

247

238

220

185

_OSC= 16.384 MHz

F_OSC= 24 MHz

Error (%)

0.16

Error (%)

BRL

243

230

202

152

4800

2400

1200

600

1.23

0.16

3.55

0.16

The baud rate generator can be used for mode 1 or 3 (refer to Figure 10. ), but also for

mode 0 for both UARTs, thanks to the bit SRC located in BDRCON register (see Table

29).

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4191B–8051–04/03

UART Registers

Table 23. SADEN - Slave Address Mask Register for UART (B9h)

7

6

5

4

3

2

1

0

Reset value = 0000 0000b

Table 24. SADDR - Slave Address Register for UART (A9h)

7

6

5

4

3

2

Reset value = 0000 0000b

Table 25. SBUF - Serial Buffer Register for UART (99h)

7

6

5

4

3

2

Reset value = XXXX XXXXb

Table 26. BRL - Baud Rate Reload Register for the internal baud rate generator, UART

UART(9Ah)

7

6

5

4

3

2

1

0

Reset value = 0000 0000b

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Table 27. SCON Register

SCON - Serial Control Register for UART (98h)

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Number Mnemonic Description

Framing Error bit (SMOD0=1) for UART

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

7

FE

SMOD0 must be set to enable access to the FE bit

Serial port Mode bit 0 (SMOD0=0) for UART

Refer to SM1 for serial port mode selection.

SM0

SMOD0 must be cleared to enable access to the SM0 bit

Serial port Mode bit 1 for UART

SM0 SM1 Mode Description Baud Rate

0

1

0

1

0

1

0

1

2

3

Shift Register F_XTAL/12 (F_XTAL/6 X2 mode)

6

5

SM1

SM2

8-bit UART

9-bit UART

Variable

_XTAL/64 or F_XTAL/32 (F_XTAL/32 or F_XTAL/16 X2 mode)

Variable

F

Serial port Mode 2 bit/Multiprocessor Communication Enable bit for UART

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3, and

eventually mode 1. This bit should be cleared in mode 0.

Reception Enable bit for UART

Clear to disable serial reception.

Set to enable serial reception.

4

3

REN

TB8

Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3 for UART.

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8/Ninth bit received in modes 2 and 3 for UART

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

2

1

0

RB8

TI

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

Transmit Interrupt flag for UART

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the

stop bit in the other modes.

Receive Interrupt flag for UART

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 8. and Figure 9.

in the other modes.

RI

Reset value = 0000 0000b

Bit addressable

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4191B–8051–04/03

Table 28. PCON Register

PCON - Power Control Register (87h)

7

6

5

4

3

2

1

0

SMOD1

SMOD0

RSTD

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Serial port Mode bit 1 for UART

Set to select double baud rate in mode 1, 2 or 3.

7

6

SMOD1

Serial port Mode bit 0 for UART

SMOD0 Clear to select SM0 bit in SCON register.

Set to to select FE bit in SCON register.

Reset Detector Disable Bit

5

4

RSTD

POF

Clear to disable PFD.

Set to enable PFD.

Power-off Flag

Clear to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set

by software.

General purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by user for general purpose usage.

Set by user for general purpose usage.

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-down mode bit

Cleared by hardware when reset occurs.

Set to enter Power-down mode.

Idle mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset value = 0001 0000b

Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset

doesn’t affect the value of this bit.

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Table 29. BDRCON Register

BDRCON - Baud Rate Control Register (9Bh)

7

-

6

-

5

-

4

3

2

1

0

BRR

TBCK

RBCK

SPD

SRC

Bit

Number

Mnemonic

Description

Reserved

7

6

5

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Baud Rate Run Control bit

4

3

2

1

0

BRR

TBCK

RBCK

SPD

Clear to stop the internal Baud Rate Generator.

Set to start the internal Baud Rate Generator.

Transmission Baud rate Generator Selection bit for UART

Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Reception Baud Rate Generator Selection bit for UART

Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Baud Rate Speed Control bit for UART

Clear to select the SLOW Baud Rate Generator.

Set to select the FAST Baud Rate Generator.

Baud Rate Source select bit in Mode 0 for UART

SRC

Clear to select F_OSC/12 as the Baud Rate Generator (F_OSC/6 in X2 mode).

Set to select the internal Baud Rate Generator for UARTs in mode 0.

Reset value = XXX0 0000b

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4191B–8051–04/03

Serial Port Interface

(SPI)

The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous,

serial communication between the MCU and peripheral devices, including other MCUs.

Features

Features of the SPI module include the following:

•

Full-duplex, three-wire synchronous transfers

Master operation

Eight programmable Master clock rates

Serial clock with programmable polarity and phase

Master Mode fault error flag with MCU interrupt capability

Write collision flag protection

Signal Description

Figure 12 shows a typical SPI bus configuration using one Master controller and many

Slave peripherals. The bus is made of three wires connecting all the devices:

Figure 12. Typical SPI bus

Slave 1

MISO

MOSI

SCK

SS

V_DD

Master

0

1

2

3

Slave 4

Slave 3

Slave 2

The Master device selects the individual Slave devices by using four pins of a parallel

port to control the four SS pins of the Slave devices.

Master Output Slave Input

(MOSI)

This 1-bit signal is directly connected between the Master Device and a Slave Device.

The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,

it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word)

is transmitted most significant bit (MSB) first, least significant bit (LSB)last.

Master Input Slave Output

(MISO)

This 1-bit signal is directly connected between the Slave Device and a Master Device.

The MISO line is used to transfer data in series from the Slave to the Master. Therefore,

it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit

word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

SPI Serial Clock (SCK)

Slave Select (SS)

This signal is used to synchronize the data movement both in and out the devices

through their MOSI and MISO lines. It is driven by the Master for eight clock cycles

which allows to exchange one byte on the serial lines.

Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay

low for any message for a Slave. It is obvious that only one Master (SS high level) can

drive the network. The Master may select each Slave device by software through port

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pins (Figure 12). To prevent bus conflicts on the MISO line, only one slave should be

selected at a time by the Master for a transmission.

In a Master configuration, the SS line can be used in conjunction with the MODF flag in

the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and

SCK (See Error Conditions).

Baud Rate

In Master mode, the baud rate can be selected from a baud rate generator which is con-

troled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is

chosen from one of seven clock rates resulting from the division of the internal clock by

2, 4, 8, 16, 32, 64 or 128, or an external clock.

Table 30 gives the different clock rates selected by SPR2:SPR1:SPR0:

Table 30. SPI Master Baud Rate Selection

SPR2:SPR1:SPR0

Clock Rate

Baud Rate Divisor (BD)

000

001

010

011

100

101

110

111

F

_CkIdle/2

_CkIdle/4

_CkIdle/8

_CkIdle/16

_CkIdle/32

2

4

F

8

F

16

F

32

F

_CkIdleH/64

_CkIdle/128

64

128

F

External clock

Output of BRG

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4191B–8051–04/03

Functional Description

Figure 13 shows a detailed structure of the SPI module.

Figure 13. SPI Module Block Diagram

Internal Bus

SPDAT

Shift Register

CkIdle

7

6

5

4

3

2

1

0

/2

/4

/8

/16

/32

/64

/128

Clock

Divider

Receive Data Register

Control

Logic

MOSI

MISO

Clock

Logic

M

S

SCK

SS

Clock

Select

External Clk

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPCON

8-bit bus

SPI

Control

1-bit signal

SPI Interrupt Request

SPSTA

-

MODF

SPIF WCOL

Operating Modes

The Serial Peripheral Interface can be configured as Master mode only. The configura-

tion and initialization of the SPI module is made through one register:

•

The Serial Peripheral CONtrol register (SPCON)

Once the SPI is configured, the data exchange is made using:

•

SPCON

The Serial Peripheral STAtus register (SPSTA)

The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and

received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-

pling on the two serial data lines (MOSI and MISO).

When the Master device transmits data to the Slave device via the MOSI line, the Slave

device responds by sending data to the Master device via the MISO line. This implies

full-duplex transmission with both data out and data in synchronized with the same clock

(Figure 14).

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Figure 14. Full-Duplex Master-slave Interconnection

MISO

MOSI

MISO

8-bit Shift register

MOSI

SCK

SPI

SCK

SS

Clock Generator

SS

VDD

Master MCU

Slave MCU

VSS

Master Mode

The SPI operates in Master mode. Only one Master SPI device can initiate transmis-

sions. Software begins the transmission from a Master SPI module by writing to the

Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is imme-

diately transferred to the shift register. The byte begins shifting out on MOSI pin under

the control of the serial clock, SCK. Simultaneously, another byte shifts in from the

Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral

transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes

set, the received byte from the Slave is transferred to the receive data register in

SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA)

with the SPIF bit set, and then reading the SPDAT.

When the pin SS is pulled down during a transmission, the data is interrupted and when

the transmission is established again, the data present in the SPDAT is present.

Transmission Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity

using two bits in the SPCON: the Clock POLarity (CPOL ⁽¹⁾) and the Clock PHAse

(CPHA⁽¹⁾). CPOL defines the default SCK line level in idle state. It has no significant

effect on the transmission format. CPHA defines the edges on which the input data are

sampled and the edges on which the output data are shifted (Figure 15 and Figure 16).

The clock phase and polarity should be identical for the Master SPI device and the com-

municating Slave device.

Figure 15. Data Transmission Format (CPHA = 0)

1

2

3

4

5

6

7

8

SCK cycle number

SPEN (internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI (from Master)

MISO (from Slave)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MSB

SS (to Slave)

Capture point

1.

Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).

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4191B–8051–04/03

Figure 16. Data Transmission Format (CPHA = 1)

1

2

3

4

5

6

7

8

SCK cycle number

SPEN (internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MOSI (from Master)

LSB

MISO (from Slave)

SS (to Slave)

Capture point

As shown in Figure 15, the first SCK edge is the MSB capture strobe. Therefore the

Slave must begin driving its data before the first SCK edge, and a falling edge on the SS

pin is used to start the transmission. The SS pin must be toggled high and then low

between each byte transmitted (Figure 17).

Figure 17. CPHA/SS timing

Byte 3

MISO/MOSI

Master SS

Byte 1

Byte 2

Slave SS

(CPHA = 0)

Slave SS

(CPHA = 1)

Figure 16 shows an SPI transmission in which CPHA is ’1’. In this case, the Master

begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first

SCK edge as a start transmission signal. The SS pin can remain low between transmis-

sions (Figure 17). This format may be preferable in systems having only one Master and

only one Slave driving the MISO data line.

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Error Conditions

The following flags in the SPSTA signal SPI error conditions:

Mode Fault (MODF)

MODe Fault error in Master mode SPI indicates that the level on the Slave Select (SS)

pin is inconsistent with the actual mode of the device. MODF is set to warn that there

may be a multi-master conflict for system control. In this case, the SPI system is

affected in the following ways:

•

An SPI receiver/error CPU interrupt request is generated.

The SPEN bit in SPCON is cleared. This disables the SPI.

The MSTR bit in SPCON is cleared.

The MODF flag is set when the SS signal becomes ’0’.

However, as stated before, for a system with one Master, if the SS pin of the Master

device is pulled low, there is no way that another Master is attempting to drive the net-

work. In this case, c learing the MODF bit is accomplished by a read of SPSTA register

with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be

restored to its original set state after the MODF bit has been cleared.

Write Collision (WCOL)

A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is

done during a transmit sequence.

WCOL does not cause an interruption, and the transfer continues uninterrupted.

Clearing the WCOL bit is done through a software sequence of an access to SPSTA

and an access to SPDAT.

Overrun Condition

An overrun condition occurs when the Master device tries to send several data bytes

and the Slave device has not cleared the SPIF bit issuing from the previous data byte

transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was

last cleared. A read of the SPDAT returns this byte. All others bytes are lost.

This condition is not detected by the SPI peripheral.

Interrupts

Two SPI status flags can generate a CPU interrupt request:

Table 31. SPI Interrupts

Flag

Request

SPIF (SP data transfer)

MODF (Mode Fault)

SPI Transmitter Interrupt request

SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)

Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer

has been completed. SPIF bit generates transmitter CPU interrupt requests.

Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is

inconsistent with the mode of the SPI. MODF generates receiver/error CPU interrupt

requests.

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4191B–8051–04/03

Figure 18 gives a logical view of the above statements:

Figure 18. SPI Interrupt Requests Generation

SPIF

SPI Transmitter

CPU Interrupt Request

SPI

CPU Interrupt Request

MODF

SSDIS

SPI Receiver/error

CPU Interrupt Request

Registers

There are three registers in the module that provide control, status and data storage

functions. These registers are described in the following paragraphs.

Serial Peripheral Control

Register (SPCON)

The Serial Peripheral Control Register does the following:

•

Selects one of the Master clock rates,

Selects serial clock polarity and phase,

Enables the SPI module.

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Table 32 describes this register and explains the use of each bit:

Table 32. Serial Peripheral Control Register

7

6

5

4

3

2

1

0

SPR2

SPEN

–

CPOL

CPHA

SPR1

SPR0

Bit

Number

Mnemonic R/W Mode Description

Serial Peripheral Rate 2

7

6

SPR2

SPEN

RW

Bit with SPR1 and SPR0 define the clock rate

Serial Peripheral Enable

Clear to disable the SPI interface

Set to enable the SPI interface

Reserved

5

4

-

RW

Leave this Bit at 0.

Reserved

Leave this Bit at 1.

Clock Polarity

3

2

CPOL

CPHA

RW

Clear to have the SCK set to ’0’ in idle state

Set to have the SCK set to ’1’ in idle low

Clock Phase

Clear to have the data sampled when the SPSCK leaves the idle

state (see CPOL)

Set to have the data sampled when the SPSCK returns to idle

state (see CPOL)

Serial Peripheral Rate (SPR2:SPR1:SPR0)

000: F_CkIdle/2

1

0

SPR1

SPR0

RW

001: F_CkIdle/4

010: F_CkIdle/8

011: F_CkIdle/16

100: F_CkIdle/32

101: F_CkIdle/64

110: F_CkIdle/128

111: External clock, output of BRG

Reset value = 00010100b

Serial Peripheral Status Register The Serial Peripheral Status Register contains flags to signal the following conditions:

(SPSTA)

•

Data transfer complete

Write collision

Inconsistent logic level on SS pin (mode fault error)

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4191B–8051–04/03

Table 33 describes the SPSTA register and explains the use of every bit in the register:

Table 33. Serial Peripheral Status and Control Register

7

6

5

4

3

2

1

0

SPIF

WCOL

-

MODF

-

Bit

R/W

Number Mnemonic Mode Description

Serial Peripheral data transfer flag

Cleared by hardware to indicate data that transfer is in progress or has

been approved by a clearing sequence.

7

SPIF

R

Set by hardware to indicate that the data transfer has been completed.

Write Collision flag

Cleared by hardware to indicate that no collision has occurred or has

been approved by a clearing sequence.

6

5

WCOL

R

Set by hardware to indicate that a collision has been detected.

Reserved

-

RW

The value read from this bit is indeterminate. Do not set this bit

Mode Fault

Cleared by hardware to indicate that the SS pin is at appropriate logic

level, or has been approved by a clearing sequence.

4

MODF

R

Set by hardware to indicate that the SS pin is at inappropriate logic

level

Reserved

3

2

1

0

-

RW

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reset value = 00X0XXXXb

Serial Peripheral Data Register

(SPDAT)

The Serial Peripheral Data Register (Table 34) is a read/write buffer for the receive data

register. A write to SPDAT places data directly into the shift register. No transmit buffer

is available in this model.

A Read of the SPDAT returns the value located in the receive buffer and not the content

of the shift register.

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Table 34. Serial Peripheral Data Register

7

6

5

4

3

2

1

0

R7

R6

R5

R4

R3

R2

R1

R0

Reset value = XXXX XXXXb

R7:R0: Receive data bits

SPCON, SPSTA and SPDAT registers may be read and written at any time while there

is no on-going exchange. However, special care should be taken when writing to them

while a transmission is on-going:

•

Do not change SPR2, SPR1 and SPR0

Do not change CPHA and CPOL

Do not change MSTR

Clearing SPEN would immediately disable the peripheral

Writing to the SPDAT will cause an overflow

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4191B–8051–04/03

Analog-to-Digital

Converter (ADC)

This section describes the on-chip 10-bit analog-to-digital converter of the

T89C51RB2/RC2. Eight ADC channels are available for sampling of the external

sources AN0 to AN7. An analog multiplexer allows the single ADC to select one of the 8

ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-cas-

caded potentiometric ADC.

Three kind of conversions are available:

•

Standard conversion (7-8 bits).

Precision conversion (8-9 bits).

Accurate conversion (10 bits).

For the precision conversion, set bits PSIDLE and ADSST in ADCON register to start

the conversion. The chip is in a pseudo-idle mode, the CPU doesn’t run but the periph-

erals are always running. This mode allows digital noise to be lower, to ensure precise

conversion.

For the accurate conversion, set bits QUIETM and ADSST in ADCON register to start

the conversion. The chip is in a quiet mode, the AD is the only peripheral running. This

mode allows digital noise to be as low as possible, to ensure high precision conversion.

For these modes it is necessary to work with end of conversion interrupt, which is the

only way to wake up the chip.

If another interrupt occurs during the precision conversion, it will be treated only after

this conversion is ended.

Features

•

8 channels with multiplexed inputs

10 - bit cascaded potentiometric ADC

Conversion time down to 10 micro-seconds

Zero Error (offset) +/- 2 LSB max

External Positive Reference Voltage Range 2.4 to Vcc

ADCIN Range 0 to Vcc

Integral non-linearity typical 1 LSB, max. 2 LSB (with 0.9*Vcc<Vref<Vcc)

Differential non-linearity typical 0.5 LSB, max. 1 LSB (with 0.9*Vcc<Vref<Vcc)

Conversion Complete Flag or Conversion Complete Interrupt

Selected ADC Clock

ADC I/O Functions

AINx are general I/O that are shared with the ADC channels. The channel select bits in

ADCF register define which ADC channel pin will be used as ADCIN. The remaining

ADC channels pins can be used as general purpose I/O or as the alternate function that

is available. Writes to the port register which aren’t selected by the ADCF will not have

any effect.

46

AT8xC5112

4191B–8051–04/03

AT8xC5112

Figure 19. ADC Description

ADCON.5

ADCON.3

ADEN

ADSST

ADCON.4

ADC

Interrupt

Request

ADEOC

CONTROL

CONV_CK

EADC

IE1.1

AIN0/P4.0

AIN1/P4.1

AIN2/P4.2

AIN3/P4.3

AIN4/P4.4

AIN5/P4.5

AIN6/P4.6

AIN7/P4.7

000

001

010

011

100

101

110

111

8

2

ADCIN

ADDH

ADDL

+

SAR

-

AVSS

Sample and Hold

10

R/2R DAC

VAGND

ADCON.5

ADEN

SCH2

SCH1

SCH0

ADCON.2 ADCON.1 ADCON.0

Vref

VADREF

Figure 20 shows the timing diagram of a complete conversion. For simplicity, the figure

depicts the waveforms in idealized form and does not provide precise timing informa-

tion. For ADC characteristics and timing parameters refer to the Section “AC

Characteristics” of the AT8xC5112 datasheet.

Figure 20. Timing Diagram

CONV_CK

ADEN

T_SETUP

ADSST

ADEOC

T_CONV

Note:

Tsetup = 4 us

47

4191B–8051–04/03

ADC Operation

Before starting a conversion, the A/D converter must be enabled, by setting the ADEN

bit, for at least Tsetup (four microseconds).

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

From the ADSST set, the first full CONV_CK period will be the sampling period for the

ADC; during this period, the switch is closed and the capacitor is being charged. At the

end of the first period, the switch opens and the capacitor is no longer being charged.

During the next 10 CONV_CK periods, the sample and hold will be in hold mode during

the conversion. The busy flag ADSST(ADCON.3) remains set as long as an A/D conver-

sion is running. After completion of the A/D conversion, it is cleared by hardware. When

a conversion is running, this flag can be read only, a write has no effect.

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is

available in ADDH and ADDL, it is cleared by software. If the bit EADC (IE1.1) is set, an

interrupt occur when flag ADEOC is set (see Figure 22). Clear this flag for re-arming the

interrupt.

From this point, if you keep starting a new conversion by resetting ADSST without

changing ADEN, it is not necessary to wait Tsetup.

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel

selection.

Before starting normal power reduction modes the ADC conversion has to be com-

pleted.

Table 35. Selected Analog Input

SCH2

SCH1

SCH0

Selected Analog Input

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Voltage Conversion

When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between

VAREF and VAGND are a straight-line linear conversion. All other voltages will result in

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range.

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AT8xC5112

Clock Selection

The maximum clock frequency for ADC (CONV_CK for Conversion Clock) is defined in

the AC characteristics section. A prescaler is featured (ADCCLK) to generate the

CONV_CK clock from the oscillator frequency.

Figure 21. A/D Converter Clock

CONV_CK

CKADC

Prescaler ADCLK

/2

A/D

Converter

The conversion frequency CONV_CK is derived from the oscillator frequency with the

following formulas :

F

_CkAdc= F_OscOut/(512 - 2*CKRL) , if X2=0

= F_OscOut, if X2=1

and

F

_{CONV_CK}= F_CkAdc/(2*PRS), if PRS > 0

_{CONV_CK}= F_CkAdc/256, if PRS = 0

Some examples can be found in the table below:

ADC Standby Mode

F_OscOut

MHz

F_CkAdc

Mhz

F_{CONV_CK}

khz

Conversion

time µs

X2

0

CKRL

FF

ADCLK

12

16

8

333

250

33

44

1

NA

16

32

When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN

in ADCON register.

In this mode the power dissipation is about 1µW.

Voltage Reference

The Vref pin is used to enter the voltage reference for the A/D conversion.

Best accuracy is obtained with 0.9 Vcc < Vref < Vcc.

IT ADC Management

An interrupt end-of-conversion will occur when the bit ADEOC is activated and the bit

EADC is set. To re-arm the interrupt the bit ADEOC must be cleared by software.

Figure 22. ADC Interrupt Structure

ADCI

ADEOC

ADCON.2

EADC

IE1.1

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4191B–8051–04/03

Registers

Table 36. ADCON Register

ADCON (S:F3h)

ADC Control Register

7

6

5

4

3

2

1

0

QUIETM

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

Bit Number

Bit Mnemonic Description

Pseudo Idle mode (best precision)

Set to put in quiet mode during conversion.

Cleared by hardware after completion of the conversion.

7

QUIETM

PSIDLE

ADEN

Pseudo Idle mode (good precision)

Set to put in idle mode during conversion.

Cleared by hardware after completion of the conversion.

6

5

Enable/Standby Mode

Set to enable ADC.

Clear for Standby mode (power dissipation 1 uW).

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can

generate an interrupt.

4

ADEOC

Must be cleared by software.

Start and Status

3

ADSST

SCH2:0

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion.

Selection of channel to convert

see Table 35.

2 - 0

Reset value = X000 0000b

Table 37. ADCLK Register

ADCLK (S:F2h)

ADC Clock Prescaler

7

-

6

5

4

3

2

1

0

PRS 6

PRS 5

PRS 4

PRS 3

PRS 2

PRS 1

PRS 0

Bit Number

Bit Mnemonic Description

Reserved

7

–

Leave this bit at 0.

Clock Prescaler

f_{CONV_CK}= f_CkADC/(2 * PRS)

6 - 0

PRS6:0

if PRS=0, f_{CONV_CK}= f_CkADC/256

Reset value = 0000 0000b

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AT8xC5112

4191B–8051–04/03

AT8xC5112

Table 38. ADDH Register

ADDH (S:F5h Read Only)

ADC Data High byte register

7

6

5

4

3

2

1

0

ADAT 9

ADAT 8

ADAT 7

ADAT 6

ADAT 5

ADAT 4

ADAT 3

ADAT 2

Bit Number

Bit Mnemonic Description

ADC result

ADAT9:2

7 - 0

bits 9 - 2

Read only register

Reset value = 00h

Table 39. ADDL Register

ADDL (S:F4h Read Only)

ADC Data Low byte register

7

-

6

-

5

-

4

-

3

-

2

-

1

0

ADAT 1

ADAT 0

Bit Number Bit Mnemonic Description

Reserved

7 - 6

-

The value read from these bits are indeterminate. Do not set these bits.

ADC result

bits 1 - 0

1 - 0

ADAT1:0

Read only register

Reset value = xxxx xx00b

Table 40. ADCF Register

ADCF (S:F6h)

ADC Input Select Register

7

6

5

4

3

2

1

0

SEL7

SEL6

SEL5

SEL4

SEL3

SEL2

SEL1

SEL0

Bit Number Bit Mnemonic Description

Select Input 7 - 0

7 - 0

SEL7 - 0

Set to select bit 7 - 0 as possible input for A/D

Cleared to leave this bit free for other function

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4191B–8051–04/03

Programmable

Counter Array (PCA)

The PCA provides more timing capabilities with less CPU intervention than the standard

timer/counters. Its advantages include reduced software overhead and improved accu-

racy. The PCA consists of a dedicated timer/counter which serves as the time base for

an array of five compare/capture modules. Its clock input can be programmed to count

any one of the following signals:

•

^{Oscillator frequency}÷ 12 (÷ 6 in X2 mode)

^{Oscillator frequency}÷ 4 (÷ 2 in X2 mode)

Timer 0 overflow

External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

•

rising and/or falling edge capture

software timer

high-speed output, or

pulse width modulator

Module 4 can also be programmed as a watchdog timer (See Section "PCA PWM

Mode", page 61).

When the compare/capture modules are programmed in the capture mode, software

timer, or high speed output mode, an interrupt can be generated when the module exe-

cutes its function. All five modules plus the PCA timer overflow share one interrupt

vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/O.

These pins are listed below. If the port is not used for the PCA, it can still be used for

standard I/O.

PCA Component

16-bit Counter

16-bit Module 0

16-bit Module 1

16-bit Module 2

16-bit Module 3

16-bit Module 4

External I/O Pin

P1.2/ECI

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

The PCA timer is a common time base for all five modules (See Figure 23). The timer

count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See

Table 41) and can be programmed to run at:

•

1/12 the oscillator frequency. (Or 1/6 in X2 Mode)

1/4 the oscillator frequency. (Or 1/2 in X2 Mode)

The Timer 0 overflow.

The input on the ECI pin (P1.2).

52

AT8xC5112

4191B–8051–04/03

AT8xC5112

Figure 23. PCA Timer/Counter

To PCA

modules

Fosc /12

Fosc/4

T0 OVF

P1.2

overflow

It

CH

CL

16 bit up/down counter

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Idle

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

Table 41. CMOD: PCA Counter Mode Register: CMOD Address 0D9H

7

6

5

4

3

2

1

0

CIDL

WDTE

-

CPS1

CPS0

ECF

Bit

Number Mnemonic Description

Counter Idle control:

7

6

CIDL

CIDL = 0 programs the PCA Counter to continue functioning during idle Mode.

CIDL = 1 programs it to be gated off during idle.

Watchdog Timer Enable:

WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1

enables it.

WDTE

5

4

3

-

Not implemented, reserved for future use. ⁽¹⁾

Not implemented, reserved for future use.

CPS1

CPS0

Selected PCA input ⁽²⁾

0

1

0

1

0

1

Internal clock f_osc/12 ( Or f_osc/6 in X2 Mode).

Internal clock f_osc/4 ( Or f_osc/2 in X2 Mode).

Timer 0 Overflow

2

CPS1

External clock at ECI/P1.2 pin (max rate = f_osc/ 8)

1

0

CPS0

ECF

PCA Count Pulse Select bit 0.

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to

generate an interrupt. ECF = 0 disables that function of CF.

Reset value = 00XXX00

1. User software should not write 1s to reserved bits. These bits may be used in future 8051

family products to invoke new features. In that case, the reset or inactive value of the

new bit will be 0, and its active value will be 1. The value read from a reserved bit is

indeterminate.

53

4191B–8051–04/03

2.

f_osc= oscillator frequency

The CMOD SFR includes three additional bits associated with the PCA (See Figure 23

and Table 41).

•

The CIDL bit which allows the PCA to stop during idle mode.

The WDTE bit which enables or disables the watchdog function on module 4.

The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in

the CCON SFR) to be set when the PCA timer overflows.

The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer

(CF) and each module (Refer to Table 42).

•

Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by

clearing this bit.

•

Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an

interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can

only be cleared by software.

•

Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,

etc.) and are set by hardware when either a match or a capture occurs. These flags

also can only be cleared by software.

Table 42. CCON: PCA Counter Control Register

CCON Address OD8H

7

6

5

4

3

2

1

0

CF

CR

-

CCF4

CCF3

CCF2

CCF1

CCF0

Bit

Number Mnemonic Description

PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags

an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or

software but can only be cleared by software.

7

CF

PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be

cleared by software to turn the PCA counter off.

6

5

4

CR

-

Not implemented, reserved for future use. ⁽¹⁾

PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

CCF4

PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

3

2

1

0

CCF3

CCF2

CCF1

CCF0

PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs.

Must be cleared by software.

1.

User software should not write 1s to reserved bits. These bits may be used in future 8051

family products to invoke new features. In that case, the reset or inactive value of the

new bit will be 0, and its active value will be 1. The value read from a reserved bit is

indeterminate.

The watchdog timer function is implemented in module 4 (See Figure 26).

54

AT8xC5112

4191B–8051–04/03

AT8xC5112

The PCA interrupt system is shown in Figure 24 below.

Figure 24. PCA Interrupt System

CCON

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

0xD8

PCA Timer/Counter

Module 0

Module 1

Module 2

Module 3

To Interrupt

priority decoder

Module 4

CMOD.0

IE.6

EC

IE.7

EA

CCAPMn.0

ECCFn

ECF

PCA Modules: each one of the five compare/capture modules has six possible func-

tions. It can perform:

•

16-bit Capture, positive-edge triggered,

16-bit Capture, negative-edge triggered,

16-bit Capture, both positive and negative-edge triggered,

16-bit Software Timer,

16-bit High Speed Output,

8-bit Pulse Width Modulator.

In addition, module 4 can be used as a Watchdog Timer.

Each module in the PCA has a special function register associated with it. These regis-

ters are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 43). The

registers contain the bits that control the mode that each module will operate in.

•

The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)

enables the CCF flag in the CCON SFR to generate an interrupt when a match or

compare occurs in the associated module.

•

PWM (CCAPMn.1) enables the pulse width modulation mode.

The TOG bit (CCAPMn.2) when set causes the CEX output associated with the

module to toggle when there is a match between the PCA counter and the module's

capture/compare register.

•

The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON

register to be set when there is a match between the PCA counter and the module's

capture/compare register.

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge

that a capture input will be active on. The CAPN bit enables the negative edge, and

the CAPP bit enables the positive edge. If both bits are set both edges will be

enabled and a capture will occur for either transition.

55

4191B–8051–04/03

•

The last bit in the register ECOM (CCAPMn.6) when set enables the comparator

function.

Table 43 shows the CCAPMn settings for the various PCA functions.

Table 43. CCAPMn: PCA Modules Compare/Capture Control Registers

CAPMn Address n = 0 - 4

7

-

6

5

4

3

2

1

0

ECOMn

CAPPn

CAPn

MATn

TOGn

PWMm

ECCFn

Bit

Number Mnemonic Description

7

6

5

4

-

Not implemented, reserved for future use. ⁽¹⁾

ECOMn

CAPPn

CAPNn

Enable Comparator. ECOMn = 1 enables the comparator function.

Capture Positive, CAPPn = 1 enables positive edge capture.

Capture Negative, CAPNn = 1 enables negative edge capture.

Match. When MATn = 1, a match of the PCA counter with this module’s

3

MATn

compare/capture register causes the CCFn bit in CCON to be set, flagging an

interrupt.

Toggle. When TOGn = 1, a match of the PCA counter with this module’s

compare/capture register causes the CEXn pin to toggle.

2

1

0

TOGn

PWMn

ECCFn

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a

pulse width modulated output.

Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register

to generate an interrupt.

Reset value = X000000

1. User software should not write 1s to reserved bits. These bits may be used in future 8051

family products to invoke new features. In that case, the reset or inactive value of the

new bit will be 0, and its active value will be 1. The value read from a reserved bit is

indeterminate.

Table 44. PCA Module Modes (CCAPMn Registers)

ECOMn CAPPn CAPNn MATn

TOGn PWMm ECCFn Module Function

0

1

0

No Operation

16-bit capture by a positive-edge

trigger on CEXn

X

16-bit capture by a negative trigger

on CEXn

X

1

0

1

0

1

0

1

0

X

16-bit capture by a transition on

CEXn

16-bit Software Timer/Compare

mode.

1

0

1

0

1

0

X

0

1

0

X

0

16-bit High Speed Output

8-bit PWM

X

Watchdog Timer (module 4 only)

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4191B–8051–04/03

AT8xC5112

There are two additional registers associated with each of the PCA modules. They are

CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a

capture occurs or a compare should occur. When a module is used in the PWM mode

these registers are used to control the duty cycle of the output (See Table & Table 46)

Table 45. CCAPnH: PCA Modules Capture/Compare Registers High

CCAP0H=0FAH

CCAP1H=0FBH

CCAP2H=0FCH

CCAP3H=0FDH

CCAP4H=0FEH

CCAPnH Address

n = 0 - 4

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset value

Table 46. CCAPnL: PCA Modules Capture/Compare Registers Low

CCAP0L=0EAH

CCAP1L=0EBH

CCAP2L=0ECH

CCAP3L=0EDH

CCAPnL Address

n = 0 - 4

CCAP4L=0EEH

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset value

Table 47. CH: PCA Counter High

CH

Address 0F9H

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset value

Table 48. CL: PCA Counter Low

CL

Address 0E9H

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset value

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4191B–8051–04/03

PCA Capture Mode

To use one of the PCA modules in the capture mode either one or both of the CCAPM

bits CAPN and CAPP for that module must be set. The external CEX input for the mod-

ule (on port 1) is sampled for a transition. When a valid transition occurs the PCA

hardware loads the value of the PCA counter registers (CH and CL) into the module’s

capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON

SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated

(Refer to Figure 25).

Figure 25. PCA Capture Mode

CCON

CCF4 CCF3 CCF2 CCF1 CCF0

CF

CR

0xD8

PCA IT

PCA Counter/Timer

Cex.n

CH

CL

Capture

CCAPnH

CCAPnL

CCAPMn, n= 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

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4191B–8051–04/03

AT8xC5112

16-bit Software Timer/

Compare Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT

bits in the modules CCAPMn register. The PCA timer will be compared to the module’s

capture registers and when a match occurs an interrupt will occur if the CCFn (CCON

SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 26).

Figure 26. PCA Compare Mode and PCA Watchdog Timer

CCON

0xD8

CCF4

CCF3 CCF2 CCF1 CCF0

CF

CR

Write to

CCAPnL Reset

PCA IT

Write to

CCAPnH

CCAPnL

Enable

1

0

Match

16 bit comparator

RESET ⁽¹⁾

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Note:

1. Only for Module 4

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,

otherwise an unwanted match could occur. Writing to CCAPnH will set the ECOM bit.

Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t

occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this

reason, user software should write CCAPnL first, and then CCAPnH. Of course, the

ECOM bit can still be controlled by accessing to CCAPMn register.

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4191B–8051–04/03

High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle

each time a match occurs between the PCA counter and the module’s capture registers.

To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR

must be set (See Figure 27).

A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

Figure 27. PCA High Speed Output Mode

CCON

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

0xD8

Write to

CCAPnL

Reset

PCA IT

Write to

CCAPnH

CCAPnL

0

Enable

1

Match

16 bit comparator

CEXn

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,

otherwise an unwanted match could happen.

Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t

occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this

reason, user software should write CCAPnL first, and then CCAPnH. Of course, the

ECOM bit can still be controlled by accessing to CCAPMn register.

Pulse Width Modulator

Mode

All of the PCA modules can be used as PWM outputs. Figure 28 shows the PWM func-

tion. The frequency of the output depends on the source for the PCA timer. All of the

modules will have the same frequency of output because they all share the PCA timer.

The duty cycle of each module is independently variable using the module's capture

register CCAPLn. When the value of the PCA CL SFR is less than the value in the mod-

ule's CCAPLn SFR the output will be low, when it is equal to or greater than, the output

will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in

CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in

the module's CCAPMn register must be set to enable the PWM mode.

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4191B–8051–04/03

AT8xC5112

Figure 28. PCA PWM Mode

CCAPnH

Overflow

CCAPnL

“0”

“1”

CEXn

Enable

<

8 bit comparator

>

CL

PCA counter/timer

CCAPMn, n= 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

An on-board watchdog timer is available with the PCA to improve the reliability of the

system without increasing chip count. Watchdog timers are useful for systems that are

susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only

PCA module that can be programmed as a watchdog. However, this module can still be

used for other modes if the watchdog is not needed. Figure 26 shows a diagram of how

the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just

like the other compare modes, this 16-bit value is compared to the PCA timer value. If a

match is allowed to occur, an internal reset will be generated. This will not cause the

RST pin to be driven high.

In order to hold off the reset, the user has three options:

•

periodically change the compare value so it will never match the PCA timer

periodically change the PCA timer value so it will never match the compare values

or

•

disable the watchdog by clearing the WDTE bit before a match occurs and then re-

enable it.

The first two options are more reliable because the watchdog timer is never disabled as

in option #3. If the program counter ever goes astray, a match will eventually occur and

cause an internal reset. The second option is also not recommended if other PCA mod-

ules are being used. Remember, the PCA timer is the time base for all modules;

changing the time base for other modules would not be a good idea. Thus, in most appli-

cations the first solution is the best option.

This watchdog timer won’t generate a reset out on the reset pin.

61

4191B–8051–04/03

ROM

ROM Structure

The T83C5112 ROM memory is divided in three different arrays:

•

the code array: 8K bytes

the encryption array: 64 bytes

the signature array: 4 bytes

ROM Lock System

The program Lock system, when programmed, protects the on-chip program against

software piracy.

Encryption Array

Within the ROM array are 64 bytes of encryption array. Every time a byte is addressed

during program verify, 6 address lines are used to select a byte of the encryption array.

This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted

verify byte. The algorithm, with the encryption array in the unprogrammed state, will

return the code in its original, unmodified form.

When using the encryption array, one important factor needs to be considered. If a byte

has the value FFh, verifying the byte will produce the encryption byte value. If a large

block (>64 bytes) of code is left unprogrammed, a verification routine will display the

content of the encryption array. For this reason all the unused code bytes should be pro-

grammed with random values.

Program Lock Bits

The lock bits when programmed according to Table 41. will provide different level of pro-

tection for the on-chip code and data.

Program Lock Bits

Security

level

LB1

LB2

Protection Description

No program lock features enabled. Code verify will still be encrypted by

the encryption array if programmed. MOVC instruction executed from

external program memory returns non encrypted data.

1

U

MOVC instruction executed from external program memory are disabled

from fetching code bytes from internal memory, EA is sampled and latched

on reset.

2

3

P

U

P

Same as 2, also verify is disabled

This security level is available because ROM integrity will be verified

thanks to another method.

U: unprogrammed

P: programmed

Signature Bytes

Verify Algorithm

The T83C5112 contains 4 factory programmed signatures bytes. To read these bytes,

perform the process described in Section “Signature Bytes”, page 72.

Refer to Section “Verify Algorithm”, page 74.

62

AT8xC5112

4191B–8051–04/03

AT8xC5112

Interrupt System

The AT8xC5112 has a total of 8 interrupt vectors: two external interrupts (INT0 and

INT1), two timer interrupts (timers 0, 1), serial port interrupt, PCA, SPI and A/D. These

interrupts are shown in Figure 29.

Figure 29. Interrupt Control System

High priority

IPH, IP

interrupt

3

INT0

IE0

0

3

0

TF0

Interrupt

3

INT1

IE1

polling

0

3

0

sequence

TF1

CF

3

PCA

0

CCFx

3

RI

TI

0

3

0

NC

3

SPI

0

3

ADC

0

Global

disable

Individual

enable

Low priority

interrupt

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register (See Table 51). This register also contains a

global disable bit, which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one of four priority levels

by setting or clearing a bit in the Interrupt Priority register (See Table 53) and in the

Interrupt Priority High register (See Table 55). Table 49 shows the bit values and priority

levels associated with each combination.

63

4191B–8051–04/03

Table 49. Priority Bit Level Values

IPH.x

IP.x

0

Interrupt Level Priority

0

1

0 (Lowest)

1

0

2

1

3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of higher priority level is serviced. If interrupt requests of the same priority level

are received simultaneously, an internal polling sequence determines which request is

serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

Table 50. Address Vectors

Interrupt Name

external interrupt (INT0)

Timer0 (TF0)

Interrupt Address Vector

Priority Number

0003h

000Bh

0013h

001Bh

0033h

0023h

004Bh

0043h

1

2

3

4

5

6

8

9

external interrupt (INT1)

Timer1 (TF1)

PCA (CF or CCFn)

UART (RI or TI)

SPI

ADC

64

AT8xC5112

4191B–8051–04/03

AT8xC5112

Table 51. IE0 Register

IE0 - Interrupt Enable Register (A8H)

7

6

5

4

3

2

1

0

EA

EC

-

ES

ET1

EX1

ET0

EX0

Bit

Number

Bit

Mnemonic Description

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

7

EA

If EA=1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

PCA Interrupt Enable

6

5

4

EC

-

Clear to disable the the PCA interrupt.

Set to enable the the PCA interrupt.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Serial port Enable bit

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

ES

Timer 1 overflow interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

3

2

1

0

ET1

EX1

ET0

EX0

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

Reset value = 00X0 0000b

Bit addressable

65

4191B–8051–04/03

Table 52. IE1 Register

IE1 (S:B1H) - Interrupt Enable Register

7

-

6

-

5

-

4

-

3

-

2

1

0

-

ESPI

EADC

Bit

Number Mnemonic Description

Reserved

7

6

5

4

3

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Enable bit

2

ESPI

Clear to disable the SPI interrupt.

Set to enable the SPI interrupt.

A/D Interrupt Enable bit

1

0

EADC

-

Clear to disable the ADC interrupt.

Set to enable the ADC interrupt.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset value = XXXX X00Xb

No Bit addressable

66

AT8xC5112

4191B–8051–04/03

AT8xC5112

Table 53. IPL0 Register

IPL0 - Interrupt Priority Register (B8H)

7

6

5

4

3

2

1

0

-

PPC

-

PS

PT1

PX1

PT0

PX0

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

PCA Counter Interrupt Priority bit

Refer to PPCH for priority level

PPC

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Serial port Priority bit

Refer to PSH for priority level.

PS

Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

PT1

PX1

PT0

PX0

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

Reset value = X0X0 0000b

Bit addressable.

67

4191B–8051–04/03

Table 54. IPL1 Register

IPL1 - Interrupt Priority Low Register 1 (S:B2H)

7

6

5

4

3

2

1

0

-

PSPI

PADC

-

Bit

Number Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Priority level less significant bit.

Refer to PSPIH for priority level.

PSPI

PADC

-

ADC Interrupt Priority level less significant bit.

Refer to PADCH for priority level.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset value = XXXX X00Xb

Not Bit addressable.

68

AT8xC5112

4191B–8051–04/03

AT8xC5112

Table 55. IPH0 Register

IPH0 - Interrrupt Priority High Register

7

6

5

4

3

2

1

0

-

PPCH

-

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Number Mnemonic Description

Reserved

7

6

5

4

-

PPCH

-

The value read from this bit is indeterminate. Do not set this bit.

PCA Counter Interrupt Priority level most significant bit

PPCH

PPC

Priority Level

0

1

Lowest

1

0

1

Highest

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Serial port Priority High bit

PSH

PS Priority Level

0

1

Lowest

PSH

1

0

1

Highest

Timer 1 overflow interrupt Priority High bit

PT1H

PT1

0

Priority Level

0

Lowest

3

2

1

0

PT1H

PX1H

PT0H

PX0H

1

0

1

Highest

External interrupt 1 Priority High bit

PX1H

PX1

Priority Level

0

Lowest

1

0

1

Highest

Timer 0 overflow interrupt Priority High bit

PT0H

PT0

0

Priority Level

0

Lowest

1

0

1

Highest

External interrupt 0 Priority High bit

PX0H

PT0

0

Priority Level

0

Lowest

1

0

1

Highest

Reset value = X0X0 0000b

Not bit addressable

69

4191B–8051–04/03

Table 56. IPH1 Register

IPH1 - Interrupt High Register 1 (B3H)

7

6

5

4

3

2

1

0

-

PSPIH

PADCH

-

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Priority level most significant bit

PSP1H PSP1

Priority Level

0

1

Lowest

2

PSPIH

1

0

1

Highest

ADC Interrupt Priority level most significant bit

PADCH PADC

Priority Level

0

1

Lowest

1

0

PADCH

1

0

1

Highest

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reset value = XXXX X00Xb

Not bit addressable

70

AT8xC5112

4191B–8051–04/03

AT8xC5112

EPROM

EPROM Structure

The T87C5112 EPROM is divided into two different arrays:

•

the code array: 8K bytes

the encryption array: 64 bytes

In addition a third non programmable array is implemented:

the signature array: 4 bytes

•

EPROM Lock System

The program Lock system, when programmed, protects the on-chip program against

software piracy.

Encryption Array

Within the EPROM array are 64 bytes of encryption array that are initially unpro-

grammed (all FF’s). Every time a byte is addressed during program verify, 6 address

lines are used to select a byte of the encryption array. This byte is then exclusive-

NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm,

with the encryption array in the unprogrammed state, will return the code in its original,

unmodified form.

When using the encryption array, one important factor needs to be considered. If a byte

has the value FFh, verifying the byte will produce the encryption byte value. If a large

block (>64 bytes) of code is left unprogrammed, a verification routine will display the

content of the encryption array. For this reason all the unused code bytes should be pro-

grammed with random values.

Program Lock Bits

The three lock bits located in the CONF byte, when programmed according to Table will

provide different levels of protection for the on-chip code and data.

Table 57. Program Lock Bits

Program Lock Bits

Security level

LB1

LB2

LB3

Protection Description

No program lock features enabled. Code verify will still be encrypted by the encryption

array if programmed. MOVC instruction executed from external program memory returns

non encrypted data.

1

U

MOVC instruction executed from external program memory are disabled from fetching

code bytes from internal memory, EA is sampled and latched on reset, and further

programming of the EPROM is disabled.

2

P

U

Same as 2, also verify is disabled

3

4

U

P

U

P

This security level is available because ROM integrity will be verified thanks to another

method.

Same as 3, also external execution is disabled.

U: unprogrammed

P: programmed

WARNING: Security level 2 and higher should only be programmed after EPROM verification.

71

4191B–8051–04/03

Configuration Byte

The configuration byte is a special register. Its content is defined by the diffusion mask

in the ROM version or is read or written by the OTP programmer in the OTP version.

This register can also be accessed as a read only register.

Table 58. CONF - Configuration Byte (EFh)

7

6

5

4

1

3

1

2

1

0

1

LB1

LB2

LB3

Bit Number

Bit Mnemonic Description

Program memory lock bits

See previous chapter for the definition of these bits.

7:5

-

Reserved

4

3

2

1

0

Leave this bit at 1.

-

Reserved

Leave this bit at 1.

Reserved

Leave this bit at 1.

Reserved

Leave this bit at 1.

Reserved

Leave this bit at 1.

Reset value = 1111 111X

Signature Bytes

The T87C5112 contains 4 factory programmed signatures bytes. To read these bytes,

perform the process described in Section .

EPROM Programming

Set-up Modes

In order to program and verify the EPROM or to read the signature bytes, the T87C5112

is placed in specific set-up modes (See Figure 30.).

Control and program signals must be held at the levels indicated in

Definition of Terms

Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4, P3.5 respectively for A0-A15 (P2.5 (A13)

for RB, P3.4 (A14) for RC, P3.5 (A15) for RD)

Data Lines:P0.0-P0.7 for D0-D7

Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.

Program Signals:ALE/PROG, RST/VPP.

72

AT8xC5112

4191B–8051–04/03

AT8xC5112

Table 59. EPROM Set-up Modes

ALE/PR

OG

Mode

RST

PSEN

RST/VPP

P2.6

P2.7

P3.3

P3.6

P3.7

Program Code data

1

0

12.75V

0

1

Verify Code data

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Program Encryption Array Address 0-3Fh

Read Signature Bytes

Program Lock bit 1

12.75V

1

12.75V

1

0

Program Lock bit 2

Program Lock bit 3

Program CONF byte

Read CONF byte

1

Figure 30. Set-up Modes Configuration

+5V

RST/VPP

ALE/PROG

VCC

PROGRAM

SIGNALS*

P0.0-P0.7

D0-D7

EA

+5V

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

P1.0-P1.7

A0-A7

CONTROL

SIGNALS*

A8-A15

P2.0-P2.5

P3.4-P3.5

4 to 6 MHz

XTAL1

VSS

GND

* See for proper value on these inputs

73

4191B–8051–04/03

Programming Algorithm

The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and

decreases the number of pulses applied during byte programming from 25 to 1.

To program the AT8xC5112 the following sequence must be exercised:

•

Step 1: Activate the combination of control signals.

Step 2: Input the valid address on the address lines.

Step 3: Input the appropriate data on the data lines.

Step 4: Raise RST/VPP from VCC to VPP (typical 12.75V).

Step 5: Pulse ALE/PROG once.

Step 6: Lower RST/VPP from VPP to VCC

Repeat step 2 through 6 changing the address and data for the entire array or until the

end of the object file is reached (See Figure 31).

Programming CONF Byte

Verify Algorithm

After having apply the proper test mode, algorithm for programming CONF byte is simi-

lar to the previous programming algorithm with no address to present on the address

lines.

Code array verify must be done after each byte or block of bytes is programmed. In

either case, a complete verify of the programmed array will ensure reliable programming

of the T87C5112.

P 2.7 is used to enable data output.

To verify the T87C5112 code the following sequence must be exercised:

•

Step 1: Activate the combination of program and control signals.

Step 2: Input the valid address on the address lines.

Step 3: Read data on the data lines.

Repeat step 2 through 3 changing the address for the entire array verification (See

Figure 31).

The encryption array cannot be directly verified. Verification of the encryption array is

done by observing that the code array is well encrypted.

Verify CONF Byte

After having apply the proper test mode, algorithm for read/verify CONF byte is similar

to the previous verify algorithm with no address to present on the address lines.

Figure 31. Programming and Verification Signal’s Waveform

Programming Cycle

Read/Verify Cycle

Data Out

A0-A12

D0-D7

Data In

100µs

ALE/PROG

RST/VPP

12.75V

5V

0V

Control

signals

74

AT8xC5112

4191B–8051–04/03

AT8xC5112

Signature Bytes

Signature Bytes Content

The T87C5112 has four signature bytes in location 30h, 31h, 60h and 61h. To read

these bytes follow the procedure for EPROM verify but activate the control lines pro-

vided in xxxx for Read Signature Bytes. Table 60. shows the content of the signature

byte for theT87C5112.

Table 60. Signature Bytes Content

Location

30h

Contents

58h

Comment

Manufacturer Code: Atmel

Family Code: C51 X2

31h

57h

Product name: AT8xC5112 8K

ROM version

60h

61h

2Dh

ADh

EFh

Product name: AT8xC5112 8K

OTP version

Product revision number:

AT8xC5112 Rev.0

75

4191B–8051–04/03

Electrical Characteristics

Absolute Maximum Ratings

Note:

Stresses at or above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions above those indicated in the operational

sections of this specification is not implied. Exposure

to absolute maximum rating conditions may affect

device reliability.

C = commercial..................................................... 0°C to 70°C

I = industrial ....................................................... -40°C to 85°C

Storage Temperature.................................... -65°C to + 150°C

Voltage on V_CCto V_SS..........................................-0.5V to + 7V

Voltage on V_PPto V_SS........................................-0.5V to + 13V

Voltage on Any Pin to V_{SS.....................................}-0.5V to V_CC+ 0.5V

Power Dissipation.............................................................. 1 W

Power dissipation value is based on the maximum

allowable die temperature and the thermal resistance

of the package.

Power Consumption Measurement

Since the introduction of the first C51 devices, every manufacturer made operating I_CC

measurements under reset, which made sense for the designs were the CPU was run-

ning under reset. In our new devices, the CPU is no more active during reset, so the

power consumption is very low but is not really representative of what will happen in the

customer system. That’s why, while keeping measurements under Reset, we present a

new way to measure the operating I_CC

Using an internal test ROM, the following code is executed:

Label: SJMP Label (80 FE)

:

Ports 1, 3, 4 are disconnected, RST = V_CC, XTAL2 is not connected and XTAL1 is driven

by the clock.

This is much more representative of the real operating I_CC

.

76

AT8xC5112

4191B–8051–04/03

AT8xC5112

DC Parameters for

Standard Voltage

Table 61. DC Parameters in Standard Voltage

T_A= -40°C to +85°C; V_SS= 0 V; V_CC= 5V 10%

Symbol Parameter

Min

Typ

Max

Unit Test Conditions

V_IL

V_IH

Input Low Voltage

-0.5

0.2 V_CC- 0.1

V

0.2 V_CC

0.9

+

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

V

_CC+ 0.5

V_IH1

0.7 V_CC

V

0.3

0.45

1.0

V

I_OL= 100 µA

I_OL= 1.6 mA

I_OL= 3.5 mA

V_OL

Output Low Voltage, ports 1, 3, 4.⁽⁶⁾

I_OH= -10 µA

I_OH= -30 µA

I_OH= -60 µA

V

_CC- 0.3

_CC- 0.7

_CC- 1.5

V

Output High Voltage, ports 1, 3, 4.⁽⁶⁾

mode pseudo bi-directional

V_OH

V

_CC= 5V 10%

I_OH= -100 µA

_OH= -1.6 mA

I_OH= -3.2 mA

_CC= 5V 10%

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

Output High Voltage, ports 1, 3, 4.⁽⁶⁾

mode Push pull

I

V_OH2

V

Off impedance, ports 1, 3, 4.

RST Pullup Resistor

6

MΩ

kΩ

R_RST

I_IL

50

90 ⁽⁵⁾

200

-50

V_IN= 0.45V, port 1 & 3

Logical 0 Input Current ports 1, 3 and 4

µA

TBD

V_IN= 0.45V, port 4

I_LI

Input Leakage Current

10

µA 0.45V < V_IN< V_CC

µA V_IN= 2.0V

I_TL

Logical 1 to 0 Transition Current, ports 1, 3, 4

-650

Fc = 1 MHz

pF

C_IO

I_PD

I_CC

Capacitance of I/O Buffer

Power Down Current

10

50

T_A= 25°C

to be

confirmed

20 ⁽⁵⁾

µA 2.0V < V_CC_<5.5V ⁽³⁾

3+ 0.4 Freq

(MHz)

at 12MHz 5.8

to be

confirmed

under Power Supply Current Maximum values, X1 mode: ⁽⁷⁾

V

_CC= 5.5V (1)

mA

RESET

at 16MHz 7.4

3 + 0.6 Freq

(MHz)

at 12MHz 10.2

I_CC

to be

confirmed

Power Supply Current Maximum values, X1 mode: ⁽⁷⁾

operating

V

_CC= 5.5V⁽⁸⁾

at 16MHz 12.6

3 + 0.3 Freq

(MHz)

at 12MHz 3.9

I_CC

to be

confirmed

Power Supply Current Maximum values, X1 mode: ⁽⁷⁾

idle

V

_CC= 5.5V⁽²⁾

mA

at 16MHz 5.1

I_CC

V

_CC= 5.5V^(8),

to be

confirmed

Power Supply Current OSCB

operating

6

mA

V

at 12MHz

V_RET

Supply voltage during power down mode

2

77

4191B–8051–04/03

DC Parameters for Low Voltage

Table 62. DC Parameters in Standard Voltage

T_A= -40°C to +85°C; V_SS= 0V; V_CC= 2.7 to 5.5V

Symbol Parameter

Min

Typ

Max

Unit Test Conditions

V_IL

V_IH

Input Low Voltage

-0.5

0.2 V_CC- 0.1

V

0.2 V_CC

0.9

+

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

V

_CC+ 0.5

V

V_IH1

0.7 V_CC

V

0.3

0.45

1.0

V

I_OL= 100 µA

I_OL= 0.8mA

I_OL= 1.6mA

V_OL

Output Low Voltage, ports 1, 3, 4.⁽⁶⁾

V

_CC- 0.3

_CC- 0.7

_CC- 1.5

V

I_OH= -10 µA

I_OH= -30 µA

Output High Voltage, ports 1, 3, 4.⁽⁶⁾

mode pseudo bidirectionnel

V_OH

I_OH= -60 µA

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

I_OH= -100 µA

I_OH= -0.8 mA

I_OH= -1.6 mA

Output High Voltage, ports 1, 3, 4.⁽⁶⁾

mode Push-pull

V_OH2

Off impedance, ports 1, 3, 4.

RST Pull-up Resistor

6

MΩ

kΩ

R_RST

I_IL

50

90 ⁽⁵⁾

200

-50

V_IN= 0.45V, port 1 & 3

Logical 0 Input Current ports 1, 3 and 4

µA

TBD

V_IN= 0.45V, port 4

I_LI

Input Leakage Current

10

µA 0.45V < V_IN< V_CC

µA V_IN= 2.0V

I_TL

Logical 1 to 0 Transition Current, ports 1, 3, 4

-650

Fc = 1 MHz

pF

C_IO

I_PD

I_CC

Capacitance of I/O Buffer

Power Down Current

10

50

T_A= 25°C

to be

confirmed

20⁽⁵⁾

µA 2.0V < V_CC_<5.5V ⁽³⁾

1.5+ 0.2 Freq

(MHz)

at 12 MHz 3.4

to be

confirmed

under Power Supply Current Maximum values, X1 mode: ⁽⁷⁾

mA

V

_CC= 3.3V⁽¹⁾

RESET

at 16 MHz 4.2

1.5 + 0.3 Freq

(MHz)

at 12 MHz 5.1

I_CC

to be

confirmed

Power Supply Current Maximum values, X1 mode: ⁽⁷⁾

operating

V

_CC= 3.3V⁽⁸⁾

at 16 MHz 6.3

1.5 + 0.15 Freq

(MHz)

at 12 MHz 2

I_CC

to be

confirmed

Power Supply Current Maximum values, X1 mode: ⁽⁷⁾

idle

V

_CC= 3.3V⁽²⁾

at 16 MHz 2.6

I_CC

V

_CC= 3.3V^(8),

to be

confirmed

Power Supply Current OSCB

operating

3

mA

V

at 12 MHz

V_RET

Supply voltage during power down mode

2

Notes: 1. I_CCunder reset is measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 36.), V_IL=

V_SS+ 0.5V, V_IH= V_CC- 0.5V; XTAL2 N.C.; V_PP= RST = V_CC. I_CCwould be slightly higher if a crystal oscillator used

2. Idle I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5V, V_IH= V_CC

0.5V; XTAL2 N.C; Vpp = RST = V_SS(see Figure 34.).

-

3. Power Down I_CCis measured with all output pins disconnected; V_PP= V_SS; XTAL2 NC.; RST = V_SS(see Figure 35.).

4. Not Applicable.

78

AT8xC5112

4191B–8051–04/03

AT8xC5112

5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and

5V.

6. If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

7. For other values, please contact your sales office.

8. Operating I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 36.), V_IL

_SS+ 0.5V,

=

V

V_IH= V_CC- 0.5V; XTAL2 N.C.; RST/V_PP= V_CC;. The internal ROM runs the code 80 FE (label: SJMP label). I_CCwould be

slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst

cas

Figure 32. V_CCTest Condition, Under Reset

V_CC

I_CC

V_CC

RST

(NC)

CLOCK

SIGNAL

XTAL2

XTAL1

V_SS

All other pins are disconnected.

Figure 33. Operating I_CCTest Condition

V_CC

I_CC

V_CC

Reset = V_SSafter a high pulse

during at least 24 clock cycles

V_CC

RST

All other pins are disconnected.

XTAL2

XTAL1

V_SS

(NC)

CLOCK

SIGNAL

Figure 34. I_CCTest Condition, Idle Mode

V_CC

I_CC

Reset = V_SSafter a high pulse

during at least 24 clock cycles

V_CC

RST

XTAL2

(NC)

All other pins are disconnected.

CLOCK

XTAL1

V_SS

SIGNAL

79

4191B–8051–04/03

Figure 35. I_CCTest Condition, Power-down Mode

V_CC

I_CC

V_CC

Reset = V_SSafter a high pulse

during at least 24 clock cycles

V_CC

RST

All other pins are disconnected.

XTAL2

XTAL1

V_SS

Figure 36. Clock Signal Waveform for I_CCTests in Active and Idle Modes

V_CC-0.5V

0.7V_CC

0.2V_CC-0.1

0.45V

T_CHCL

T_CLCH

T_CLCH= T_CHCL= 5ns.

80

AT8xC5112

4191B–8051–04/03

AT8xC5112

DC Parameters for A/D

Converter

T_A= 0°C to +70°C; V_SS= 0 V; V_CC= 2.7V to 5.5V

T_A= -40°C to +85°C; V_SS= 0 V; V_CC= 2.7V to 5.5V

Table 63. DC Parameters

Symbol

Parameter

Min

Typ

Max

Unit

bit

Test Conditions

Resolution

10

AV_IN

R_REF

Analog input voltage

V_SS- 0.2

13

V

_CC+ 0.2

V

Resistance between Vref

and V_SS

18

60

1

24

KΩ

pF

Analog input

Capacitance

C_AI

During sampling

0.9 V_CC< V_REF

V_CC

<

Integral non-linearity

Differential non-linearity

Offset error

2

1

2

lsb

0.9 V_CC< V_REF

V_CC

0.5

0.9 V_CC< V_REF

V_CC

-2

For 10 bit

Input source impedance

1

KΩ

resolution at

maximum speed

81

4191B–8051–04/03

AC Parameters

Explanation of the AC

Symbols

Each timing symbol has 5 characters. The first character is always a “t” (that stands for

Time). The other characters, depending on their positions, stand for the name of a sig-

nal or the logical status of that signal. The following is a list of all the characters and

what they stand for.

Example:T_XHDV= Time from clock rising edge to input data valid.

T_A= -40°C to +85°C (industrial temperature range); V_SS= 0V; 2.7V < V_CC< 5.5V ; -L

range.

Table 64. gives the maximum applicable load capacitance for Port 1, 3 and 4. Timings

will be guaranteed if these capacitances are respected. Higher capacitance values can

be used, but timings will then be degraded.

Table 64. Load Capacitance Versus Speed Range, in pF

-L

Port 1, 3 & 4

80

Table 66, Table 69 and Table 72 give the description of each AC symbols.

Table 67, Table 70 and Table 73 give for each range the AC parameter.

Table 68, Table 71 and Table 74. give the frequency derating formula of the AC param-

eter. To calculate each AC symbols, take the x value corresponding to the speed grade

you need ( -L) and replace this value in the formula. Values of the frequency must be

limited to the corresponding speed grade:

Table 65. Max frequency for Derating Formula Regarding the Speed Grade

-L X1 mode,

-L X2 mode,

-L X1 mode,

-L X2 mode,

V_CC= 5V

V_CC= 3V

Freq (MHz)

T (ns)

40

33

40

20

25

30

25

50

Example:

T

_XHDVin X2 mode for a -L part at 20 MHz (T = 1/20^E6= 50 ns):

x = 133 (Table 74)

T = 50ns

T

_XHDV= 5T - x = 5 x 50 - 133 = 117 ns

82

AT8xC5112

4191B–8051–04/03

AT8xC5112

External Program Memory

Characteristic

Table 66. Symbol Description

Symbol

T

Parameter

Oscillator clock period

ALE pulse width

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_PXAV

T_AVIV

T_PLAZ

Address Valid to ALE

Address Hold After ALE

ALE to Valid Instruction In

ALE to PSEN

PSEN Pulse Width

PSEN to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction Float After PSEN

PSEN to Address Valid

Address to Valid Instruction In

PSEN Low to Address Float

Table 67. AC Parameters for Fix Clock

Speed

-L

Units

X2 Mode

Standard

Mode

X2 Mode

Standard

Mode

V_CC= 5V

V_CC= 3 V

V_CC= 5V

V_CC= 3V

Symbol

T

Min

33

25

4

Max

Min

Max

Min

50

35

5

Max

Min

Max

25

42

12

33

52

13

ns

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

4

5

45

25

78

50

65

30

98

55

9

17

60

10

50

18

75

35

0

12

53

10

20

95

10

80

10

18

122

10

83

4191B–8051–04/03

Table 68. AC Parameters for a Variable Clock: Derating Formula

-L

Standard

V_CC= 5V

V_CC= 3V

Symbol

T_LHLL

T_AVLL

T_LLAX

T_LLIV

Type

Min

Clock

2 T - x

T - x

4 T - x

T - x

3 T - x

x

X2 Clock

T - x

Units

ns

8

15

20

35

15

25

45

0

Min

0.5 T - x

2 T - x

0.5 T - x

1.5 T - x

x

13

22

8

ns

Min

ns

Max

Min

ns

T_LLPL

T_PLPH

T_PLIV

ns

Min

15

25

0

ns

Max

Min

ns

T_PXIX

T_PXIZ

T_AVIV

ns

Max

T - x

5 T - x

x

0.5 T - x

2.5 T - x

x

5

15

45

10

ns

30

10

ns

T_PLAZ

ns

84

AT8xC5112

4191B–8051–04/03

AT8xC5112

External Program Memory

Read Cycle

Figure 37. External Program Memory Read Cycle

12 T_CLCL

T_LHLL

T_LLIV

T_LLPL

ALE

PSEN

T_PLPH

T_PXAV

T_PXIZ

T_LLAX

T_AVLL

T_PLIV

TPLAZ

T_PXIX

INSTR IN

PORT 0

PORT 2

INSTR IN

A0-A7

INSTR IN

T_AVIV

ADDRESS A8-A15

ADDRESS

OR SFR-P2

ADDRESS A8-A15

External Data Memory

Characteristics

Table 69. Symbol Description

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Parameter

RD Pulse Width

WR Pulse Width

RD to Valid Data In

Data Hold after RD

Data Float after RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

Address to WR or RD

Data Valid to WR Transition

Data set-up to WR High

Data Hold after WR

RD Low to Address Float

RD or WR High to ALE high

T_WHLH

85

4191B–8051–04/03

Table 70. AC Parameters for a Fix Clock

-l

X2 Mode

Standard

Mode

X2 Mode

Standard

Mode

Speed

V_CC= 5v

V_CC= 3 V

V_CC= 5v

V_CC= 3v

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Min

85

Max

Min

135

Max

Min

125

Max

Min

175

Max

Units

ns

85

60

102

95

137

0

18

98

35

165

175

95

25

42

155

160

105

222

235

130

T_AVDV

T_LLWL

100

70

30

47

7

55

80

45

70

103

13

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

15

5

107

9

165

17

155

109

213

16

0

T_WHLH

7

27

15

35

5

45

13

53

86

AT8xC5112

4191B–8051–04/03

AT8xC5112

Table 71. AC Parameters for a Variable Clock: Derating Formula

-L

Standard

V_CC= 5V

V_CC= 3V

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Type

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Clock

6 T - x

5 T - x

x

X2 Clock

3 T - x

2.5 T - x

x

Units

ns

15

23

0

25

30

0

2 T - x

8 T - x

9 T - x

3 T - x

3 T + x

4 T - x

T - x

15

35

50

20

10

8

25

45

65

30

20

15

0

4T -x

T_AVDV

T_LLWL

4.5 T - x

1.5 T - x

1.5 T + x

2 T - x

0.5 T - x

3.5 T - x

0.5 T - x

x

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

7 T - x

T - x

x

0

T - x

0.5 T - x

0.5 T + x

10

20

T + x

External Data Memory Write

Cycle

Figure 38. External Data Memory Write Cycle

T_WHLH

ALE

PSEN

WR

T_LLWL

T_WLWH

T_QVWX

T_WHQX

T_LLAX

A0-A7

T_QVWH

DATA OUT

PORT 0

T_AVWL

ADDRESS

OR SFR-P2

PORT 2

ADDRESS A8-A15 OR SFR P2

87

4191B–8051–04/03

External Data Memory Read

Cycle

Figure 39. External Data Memory Read Cycle

T_WHLH

T_LLDV

ALE

PSEN

RD

T_LLWL

T_RLRH

T_RLDV

T_RHDZ

T_AVDV

T_LLAX

A0-A7

T_RHDX

DATA IN

PORT 0

PORT 2

T_RLAZ

T_AVWL

ADDRESS

OR SFR-P2

ADDRESS A8-A15 OR SFR P2

Serial Port Timing - Shift

Register Mode

Table 72. Symbol Description

Symbol

T_XLXL

Parameter

Serial port clock cycle time

T_QVHX

T_XHQX

T_XHDX

T_XHDV

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

Table 73. AC Parameters for a Fix Clock

-L (V_CC=5V)

-L (V_CC=3V)

X2 Mode

-L (V_CC=5V)

-L (V_CC=3V)

33 MHz

Standard Mode

40 MHz

Standard Mode

40 MHz

Speed

Symbol

T_XLXL

66 MHz Equiv.

Min

180

100

10

Max

Min

300

200

30

Max

Min

300

200

30

Max

Min

300

200

30

Max

Units

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

ns

0

ns

17

117

17

117

ns

88

AT8xC5112

4191B–8051–04/03

AT8xC5112

Table 74. AC Parameters for a Variable Clock: Derating Formula

Standard

Clock

-L

Symbol

T_XLXL

Type

Min

Max

X2 Clock

6 T

(V_CC= 5V) (V_CC= 3V)

Units

ns

12 T

10 T - x

2 T - x

x

T_QVHX

T_XHQX

T_XHDX

T_XHDV

5 T - x

T - x

50

20

0

50

20

0

ns

x

ns

10 T - x

5 T- x

133

ns

Shift Register Timing

Waveforms

Figure 40. Shift Register Timing Waveforms

0

1

2

3

4

5

6

7

8

INSTRUCTION

ALE

T_XLXL

CLOCK

T_XHQX

1

T_QVXH

0

2

3

4

5

6

7

OUTPUT DATA

T_XHDX

SET TI

T_XHDV

WRITE to SBUF

INPUT DATA

VALID

SET RI

CLEAR RI

89

4191B–8051–04/03

EPROM Programming and

Verification Characteristics

T_A= 21°C to 27°C; V_SS= 0V; V_CC= 5V 10% while programming.

V_CC= operating range while verifying.

Table 75. EEPROM Programming and Verification Characteristics

Symbol

V_PP

Parameter

Min

Max

13

75

6

Units

V

Programming Supply Voltage

Programming Supply Current

Oscillator Frequency

12.5

I_PP

mA

1/T_CLCL

T_AVGL

T_GHAX

T_DVGL

T_GHDX

T_EHSH

T_SHGL

T_GHSL

T_GLGH

T_AVQV

T_ELQV

T_EHQZ

4

MHz

Address Setup to PROG Low

Address Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

(Enable) High to V_PP

48 T_CLCL

10

V_PPSetup to PROG Low

µs

V_PPHold after PROG

10

PROG Width

90

110

Address to Valid Data

ENABLE Low to Data Valid

Data Float after ENABLE

48 T_CLCL

0

EPROM Programming and

Verification Waveforms

Figure 41. EPROM Programming and Verification Waveforms

PROGRAMMING

VERIFICATION

ADDRESS

T_AVQV

P1.0-P1.7

ADDRESS

P2.0-P2.5

P3.4-P3.5*

P

DATA OUT

P0

DATA IN

T_GHDX

T_GHAX

T_DVGL

T_AVGL

ALE/PROG

EA/V_PP

T_SHGL

T_GHSL

T_GLGH

V_PP

V_CC

T_EHSH

T_ELQV

T_EHQZ

CONTROL

SIGNALS

(ENABLE)

* 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5

90

AT8xC5112

4191B–8051–04/03

AT8xC5112

External Clock Drive

Characteristics (XTAL1)

Symbol

T_CLCL

Parameter

Oscillator Period

High Time

Low Time

Min

25

5

Max

Units

ns

T_CHCX

T_CLCX

T_CLCH

T_CHCL

ns

5

ns

Rise Time

5

ns

Fall Time

ns

T

_CHCX/T_CLCXCyclic ratio in X2 mode

40

60

%

External Clock Drive

Waveforms

Figure 42. External Clock Drive Waveforms

V

_CC-0.5V

0.7VCC

0.2VCC-0.1 V

TCHCL

0.45V

TCHCX

TCLCH

TCLCX

TCLCL

A/D Converter

Symbol

Parameter

Min

Typ

Max

Units

Clock periods (1 for

sampling, 10 for

conversion)

TConv

Conversion time

11

TSetup

Setup time

4

8

µs

Fconv_ck

Clock Conversion frequency

Sampling frequency

350⁽¹⁾

32

kHz

Note:

1. For 10 bits resolution

AC Testing Input/Output

Waveforms

Figure 43. AC Testing Input/Output Waveforms

V

_CC-0.5V

0.2VCC+0.9

0.2VCC-0.1

INPUT/OUTPUT

0.45V

AC inputs during testing are driven at V_CC- 0.5 for a logic “1” and 0.45V for a logic “0”.

Timing measurement are made at V_IHmin for a logic “1” and V_ILmax for a logic “0”.

91

4191B–8051–04/03

Float Waveforms

Figure 44. Float Waveforms

FLOAT

VOH-0.1 V

VOL+0.1 V

VLOAD

VLOAD+0.1 V

VLOAD-0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel

occurs. I_OL/I_OH

≥

20 mA.

Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2

divided by two.

92

AT8xC5112

4191B–8051–04/03

AT8xC5112

Figure 45. Clock Waveforms

STATE1

P1P2

STATE2

P1P2

STATE3

P1P2

STATE4

P1P2

STATE4

P1P2

STATE5

P1P2

STATE6

P1P2

STATE5

P1P2

INTERNAL

CLOCK

XTAL2

ALE

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

EXTERNAL PROGRAM MEMORY FETCH

PSEN

PCL OUT

DATA

P0

DATA

SAMPLED

FLOAT

DATA

SAMPLED

FLOAT

SAMPLED

FLOAT

INDICATES ADDRESS

TRANSITIONS

P2 (EXT)

READ CYCLE

RD

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

P0

P2

DPL OR Rt

FLOAT

INDICATES DPH OR P2 SFR TO PCH

TRANSITION

WRITE CYCLE

WR

PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

P0

DPL OR Rt OUT

DATA OUT

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

P2

INDICATES DPH OR P2 SFR TO PCH

TRANSITION

PORT OPERATION

OLD DATA

P0 PINS SAMPLED

NEW DATA

P0 PINS SAMPLED

MOV DEST P0

P1, P2, P3 PINS SAMPLED

RXD SAMPLED

P1, P2, P3 PINS SAMPLED

MOV DEST PORT (P1, P2, P3)

(INCLUDES INT0, INT1, TO, T1)

RXD SAMPLED

SERIAL PORT SHIFT CLOCK

TXD (MODE 0)

This diagram indicates when signals are clocked internally. The time it takes the signals

to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is

dependent on variables such as temperature and pin loading. Propagation also varies

from output to output and component. Typically though (T_A= 25°C fully loaded) RD and

WR propagation delays are approximately 50 ns. The other signals are typically 85 ns.

Propagation delays are incorporated in the AC specifications.

93

4191B–8051–04/03

Ordering Information Table 76. Maximum Clock Frequency

Code

-L

Unit

Standard Mode, oscillator frequency

Standard Mode, internal frequency

40

MHz

X2 Mode, oscillator frequency (V_CC= 5V)

33

66

MHz

X2 Mode, internal equivalent frequency (V_CC= 5V)

X2 Mode, oscillator frequency (V_CC= 3V)

20

40

X2 Mode, internal equivalent frequency (V_CC= 3V)

Table 77. Possible Order Entries

Temperature

Part Number

Memory Size

ROMless

8K ROM

8K OTP

Supply Voltage

2.7 - 5.5V

Range

Max Frequency

66 MHZ

Package

PLCC52

LQFP48

PLCC52

LQFP48

PLCC52

LQFP48

Packing

Stick

AT80C5112-S3SIL

AT80C5112-S3RIL

AT80C5112-RKTIL

AT80C5112-RKRIL

AT83C5112-S3SIL

AT83C5112-S3RIL

AT83C5112-RKTIL

AT83C5112-RKRIL

AT87C5112-S3SIL

AT87C5112-S3RIL

AT87C5112-RKTIL

AT87C5112-RKRIL

Industrial

Tape & Reel

Tray

Tape & Reel

Stick

Tape & Reel

Tray

Tape & Reel

Stick

8K OTP

Tape & Reel

Tray

8K OTP

Tape & Reel

94

AT8xC5112

4191B–8051–04/03

AT8xC5112

Packaging Information

PLCC52

95

4191B–8051–04/03

LQFP48

96

AT8xC5112

4191B–8051–04/03

Atmel Corporation

Atmel Operations

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Tel: 1(408) 441-0311

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Memory

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San Jose, CA 95131

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

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Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

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Tel: 1(719) 576-3300

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Japan

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e-mail

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Web Site

http://www.atmel.com

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

Corporation or its subsidiaries.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

4191B–8051–04/03

/xM


型号：	AT87C5112
厂家：	ATMEL
描述：	8-bit Microcontroller with A/D Converter 8位微控制器与A / D转换器转换器微控制器
文件：	总97页 (文件大小：1160K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT87C5112 [ATMEL]

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