AT85C5121-ICSIL_技术文档

Features

• 80C51 Core

– 12 or 6 Clocks per Instruction (X1 and X2 Modes)

– 256 Bytes Scratchpad RAM

– Dual Data Pointer

– Two 16-bit Timer/Counters: T0 and T1

• T83C5121 with 16 Kbytes Mask ROM

• T85C5121 with 16 Kbytes Code RAM

• T89C5121 with 16 Kbytes Code RAM and 16 Kbytes EEPROM

• On-chip Expanded RAM (XRAM): 256 Bytes

• Versatile Host Serial Interface

8-bit

Microcontroller

with Multi-

– Full-duplex Enhanced UART (EUART) with Dedicated Baud Rate Generator (BRG):

Most Standard Speeds up to 230K bits/s at 7.36 MHz

– Output Enable Input

– Multiple Logic Level Shifters Options (1.8V to V_CC

– Automatic Level Shifter Option

)

• Multi-protocol Smart Card Interface

– Certified with Dedicated Firmware According to ISO 7816, EMV2000, GIE-CB, GSM

11.12V and WHQL Standards

– Asynchronous Protocols T = 0 and T = 1 with Direct and Inverse Modes

– Baud Rate Generator Supporting All ISO7816 Speeds up to D = 32/F = 372

– Parity Error Detection and Indication

protocol Smart

Card Interface

– Automatic Character Repetition on Parity Errors

– Programmable Timeout Detection

T83C5121

T85C5121

T89C5121

AT83C5121

AT85C5121

AT89C5121

– Card Clock Stop High or Low for Card Power-down Mode

– Support Synchronous Card with C4 and C8 Programmable Outputs

– Card Detection and Automatic De-activation Sequence

– Step-up/down Converter with Programmable Voltage Output: 5V, 3V (± 8% at

60 mA) and 1.8V (±8% at 20 mA)

– Direct Connection to Smart Card Terminals:

Short Circuit Current Limitation

Logic Level Shifters

4 kV ESD Protection (MIL/STD 833 Class 3)

• Alternate Card Support with CLK, I/O and RST According to GSM 11.12V Standard

• 2x I/O Ports: 6 I/O Port1 and 8 I/O Port3

• 2x LED Outputs with Programmable Current Sources: 2, 4, or 10 mA

• Hardware Watchdog

• Reset Output Includes

– Hardware Watchdog Reset

– Power-on Reset (POR)

– Power-fail Detector (PFD)

• 4-level Priority Interrupt System with 7 Sources

• 7.36 to 16 MHz On-chip Oscillator with Clock Prescaler

• Absolute CPU Maximal Frequency: 16 MHz in X1 mode, 8MHz in X2 mode

• Idle and Power-down Modes

• Voltage Operation: 2.85V to 5.4V

• Low Power Consumption

– 8 mA Operating Current (at 5.4V and 3.68 MHz)

– 150 mA Maximum Current with Smart Card Power-on (at 16 MHz X1 Mode)

– 30 μA Maximum Power-down Current at 3.0V (without Smart Card)

– 100 μA Maximum Power-down Current at 5.4V (without Smart Card)

• Temperature Range

– Commercial: 0 to +70°C Operating Temperature

– Industrial: -40 to +85°C Operating Temperature

• Packages

– SSOP24

– QFN32

– PLCC52

Rev. 4164G–SCR–07/06

Description

T8xC5121 is a high performance CMOS ROM/CRAM derivative of the 80C51 CMOS

single chip 8-bit microcontrollers.

T8xC5121 retains the features of the Atmel 80C51 with extended ROM capacity (16

Kbytes), 512 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters

(T0/T1), a full duplex enhanced UART (EUART) with baud rate generator (BRG) and an

on-chip oscillator.

In addition, the T8xC5121 have, a Multi protocol Smart Card Interface, a dual data

pointer, 2 programmable LED current sources (2-4-10 mA) and a hardware Watchdog.

T89C5121 Flash RAM version and T85C5121 Code RAM version can be loaded by In-

System Programming (ISP) software residing in the on-chip ROM from a low-cost exter-

nal serial EEPROM or from R232 interface.

T8xC5121 have 2 software-selectable modes of reduced activity for further reduction in

power consumption.

Block Diagram

Figure 1. Block Diagram

(2) (2)

XTAL1

XTAL2

(3)

DC/DC

Xtal

Osc

CV_CC

RAM

256 x8

Converter

XRAM

256

ROM

EUART

BRG

Voltage

Reg.

CRAM

16K x8

(1)

x8

CC4

CC8

CIO

:1-16

Clock

Prescaler

Level

Shifters

C51

CORE

(1)

IB-bus

CRST

CCLK

(1)

CPU

SCIB

CPRES

(2)

X2

(4)

CIO1

Alternate

Card

(2)

CRST1

Direct

Drive

LED

8 I/Os

EA

PSEN

ALE

6 I/Os

Timer 0

Timer 1

INT

Ctrl

Watchdog

POR

PFD

Parallel I/O Ports

(2)

Output

CCLK1

(2) (2)

(2)

Notes: 1. Alternate function of Port 1

2. Alternate function of Port 3

3. Only for the Code RAM version

4. Only for PLCC52

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4164G–SCR–07/06

A/T8xC5121

Pin Description

Figure 2. 24-pin SSOP Pinout

CVSS

24

1

2

V_CC

EV_CC

LI

CV_CC

P1.5/CRST

P1.4/CCLK

23

22

3

4

DV_CC

VSS

P3.0/RxD

21

20

19

18

17

16

15

14

5

6

P1.3/CC4

P3.1/TxD

P3.3/INT1/OE

P3.4/T0

7

8

P1.2/CPRES

P1.1/CC8

P1.0/CIO

RST

P3.2/INT0

9

P3.5/CIO1/T1

10

11

XTAL2

P3.6/CCLK1/LED0

P3.7/CRST1/LED1

XTAL1 12

13

Figure 3. QFN32 Pinout

32 31 30 29 28 27 26 25

CVcc

Vss

1

2

3

4

5

6

7

8

24

P1.5/CRST

P1.4/CCLK

P1.3/CC4

P1.2/CPRES

P1.1/CC8

P1.0/CIO

RST

Vss

23

22

21

20

19

18

17

P3.0/RxD

P3.1/TxD

QFN32

P3.3/INT1/OE

P3.4/T0

P3.2/INT0

P3.5/CIO1/T1

9 10 11 12 13 14 15 16

3

4164G–SCR–07/06

Figure 4. PLCC52 Pinout

6

5

4

3

2

1

47

52 51 50 49 48

7

46

45

DV_CC

8

9

P1.4/CCLK

VSS

P3.0/RxD

P1.3/CC4

EA

44

10

43

42

41

40

11

12

13

14

PSEN

ALE

P3.1/TxD

P0.0/AD0

P2.7/A15

P2.6/A14

P0.1/AD1

P0.2/AD2

39

38

37

36

35

34

15

16

17

P0.3/AD3

P0.6/AD6

P2.5/A13

P1.2/CPRES

P3.3/INT1/OE

P3.4/T0

P1.1/CC8

P1.0/CIO

P2.4/A12

18

19

20

P3.2/INT0

P3.5/CIO1/T1

RST

32 33

21 22 23 24 25 26 27 28 29 30 31

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4164G–SCR–07/06

A/T8xC5121

Signals

All the T8xC5121 signals are detailed in Table 1.

The port structure is described in Section “Port Structure Description”.

Table 1. Ports Description

Internal

Power

Signal

Port

Name

Alternate

Supply

ESD

Type Description

Smart card interface function

P1.0

CIO

CV_CC

4 kV

I/O

I

Card I/O.

Input/Output function

P1.0 is a bi-directional I/O port .

Reset configuration

Input .

Smart card interface function

P1.1

CC8

CV_CC

4 kV

O

I

Card contact 8

Output function

P1.1 is a Push-pull port.

Reset configuration

Input

Smart card interface function

P1.2

CPRES

V_CC

4 kV

I

Card presence

Input/Output function

I/O

P1.2 is a bi-directional I/O port with internal pull-ups- ( External Pull-up

configuration can be selected).

Reset configuration

I

O

I

Input (high level due to internal pull-up)

Smart card interface function

P1.3

P1.4

P1.5

CC4

CCLK

CRST

CV_CC

4 kV

Card contact 4

Output function

P1.3 is a Push-pull port.

Reset configuration

Input (high level due to internal pull-up)

Smart card interface function

O

I/O

O

I/O

O

Card clock

Input/Output function

P1.4 is a a Push-pull port.

Reset configuration

Output at low level

Smart card interface function

Card reset

Input/Output function

P1.5 is a a Push-pull port.

Reset configuration

Output at low level

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4164G–SCR–07/06

Table 1. Ports Description (Continued)

Internal

Power

Signal

Name

Port

Alternate

Supply

ESD

Type Description

UART function

P3.0

RxD

EV_CC

I

Receive data input

Input/Output function

I/O

P3.0 is a bi-directional I/O port with internal pull-ups.

Reset configuration

I

Input (high level)

UART function

P3.1

TxD

EV_CC

O

Transmit data output

OE active at low or high level depending of PMSOEN bits in SIOCON Reg.

Input/Output function

I/O

Z

P3.1 is a bi-directional I/O port with internal pull-ups.

Reset configuration

High impedance due to PMOS switched OFF

External interrupt 0

INT0 input set IE0 in the TCON register. If bit IT0 in this register is set, bits IE0

are set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by a low

level on INT0.

P3.2

INT0

DV_CC

I

Input/Output function

I/O

P3.2 is a bi-directional I/O port with internal pull-ups.

Timer 0: Gate input

I

INT0 serves as external run control for Timer 0 when

selected in TCON register.

Reset configuration

Input (high level)

External Interrupt 1

INT1 input set OEIT in ISEL Register, IE1 in the TCON register.

P3.3

INT1

OE

EV_CC

I

If bit IT1 in this register is set, bits OEIT and IE1 are set by a falling edge on

INT1. If bit IT1 is cleared, bits OEIT and IE1 is set by a low level on INT1

UART function

Output enable. A low or high level (depending OELEV bit in

ISEL Register) on this pin disables the PMOS transistors of TxD

(P3.1) and T0 (P3.4). This function can be disabled by software

Input/Output function

I/O

P3.3 is a bi-directional I/O port with internal pull-ups.

Timer 1 function: Gate input

I

INT1 serves as external run control for Timer 1 when

selected in TCON register.

Reset configuration

Input (high level)

UART function

P3.4

T0

EV_CC

O

OE active at low or high level depending of PMSOEN

bits in SIOCON Reg.

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A/T8xC5121

Table 1. Ports Description (Continued)

Internal

Power

Signal

Name

Port

Alternate

Supply

ESD

Type Description

Input/Output function

P3.4 is a bi-directional I/O port with internal pull-ups.

I/O

I

Timer 0 function: External clock input

When Timer 0 operates as a counter, a falling edge on the T0 pin

increments the count.

Reset configuration

Z

High impedance due to PMOS switched OFF

Alternate card function

P3.5

CIO1

DV_CC

I/O

Card I/O

Input/Output function

P3.5 is a bi-directional I/O port with internal pull-ups.

Timer 1 function: External clock input

When Timer 1 operates as a counter, a falling edge on the T1 pin

increments the count.

I

Reset configuration

I

Input (high level due to internal pull-up)

Alternate card function

P3.6

CCLK1

LED0

DV_CC

O

Card clock

LED function

These pins can be directly connected to the cathode of standard

LED without external current limiting resistors. The typical current

of each output can be programmed by software to 2, 4 or 10 mA

(LEDCON register).

O

Input/Output function

I/O

I

P3.6 is a LED port.

Reset configuration

Input at high level

Alternate card function

P3.7

CRST1

DV_CC

O

Card reset

LED1

LED function

These pins can be directly connected to the cathode of standard

LED without external current limiting resistors. The typical current

of each output can be programmed by software to 2, 4 or 10 mA

(LEDCON register).

I/O

I

Input/Output function

P3.7 is a a LED port.

Reset configuration

Input at high level

7

4164G–SCR–07/06

Table 1. Ports Description (Continued)

Internal

Power

Signal

Name

Port

Alternate

Supply

ESD

Type Description

RST

V_CC

I/O

Reset input

Holding this pin low for 64 oscillator periods while the oscillator

is running resets the device. The Port pins are driven to their reset

conditions when a voltage lower than V_ILis applied, whether or

not the oscillator is running.

This pin has an internal pull-up resistor which allows the device to be reset by

connecting a capacitor between this pin and VSS.This capacitor is optional

thanks to the internal POR which output a Reset as long as Vcc has not

reached the POR threshold level

Asserting RST when the chip is in Idle mode or Power-down mode

returns the chip to normal operation.

The output is active for at least 12 oscillator periods when an internal

reset occurs.

XTAL1

XTAL2

V_CC

I

Input to the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected

to this pin.

If an external oscillator is used, its output is connected to this pin.

V_CC

O

Output of the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected

to this pin.

If an external oscillator is used, XTAL2 may be left unconnected.

V_CC

LI

PWR Supply voltage

V_CCis used to power the internal voltage regulators and internal I/O’s.

PWR DC/DC input

LI must be tied to V_CCthrough an external coil (typically 4, 7 μH) and provide

the current for the pump charge of the DC/DC converter.

CV_CC

DV_CC

PWR Card Supply voltage

CV_CCis the programmable voltage output for the Card interface.

It must be connected to an external decoupling capacitor.

PWR Digital Supply voltage

DV_CCis used to supply the digital core and internal I/Os. It is

internally connected to the output of a 3V regulator and must be connected to

an external decoupling capacitor.

EV_CC

V_CC

PWR Extra supply voltage

EV_CCis used to supply the level shifters of UART interface I/O

pins. It must be connected to an external decoupling capacitor.

This reference voltage is generated internally (automatically or not),

or it can be connected to an external voltage reference.

CVSS

VSS

GND DC/DC ground

CVSS is used to sink high shunt currents from the external coil.

GND Ground

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4164G–SCR–07/06

A/T8xC5121

Table 1. Ports Description (Continued)

Internal

Power

Signal

Name

Port

Alternate

Supply

ESD

Type Description

ONLY FOR PLCC52 version

P0[7:0] AD[7:0]

V_CC

I/O

Input/Output function Port 0

P0 is an 8-bit open-drain bi-directional I/O port. Port 0 pins that

have 1s written to them float and can be used as high impedance

inputs. To avoid any parasitic current consumption, Floating P0

inputs must be pulled to V_CCor V_SS

.

I/O

O

Address/Data low

Mutiplexed Address/Data LSB for external access

P2[7:0]

A[15:8]

V_CC

Input/Output function Port 2

P2 is an 8-bit open-drain bi-directional I/O port with internal pull-ups

Address high

Address Bus MSB for external access

P3.6

P3.7

ALE

WR

RD

DV_CC

V_CC

O

Write signal

Write signal asserted during external data memory write operation

I

Read signal

Read signal asserted during external data memory read operation

O

Address latch enable output

The falling edge of ALE strobes the address into external latch

PSEN

EA

PSEN

EA

V_CC

O

I

Program strobe enable

External access enable

This pin must be held low to force the device to fetch code from

external program memory starting at address 0000h. It is latched

during reset and cannot be dynamically changed during operation.

9

4164G–SCR–07/06

Port Structure

Description

The different ports structures are described as follows.

Quasi Bi-directional Output

Configuration

The default port output configuration for standard I/O ports is the quasi bi-directional out-

put that is common on the 80C51 and most of its derivatives. This output type can be

used as both an input and output without the need to reconfigure the port. This is possi-

ble because when the port outputs a logic high, it is weakly driven, allowing an external

device to pull the pin low. When the port outputs a logic low state, it is driven strongly

and able to sink a fairly large current. These features are somewhat similar to an open

drain output except that there are three pull-up transistors in the quasi bi-directional out-

put that serve different purposes. One of these pull-ups, called the weak pull-up, is

turned on whenever the port latch for the pin contains a logic 1. The weak pull-up

sources a very small current that will pull the pin high if it is left floating. A second pull-

up, called the medium pull-up, is turned on when the port latch for the pin contains a

logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary

source current for a quasi bi-directional pin that is outputting a 1. If a pin that has a logic

1 on it is pulled low by an external device, the medium pull-up turns off, and only the

weak pull-up remains on. In order to pull the pin low under these conditions, the external

device has to sink enough current to overpower the medium pull-up and take the voltage

on the port pin below its input threshold.

Figure 5. Quasi Bi-directional Output Configuration

P

2 CPU

CLOCK DELAY

P

Strong

Weak

Medium

PMOS

Port latch

Data

N

NMOS

Input

Data

Push-pull Output

Configuration

The Push-pull output configuration has the same pull-down structure as the quasi bi-

directional output modes, but provides a continuous strong pull-up when the port latch

contains a logic 1. The Push-pull mode may be used when more source current is

needed from a port output. The Push-pull port configuration is shown in Figure 5.

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4164G–SCR–07/06

A/T8xC5121

Figure 6. Push-pull Output Configuration

P

Strong

PMOS

Port latch

Data

N

NMOS

Input

Data

LED Output Configuration

The input only configuration is shown in Figure 7.

Figure 7. LED Source Current Configuration

P

2 CPU

CLOCK DELAY

PMOS

Medium

Strong

Weak

N

NMOS

LEDx.0

LED1CTRL

LED2CTRL

N

Port Latch

Data

N

LEDx.1

Input

Data

Note:

The port can be configured in quasi bi-directional mode and the level of current can be programmed by means of LEDCON0

and LEDCON1 registers before switching the led on by writing a logical 0 in Port latch.

11

4164G–SCR–07/06

SFR Mapping

The Special Function Registers (SFR) of the T8xC5121 belongs to the following

categories:

•

C51 core registers: ACC, B, DPH, DPL, PSW, SP

I/O port registers: P0, P1, P2, P3

Timer 0 registers: TCON, TH0, TH1, TMOD, TL0, TL1

Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON

Power and clock control registers: PCON, CKRL, CKCON0, CKCON1, DCCKPS

Interrupt system registers: IE0, IPL0, IPH0, IE1,IPL1, IPH1, ISEL

Watchdog Timer 0: WDTRST, WDTPRG

Others: AUXR, AUXR1, RCON

Smart Card Interface: SCSR, SCCON/SCETU0, SCISR/SCETU1, SCIER/SCIIR,

SCTBUF/SCRBUF, SCGT0/SCWT0, SCGT1/SCWT1, SCICR/SCWT2

•

Port configuration: SIOCON, LEDCON

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A/T8xC5121

Table 2. SFR Addresses and Reset Values

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

F8h

F0h

E8h

E0h

FFh

B

LEDCON

XXXX 0000

F7h

EFh

E7h

0000 0000

ACC

0000 0000

D8h

D0h

DFh

D7h

PSW

0000 0000

RCON

XXXX OXXX

C8h

C0h

B8h

CFh

C7h

IPL0

SADEN

ISEL

DCCKPS

BFh

B7h

XXX0 0000

0000 0000

0000 0100

XXXX XX11

B0h

0

1

0

1

SCWT0 *

0

1

0

1

SCWT1 *

0

1

0

1

SCWT2 *

P3

1111 1111

IE1

XXXX 0XXX

IPL1

XXXX 0XXX

IPH1

1000 0000

0010 0101

0000 0000

IPH0

XXX0 0000

XXXX 0XXX

SCGT0 *

0000 1100

SCGT1*

0000 0000

SCICR *

0000 0000

A8h

SCTBUF*

0000 0000

SCCON *

0X000

SCISR*

10X0 0000

SCIIR*

0X00 0000

AFh

IE0

0XX0 0000

SADDR

0000 0000

SCSR

XXX0 1000

CKCON1

XXXX 0XXX

SCRBUF

0000 000

SCETU0

0111 0100

SCETU1

0XXX

SCIER *

0X00 0000

A0h

98h

90h

88h

80h

P2

AUXR1

WDTRST

WDTPRG

A7h

9Fh

97h

8Fh

87h

1111 1111

XXX XXX0

XXXX XXXX

XXXX X0000

SCON

XXX0 0000

SBUF

BRL

0000 0000

BDRCON

XXXX XXXX

XXX0 0000

P1

SIOCON

00XX 0000

CKRL

XXXX 111X

XX11 1111

TCON

0000 0000

TMOD

0000 0000

TL0

0000 0000

TL1

0000 0000

TH0

TH1

0000 0000

AUXR

00XX XX00

CKCON0

X0X0 X000

0000 0000

P0

1111 1111

SP

0000 0111

DPL

0000 0000

DPH

0000 0000

20

PCON

00XX XX00

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

Reserved

SCRS Bit (SCSR.0)

(*)

0

1

SFR value

13

4164G–SCR–07/06

PowerMonitor

The PowerMonitor function supervises the evolution of the voltages feeding the micro-

controller, and if needed, suspends its activity when the detected value is out of

specification.

It is guaranteed to start up properly when T8xC5121 is powered up and prevents code

execution errors when the power supply becomes lower than the functional threshold.

This section describes the functions of the PowerMonitor.

Description

In order to start up and to properly maintain the microcontroller operation, V_DDhas to be

stabilized in the V_DDoperating range and the oscillator has to be stabilised with a nomi-

nal amplitude compatible with logic threshold.

This control is carried out during three phases which are the power-up, normal operation

and stop. It complies with the following requirements:

•

It guarantees an operational Reset when the microcontroller is powered

and a protection if the power supply goes out from the functional range of the

microcontroller.

Figure 8. PowerMonitor Block Diagram

DC to DC

CV_CC

External

V_DD

Power Supply

DV_CC

3V Regulator

Internal RESET

Power-up

Detector

Power-fail

Detector

PowerMonitor Diagram

The target of the PowerMonitor is to survey the power supply in order to detect any volt-

age drops which are not in the target specification. This PowerMonitor block checks two

kind of situations that occur:

•

During the power-up condition, when V_DDis reaching the product specification

During a steady-state condition, when V_DDis stable but disturbed by any

undesirable voltage drops.

Figure 9 shows some configurations that can be met by the PowerMonitor.

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4164G–SCR–07/06

A/T8xC5121

Figure 9. Power-Up and Steady-state Conditions Monitored

DV_CC

VPFDP

VPFDM

t_G

Steady-state Condition

Power-down

Power-up

t_rise

t_fall

Reset

V_CC

Such device when it is integrated in a microcontroller, forces the CPU in reset mode

when V_DDreaches a voltage condition which is out of the specification.

The thresholds and their functions are:

•

V_PFDP: the output voltage of the regulator has reached a minimum functional value

at the power-up. The circuit leaves the RESET mode.

•

V

_PFDM: the output voltage of the regulator has reached a low threshold functional

value for the microcontroller. An internal RESET is set.

Glitch filtering prevents the system from RESET when short duration glitches are carried

on V_DDpower supply.

The electrical parameters V_PFDP, V_PFDM, t_rise, t_fall, t_Gare specified in the DCparameters

section.

15

4164G–SCR–07/06

Power Monitoring

and Clock

Management

For applications where power consumption is a critical factor, three power modes are

provided:

•

Idle mode

Power-down mode

Clock Management (X2 feature and Clock Prescaler)

3V Regulator Modes (pulsed or not pulsed)

Idle Mode

An instruction that sets PCON.0 causes the last instruction to be executed before going

into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but

not to the interrupt, Timer 0, and Serial Port functions. The CPU status is preserved in

its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator

and all other registers maintain their data during Idle. The port pins hold the logical

states they had at the time Idle was activated. ALE and PSEN hold at logic high levels.

There are two ways to terminate the Idle. Activation of any enabled interrupt will cause

PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be ser-

viced, and following RETI the next instruction to be executed will be the one following

the instruction that put the device into idle.

The flag bit GF0 can be used to give an indication if an interrupt occurred during normal

operation or during an Idle. For example, an instruction that activates Idle can also set

one or both flag bits. When Idle is terminated by an interrupt, the interrupt service rou-

tine can examine the flag bits.

The other way of terminating the Idle mode is with a hardware reset. Since the clock

oscillator is still running, the hardware reset needs to be held active for only two

machine cycles (24 oscillator periods) to complete the reset.

Power-down Mode

Entering Power-down Mode

To save maximum power, a Power-down mode can be invoked by software (refer to

Table 3, PCON register).

In Power-down mode, the oscillator is stopped and the instruction that invoked Power-

down mode is the last instruction executed. The internal RAM and SFRs retain their

value until the Power-down mode is terminated. V_CCcan be lowered to save further

power. Either a hardware reset or an external interrupt can cause an exit from Power-

down. To properly terminate Power-down, the reset or external interrupt should not be

executed before V_CCis restored to its normal operating level and must be held active

long enough for the oscillator to restart and stabilize.

Only external interrupts INT0 and INT1 are useful to exit from Power-down. For that,

interrupt must be enabled and configured as level or edge sensitive interrupt input.

Holding the pin low restarts the oscillator but bringing the pin high completes the exit as

detailed in Figure 10. When both interrupts are enabled, the oscillator restarts as soon

as one of the two inputs is held low and Power-Down exit will be completed when the

first input will be released. In this case the higher priority interrupt service routine is

executed.

Once the interrupt is serviced, the next instruction to be executed after RETI will be the

one following the instruction that put it into Power-down mode.

Exit from Power-down Mode

Exiting from Power-down by external interrupt does not affect the SFRs and the internal

RAM content.

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The ports status under Power-down is the status which was valid before entering this

mode.

The INT1 interrupt is a multiplexed input (see Interrupt paragraph) with CPRES (Card

detection) and Rxd (UART Rx). So these three inputs can be used to exit from Power-

down mode. The configurations which must be set are detailed below:

•

Rxd input:

–

RXEN (ISEL.0) must be set

EX1 (IE0.2) must be set

A low level detected during more than 100 microseconds exit from Power-

down

•

CPRES input:

–

PRSEN (ISEL.1) must be set

EX1 (IEO.2) must be set

EA (IE0.7) must be set

In the INT1 interrupt vector, the CPLEV Bit (ISEL.7) must be inverted

and PRESIT Bit (ISEL.5) must be reset.

Figure 10. Power-down Exit Waveform

INT0

INT1

XTAL1

Active phase

Power-down phase

Active phase

Oscillator restart phase

Exiting from Power-down by reset redefines all the SFRs, exiting from Power-down by

external interrupt does no affect the SFRs.

Exiting from Power-down by either reset or external interrupt does not affect the internal

RAM content.

Note:

If idle mode is activated with Power-down mode (IDL and PD bits set), the exit sequence

is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and

idle mode is not entered.

SCI Control

Prior to entering Power-down mode, a de-activation of the Smart Card system must be

performed.

LED Control

Prior to entering Power-down mode, if the LED mode output is used, the medium pull-up

must be disconnected by setting the LEDPD bit in the PCON Register (PCON 3).

Low Power Mode

Only in Power-down mode, in order to reduce the power consumption, the user can

choose to select this low-power mode.

The activation reference is the following.

•

First select the Low-power mode by setting the LP bit in the AUXR Register (AUXR.

6)

•

The activation of Power-down can then be done.

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4164G–SCR–07/06

Reduced EMI Mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with

external program or data memory. Nevertheless, during internal code execution, ALE

signal is still generated.

Only in case of PLCC52 version, in order to reduce EMI, ALE signal can be disabled by

setting AO bit.

The AO bit is located in AUXR register at bit location 0 (See Table 4). As soon as AO is

set, ALE is no longer output but remains active during MOVX and MOVC instructions

and external fetches. During ALE disabling, ALE pin is weakly pulled high.

Power Modes Control

Registers

Table 3. PCON Register

PCON (S:87h)

Power Configuration Register

7

6

5

-

4

-

3

2

1

0

SMOD1

SMOD0

LEDPD

GF0

PD

IDL

Bit

Number Mnemonic Description

Double Baud Rate bit

7

6

SMOD1 Set to double the Baud Rate when Timer 1 is used and mode 1, 2 or 3 is selected in

SCON register.

SCON Select bit

When cleared, read/write accesses to SCON.7 are to SM0 bit and read/write

SMOD0 accesses to SCON.6 are to SM1 bit.

When set, read/write accesses to SCON.7 are to FE bit and read/write accesses to

SCON.6 are to OVR bit. SCON is Serial Port Control register.

5

4

Reserved

LED Control Power-Down Mode bits

3

2

LEDPD

GF0

When cleaned the I/O pull-up is the standard C51 pull-up control. When set the

medium pull-up is disconnected.

General-purpose flag 0

One use is to indicate wether an interrupt occurred during normal operation or

during Idle mode.

Power-down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-down mode.

If IDL and PD are both set, PD takes precedence.

1

0

PD

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

IDL

If IDL and PD are both set, PD takes precedence.

Reset Value = X0XX XX00b

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Table 4. AUXR Register

AUXR (S:8Eh)

Auxiliary Register

7

-

6

5

-

4

-

3

-

2

-

1

0

LP

EXTRAM

AO

Bit

Number

Mnemonic Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

Low Power mode selection

Clear to select standard mode

LP

Set to select low consumption mode

Reserved

5

4

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

EXTRAM select

(ONLY for PLCC52 version)

Clear to map XRAM datas in internal XRAM memory.

Set to map XRAM datas in external XRAM memory.

1

0

EXTRAM

AO

ALE Output bit

(ONLY for PLCC52 version)

Clear to restore ALE operation during internal fetches.

Set to disable ALE operation during internal fetches.

Reset Value = 00XX XX00b

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4164G–SCR–07/06

Table 5. IE0 Register

IE0

Interrupt Enable Register (A8h)

7

6

-

5

-

4

3

2

1

0

EA

ES

ET1

EX1

ET0

EX0

Bit

Mnemonic Description

Number

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

7

EA

If EA = 1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

Reserved

6

5

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Serial port Enable bit

4

3

2

1

0

ES

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

ET1

EX1

ET0

EX0

Clear to disable Timer 1 overflow interrupt.

Set to enable Timer 1 overflow interrupt.

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Clear to disable Timer 0 overflow interrupt.

Set to enable Timer 0 overflow interrupt.

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0XX0 0000b

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Table 6. ISEL Register

ISEL (S:BAh)

Interrupt Enable Register

7

6

-

5

4

3

2

1

0

CPLEV

RXIT

PRESIT

OELEV

OEEN

RXEN

PRESEN

Bit

Mnemonic Description

Number

Card presence detection level

This bit indicates which CPRES level will bring about an interrupt

Set this bit to indicate that Card Presence IT will appear if CPRES is at high

level.

7

CPLEV

Clear this bit to indicate that Card Presence IT will appear if CPRES is at low

level.

Reserved

6

5

-

The value read from this bit is indeterminate. Do not set this bit.

Card presence detection interrupt flag

Set by hardware

PRESIT

Must be cleared by software

Received data interrupt flag

Set by hardware

4

3

2

RXIT

OELEV

OEEN

Must be cleared by software

OE/INT1 signal active level

Set this bit to indicate that high level is active.

Clear this bit to indicate that low level is active.

OE/INT1 interrupt disable bit

Clear to disable INT1 interrupt

Set to enable INT1 interrupt

Card presence detection interrupt enable bit

1

0

PRESEN

RXEN

Clear to disable the card presence detection interrupt coming from SCIB.

Set to enable the card presence detection interrupt coming from SCIB.

Received data Interrupt enable bit

Clear to disable the RxD interrupt.

Set to enable the RxD interrupt

Reset Value = 0X00 0000b

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4164G–SCR–07/06

Clock Management

In order to optimize the power consumption and the execution time needed for a specific

task, an internal prescaler feature and a X2 feature have been implemented between

the oscillator and the CPU.

Functional Block

Diagram

Figure 11. Clock Generation Diagram

1

F_{CLK_CPU}

0

1

2(7-CKRL)

XTAL1

XTAL2

F_{CLK_Periph}

F_OSC

1

2

Osc.

0

1

F_OSC

x2

CKRL = 7

CKRL

2

X2

CKCON0

If CKRL<>7 then:

F

OSC

(x2) 2(7 CKRL)

1

F

= ----------------- ----------------------------------

CLK CPU

2

If CKRL = 7 then:

Fosc

F

= -------------

CLK CPU

x2

2

CKRL

Prescalor Factor

7

6

5

4

3

2

1

0

1

2

4

6

8

10

12

14

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A/T8xC5121

X2 Feature

The T8xC5121 core needs only 6 clock periods per machine cycle. This feature called

”X2” provides the following advantages:

•

Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

Saves power consumption while keeping same CPU power (oscillator power

saving).

•

Saves power consumption by dynamically dividing the operating frequency by 2 in

operating and idle modes.

Increases CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by software.

Description

The clock for the whole circuit and peripherals is first divided by two before being used

by the CPU core and the peripherals.

This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is

bypassed, the signals on XTAL1 must have a cyclic ratio from 40 to 60%.

As shown in Figure 11, X2 bit is validated on the rising edge of the XTAL1÷2 to avoid

glitches when switching from X2 to standard mode. Figure 12 shows the switching mode

waveforms.

Figure 12. Mode Switching Waveforms

XTAL1

XTAL1:2

X2 bit

F_OSC

CPU clock

STD Mode

X2 Mode

STD Mode

The X2 bit in the CKCON0 register (see Table 9) allows to switch (if CKRL=7) from 12

clock periods per instruction to 6 clock periods and vice versa.

The T0X2, T1X2, UartX2, and WdX2 bits in the CKCON0 register (see Table 9) and

SCX2 bit in the CKCON1 register (see Table 10) allow to switch from standard periph-

eral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock

periods per peripheral clock cycle). These bits are active only in X2 mode.

More information about the X2 mode can be found in the application note "How to Take

Advantage of the X2 Features in TS80C51 Microcontroller?".

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4164G–SCR–07/06

Clock Prescaler

Before supplying the CPU and the peripherals, the main clock is divided by a factor 2 to

30 to reduce the CPU power consumption. This factor is controlled with the CKRL

register.

Table 7. Examples of Factors

F_{CLK_CPU,}F_{CLK_Periph}

XTAL (MHz)

X2 CPU CKCON0

CKRL Value

07h

Prescaler Factor

(MHz)

16

0 (reset mode)

1

2

8

16

8

1 (X2 mode)

07h

1

0

1

07h

06h

4

06h

8

Clock Control Registers

Clock Prescaler Register

This register is used to reload the clock prescaler of the CPU and peripheral clock.

Table 8. CKRL Register

CKRL - Clock Reload Register (97h)

7

-

6

-

5

-

4

-

3

2

1

0

-

CKRL

Bit

Number

Mnemonic Description

Reserved

7 - 4

3 - 1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Clock Reload Register

Prescaler value

CKRL

XXXX 000Xb: CKRL=7 and Division factor equals 14

XXXX 110Xb: CKRL=6 and factor equals 2

XXXX 111Xb: CKRL=7 and division factor equals 1

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = XXXX 111Xb

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A/T8xC5121

Table 9. CKCON0 Register

CKCON0 - Clock Control Register (8Fh)

7

-

6

5

-

4

3

-

2

1

0

WDX2

SIX2

T1X2

T0X2

X2

Bit

Number

Mnemonic Description

7

6

5

4

3

2

-

WDX2

-

Reserved

Watchdog clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit has no effect)

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Reserved

Enhanced UART clock (Mode 0 and 2)

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

SIX2

-

Set to select 12 clock periods per peripheral clock cycle.

Reserved

Timer 1 clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit has no effect)

T1X2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

Timer 0 clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this

bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

1

0

T0X2

Set to select 12 clock periods per peripheral clock cycle

CPU clock

Clear to select 12 clock periods per machine cycle (Standard mode) for CPU

and all the peripherals.

X2

Set to select 6 clock periods per machine cycle (X2 mode) and to enable the

individual peripherals "X2" bits.

Reset Value = X0X0 X000b

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4164G–SCR–07/06

Table 10. CKCON1 Register

CKCON1 - Clock Control Register (AFh)

7

-

6

-

5

-

4

-

3

2

-

1

-

0

-

SCX2

Bit

Mnemonic Description

Number

7

6

5

4

-

Reserved

SCIB clock

Clear to select 6 clock periods per peripheral clock cycle.

3

SCX2

Set to select 12 clock periods per peripheral clock cycle.

2

1

0

-

Reserved

Reset Value = XXXX 0XXXb

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A/T8xC5121

DC/DC Clock

The DC/DC block needs a clock with a 50% duty cycle. The frequency must also respect

a value between 3.68 MHz and 4 MHz. The first requirement imposes a divider in the

clock path and the second constraint is solved with the use of a prescaler.

Figure 13. Functional Block Diagram

1

F_OSC

F_{CLK_DC/DC}

(2 to 5)

F_OSC

2 to 5

DCCKPS

Address BFh

Clock Control Register

This register is used to reload the clock prescaler of the DC/DC converter clock.

Table 11. DCCKPS Register

DCCKPS - DC/DC converter Reload Register (BFh)

7

-

6

-

5

-

4

-

3

-

2

-

1

0

DCCKPS

Bit

Number

Mnemonic Description

Reserved

7:2

-

Do not use write those bits

Clock Reload Register

Prescaler value

00b: Division factor equals 2

01b: division factor equals 3

10b: division factor equals 4

1:0

DCCKPS

11b: division factor equals 5 (reset value which minimize the consumption)

Reset Value = XXXX XX11b

Clock Prescaler

Before supplying the DC/DC block, the oscillator clock is divided by a factor 2 to 5 to

adapt the clock needed by the DC/DC converter. This factor is controlled with the

DCCKPS register.

The prescaler factor must be chosen to match the requirement range which is 4MHz.

Table 12. Examples of Factors

Prescaler

XTAL (MHz)

DCCKPS Value

Factor

DC/DC Converter CLK (MHz)

8

12

00h

01h

02h

03h

2

3

4

5

4

3.689

4

14.756

16

20

4

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4164G–SCR–07/06

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A/T8xC5121

Smart Card Interface Block (SCIB)

Introduction

The SCIB provides all signals to directly interface a smart card. Compliance with the

ISO7816, EMV’2000, GSM and WHQL standards has been certified.

Both synchronous (e.g. memory card) and asynchronous smart cards (e.g. micropro-

cessor card) are supported. The component supplies the different voltages requested by

the smart card. The power-off sequence is directly managed by the SCIB.

The card presence switch of the smart card connector is used to detect card insertion or

card removal. In case of card removal, the SCIB de-activates the smart card using the

de-activation sequence. An interrupt can be generated when a card is inserted or

removed.

Any malfunction is reported to the microcontroller (interrupt + control register).

The different operating modes are configured by internal registers.

Main Features

•

Support of ISO/IEC7816

Character mode

1 transmit buffer + 1 receive buffer

11 bits ETU counter

9 bits guard time counter

24 bits waiting time counter

Auto-character repetition on error signal detection in transmit mode

Auto-error signal generation on parity error detection in receive mode

Power-on and power-off sequence generation

Manual mode to directly drive the card I/O

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4164G–SCR–07/06

Block Diagram

The Smart Card Interface Block diagram is shown in Figure 14.

Figure 14. SCIB Block Diagram

Barrel shifter

IO (in)

IO (out)

Clk_iso

Clk_cpu

CLK

RST

Etu counter

I/O

mux

Scart

fsm

Guard time

C4 (out)

C8 (out)

Waiting time

CLK1

C4 (in)

C8 (in)

SCI Registers

Power on

Interrupt generator

INT

VCARD

Power off

fsm

Functional Description

The architecture of the Smart Card Interface Block is detailed below.

It allows the translation between 1 bit serial data and 8 bits parallel data.

Barrel Shifter

The barrel function is useful for character repetition since the character is still present in

the shifter at the end of the character transmission.

This shifter is able to shift the data in both directions and to invert the input or output

value in order to manage both direct and inverse ISO7816-3 convention.

Coupled with the barrel shifter there is a parity checker and generator.

There are 2 registers connected to this barrel shifter, one for the transmission and one

for the reception.

They act as buffers to relieve the CPU of timing constraints.

SCART FSM

(Smart Card Asynchronous Receiver Transmitter Finite State Machine)

This is the core of the design. Its purpose is to control the barrel shifter. To sequence

correctly the barrel shifter for a reception or a transmission, it uses the signals issued by

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A/T8xC5121

the different counters. One of the most important counters is the guard time counter that

gives time slots corresponding to the character frame.

It is enabled only in UART mode.

The transition from the receipt mode to the transmit mode is done automatically. Priority

is given to the transmission.

ETU Counter

The ETU (Elementary Timing Unit) counter controls the working frequency of the barrel

shifter, in fact, it generates the enable signal of the barrel shifter.

It is 11 bits wide and there is a special compensation mode activated with the most sig-

nificant bit that allows non integer ETU value with a working clock equal to the card

clock .

But the decimal value is limited to a half clock cycle. In fact the bit duration is not fixed. It

takes turns in n clock cycles and n-1 clock cycles. The character duration (10 bits) is

also equal to 10*(n+1/2) clock cycles.

This allows to reach the required precision of the character duration specified by the

ISO7816 standard.

example: F = 372 D = 32 = > ETU = 11.625 clock cycles.

ETU = (ETU[10-0] -0.5 * COMP)*f with ETU[10-0] = 12, COMP = 1 (bit 7 of SCETU1)

To achieve this clock rate we activated the compensation mode and we programmed

the ETU duration to 12 clock cycles.

The result will be a full character duration (10 bits) equal to 11.5 clock cycles.

Guard Time Counter

The minimum time between the leading edge of the start bit of a character and the lead-

ing edge of the start bit of the following character transmitted (Guard time) is controlled

by one counter.

It is 9 bits wide and is incremented at the ETU rate.

Figure 15. Guard Time Counter

ETU Counter

Guard Time Counter

Timeout

GT[8:0]

SCGT1

SCGT0

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4164G–SCR–07/06

Waiting Time Counter (WT)

The WT counter is a 24 bits down counter which can be loaded with the value contained

in the SCWT2, SCWT1, SCWT0 registers. Its main purpose is time out signal genera-

tion. It is 24 bits wide and is decremented at the ETU rate. The ETU counter acts as a

prescaler (See Figure 16).

When the WT counter timeout, an interrupt is generated and the SCIB function is

locked: reception and emission are disabled. It can be enabled by resetting the macro or

reloading the counter.

Figure 16. Waiting Time Counter

ETU Counter

WTEN

WT Counter

Load

Timeout

Write_SCWT2

WT[23:0]

SCWT1

UART

Start bit

SCWT0

SCWT2

The counter is loaded, if WTEN = 0, during the write of SCWT2 register.

This counter is available in both UART and manual modes. But the behaviour depends

on the selected mode.

In manual mode, the WTEN signal controls the start of the counter (rising edge) and the

stop of the counter (falling edge). After a time out of the counter, a falling edge on

WTEN, a reload of SCWT2 and a rising edge of WTEN are necessary to start again the

counter and to release the SCIB macro. The reload of SCWT2 transfers all SCWT0,

SCWT1 and SCWT2 registers to the WT counter.

In UART mode there is an automatic load on the start bit detection. This automatic load

is very useful for changing on-the-fly the Timeout value since there is a register to hold

the load value. This is the case, for example, when in T = 1 a launch is performed on the

BWT Timeout on the start bit of the last transmitted character. But on the receipt of the

first character an other time out value (CWT) must be used . For this, the new load value

of the waiting time counter must be loaded with CWT before the transmission of the last

character. The reload of SCWT[2-0] with the new value occurs with WTEN = 1.

After a time out of the counter in UART mode, the restart is done as in manual mode.

The maximum interval between the start leading edge of a character and the start lead-

ing edge of the next character is loaded in the SCWT2, SCWT1, SCWT0 registers.

In T = 1 mode, the CWT (character waiting time) or the BWT (block waiting time) are

loaded in the same registers.

The maximum time between two consecutive start bit is WT[23:0] * ETU.

When used to check BWT according to ISO 7816, WT can be set between 971 and

15728651.

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A/T8xC5121

Figure 17. T = 0 Mode

> GT

CHAR 2

CHAR 1

< WT

Figure 18. T = 1 Mode

Transmission

Reception

BLOC 2

BLOC 1

CHAR 2

CHAR n

CHAR n+1 CHAR n+2 CHAR n+3

CHAR 1

< CWT

< BWT

Power-on and Power-off FSM In this state, the machine applies the signals on the smart card in accordance with

ISO7816 standard.

To be able to power-on the SCIB, the card presence is mandatory.

Removal of the smart card will automatically start the power-off sequence as described

in Figure 19.

Figure 19. SCI Deactivation Sequence after a Card Extraction

V_CC

RST

CLK

IO

8 Clock Cycles

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4164G–SCR–07/06

Interrupt Generator

There are several sources of interruption but the SCIB macro-cell issues only one inter-

rupt signal: SCIB IT.

Figure 20. SCIB Interrupt Sources

Transmit buffer

copied to shift register

ESCTBI

Output current

out of range

CIccER

Output voltage

out of range

ECVccER

Timeout on WT

counter

SCIB IT

ESCWTI

ESCTI

Complete

transmission

Complete

reception

ESCRI

ESCPI

Parity error

detected

This signal is high level active. One of the sources is able to set up the interrupt signal

and this is the read of the Smart Card Interrupt register by the CPU that clears this

signal.

If during the read of the Smart Card Interrupt register an interrupt occurs, the set of the

corresponding bit into the Smart Card Interrupt register and the set of the interrupt signal

will be delayed after the read access.

Registers

There are fourteen registers to control the SCIB macro-cell. They will be described in

the Section “DC/DC Converter”.

Some of the register widths are greater than a byte. Despite the 8 bits access provided

by the BIU, the address mapping of this kind of register respects the following rule:

•

The Lowest significant byte register is implemented at the higher address.

This implementation makes access to these registers easier when using high level pro-

gramming language (C,C++).

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A/T8xC5121

Other Features

Clock

The Ck-ISO input must be in the range 1 - 5 MHz according to ISO7816.

The ISO Clock diagram and the configuration examples are shown in Figure 20.

Figure 21. Clock Diagram of the SCIB Block

FCLK_CPU

SCIB

FCLK_Periph

Clk_cpu

1

2

Clk_iso

F4_8MHz

0

SCX2

CKCON 1.3

Reset value = 1

Table 13. Examples of Settings for Clocks

FCLK Cpu

+ FCLK Periph

( MHz)

Clk_ iso

Xtal ( MHz)

X2 CKCON0

SCX2

(1 to 5 MHz)

4

0

2

0

1

2

4

8

1 (mode X2)

4

8

4

1

0

4

2.7648

3.6864

4

11.059

14.7456

16

5.5295

7.3728

8

20

10

5

Alternate Card

A second card named "Alternate card" can be controlled.

The Clock signal CCLK1 can be adapted to the XTAL frequency. Thanks to the clock

prescaler which can divide the frequency by 1, 2, 4 or 8. The bits ALTKPS0 and

ALTKPS1 in SCSR Register are used to set this factor.

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4164G–SCR–07/06

Figure 22. Alternate Card

CV_CC

CRST

CIO

CCLK

Main

card

CPRES

F_{CK_IDLE}

1, 2, 4 or 8

F_{CK_IDLE}

1

0

CCLK1

Alternate

card

PR3

SIM,SAM

CARD

P3.6

ALTKPS0,1

SCSR Reg.

SCCLK1

SCSR Reg.

Card Presence Input

The internal pull-up on Card Presence input can be disconnected in order to reduce the

consumption (CPRESRES, bit 3 in PMOD0).

In this case, an external resistor (typically 1 MΩ) must be externally tied to V_CC.

CPRES input can generate an interrupt (see Interrupt system section).

The detection level can be selected.

SCIB Reset

The SCICR register contains a reset bit. If set, this bit generates a reset of the SCI and

its registers. Table 15 shows the SCIB registers that are reseted and their reset values.

Table 14. Reset Values for SCI Registers

Register Name

SCICR

SCIB Reset Value (Binary)

0000 0000b

SCCON

0X00 0000b

SCISR

1000 0000b

SCIIR

0X00 0000b

SCIER

0X00 0000b

SCSR

XXX0 1000b

SCTBUF

0000 0000b

SCRBUF

0000 0000b

SCETU1, SCETU0

SCGT1, SCGT0

SCWT2, SCWT1, SCWT0

XXX X001b, 0111 0100b (372)

XXXX XXX0b, 0000 1100b (12)

0000 0000b, 0010 0101b, 1000 0000b (9600)

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A/T8xC5121

DC/DC Converter

The Smart Card supply voltage (CV_CC) is generated by the integrated DC/DC converter.

It is controlled by several registers:

•

The register described in Section “SCICR Register” controls the CVCC voltage with

bits CVcc0, CVcc1

The register described in Section “SCCON Register”, switches ON/OFF the DC/DC

converter with bit CARDV_CC

After the selection of the card voltage (CVcc[1:0]), the CARV_CCbit is used to switch

on the DC\DC converter. The CVccOK bit indicates that the card voltage is within

the voltage range.

•

It is mandatory to switch off the CV_CCbefore entering in power-down mode.

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4164G–SCR–07/06

Registers Description

Table 15. SCICR Register

SCICR (S:B6h, SCRS = 1)

Smart Card Interface Control Register

7

6

5

4

3

2

1

0

RESET

CARDDET

CVcc1

CVcc0

UART

WTEN

CREP

CONV

Bit Number Bit Mnemonic Description

Reset

7

RESET

Set this bit to reset the SCIB and its configuration

Card presence detector sense

Clear this bit to indicate the card presence detector is opened when no card

is inserted (CPRES is high).

6

CARDDET

Set this bit to indicate the card presence detector is closed when no card is

inserted (CPRES is low).

Card Voltage Selection:

CVcc[1]

CVcc[0]

CVcc

0V

0

1

0

1

0

1

5 - 4

CVcc[1:0]

1.8V

3V

5V

Card UART selection

Clear this bit to use the Card I/O bit to drive the Card I/O pin.

Set this bit to use the Smart Card UART to drive the Card I/O pin.

3

UART

Also controls the Wait Time Counter as described in Section “Waiting Time

Counter (WT)”

Wait time counter enable

Clear this bit to stop the counter and enable the load of the Wait Time

counter hold registers.

The hold registers are loaded with SCWT0, SCWT1 and SCWT2 values

when SCWT2 is written.

2

WTEN

Set this bit to start the Wait Time counter. The counters stop when it

reaches the timeout value.

If the UART bit is set, the Wait Time counter automatically reloads with the

hold registers whenever a start bit is sent or received.

Character repetition

Clear this bit to disable parity error detection and indication on the Card I/O

pin in receive mode and to disable character repetition in transmit mode.

Set this bit to enable parity error indication on the Card I/O pin in receive

mode and to set automatic character repetition when a parity error is

indicated in transmit mode. In receive mode, three times error indication is

performed and the parity error flag is set after four times parity error

detection. In transmit mode, up to three times character repetition is

allowed and the parity error flag is set after five times (reset configuration,

can be set at 4 using CREPSET bit in SCSR Register) consecutive parity

error indication.

1

CREP

ISO convention

Clear this bit to use the direct convention: b0 bit (LSB) is sent first, the

parity bit is added after b7 bit and a low level on the Card I/O pin represents

a “0”.

0

CONV

Set this bit to use the inverse convention: b7 bit (LSB) is sent first, the parity

bit is added after b0 bit and a low level on the Card I/O pin represents a “1”.

Reset Value = 0000 0000b

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A/T8xC5121

Table 16. SCCON Register

SCCON (S:ACh, SCRS = 0)

Smart Card Contacts Register

7

6

-

5

4

3

2

1

0

CLK

CARDC8

CARDC4

CARDIO

CARDCLK CARDRST CARDVCC

Bit Number Bit Mnemonic Description

Card Clock Selection

Clear this bit to use the CardClk bit (CARDCLK) to drive Card CLK pin.

Set this bit to use XTAL signal to drive the Card CLK pin.

7

CLK

Note: internal synchronization avoids any glitch on the CLK pin when

switching this bit.

Reserved

6

5

-

The value read from this bit is indeterminate. Do not change this bit or write 0.

Card C8

CARDC8

Clear this bit to drive a low level on the Card C8 pin.

Set this bit to set a high level on the Card C8 pin.

Card C4

4

3

CARDC4

CARDIO

Clear this bit to drive a low level on the Card C4 pin.

Set this bit to set a high level on the Card C4 pin.

Card I/O

When the UART bit is cleared in SCICR Register, the value of this bit is

driven to the Card I/O pin.

Then this pin can be used as a pseudo bi-directional I/O when this bit is set.

To be used as an input, this bit must contain a 1.

Card CLK

2

1

CARDCLK

CARDRST

When the CLK bit is cleared in SCCON Register, the value of this bit is driven

to the Card CLK pin.

Card RST

Clear this bit to drive a low level on the Card RST pin.

Set this bit to set a high level on the Card RST pin.

Read is not allowed if VCARDOK=0

Card VCC Control

Clear this bit to desactivate the Card interface and set its power-off. The other

bits of SCC register have no effect while this bit is cleared.

Set this bit to power-on the Card interface. The activation sequence shall be

handled by software.

0

CARDV_CC

Reset Value = 0X00 0000b

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4164G–SCR–07/06

Table 17. SCISR Register

SCISR (S:ADh, SCRS = 0)

Smart Card UART Interface Status Register

7

6

5

4

3

2

1

0

SCTBE

CARDIN

CIccOVF

CVccOK

SCWTO

SCTC

SCRC

SCPE

Bit

Number

Mnemonic Description

SCIB transmit buffer empty

This bit is set by hardware when the Transmit Buffer is copied to the transmit shift

register of the Smart Card UART.

7

SCTBE

It is cleared by hardware when SCTBUF is written to.

Card presence status

This bit is set when a card is detected (debouncing filter has to be done in

software).

It is cleared otherwise.

6

5

CARDIN

ICC overflow on card

CIccOVF This bit is set when the current on card is above the limit

It shall be cleared by the hardware .

Card voltage status

This bit is set when the output voltage is within the voltage range specified by

CVcc field.

It is cleared otherwise.

4

3

2

CVccOK

Smart card wait Timeout

This bit is set by hardware when the Smart card wait time counter times out.

It shall be cleared by the reload of the counter or by the reset of the SCIB.

SCWTO

SCTC

Smart card transmitted character

This bit is set by hardware when the Smart Card UART has transmitted a

character.

It shall be cleared by software after this register has been read.

Smart card received character

1

0

SCRC

SCPE

This bit is set by hardware when the Smart Card UART has received a character

It is cleared by hardware when SCBUF is read.

Smart card parity error

This bit is set at the same time as SCTI or SCRI if a parity error is detected.

It shall be cleared by software after this register has been read.

Reset Value = 1000 0000b

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A/T8xC5121

Table 18. SCIIR Register

SCIIR (S:AEh, SCRS = 0)

Smart Card UART Interrupt

Identification Register (read only)

7

6

-

5

4

3

2

1

0

SCTBI

CIccERR

CVccERR

SCWTI

SCTI

SCRI

SCPI

Bit

Number

Bit Mnemonic Description

SCIB transmit buffer interrupt

This bit is set by hardware when the Transmit Buffer is copied to the transmit

shift register of the Smart Card UART.

7

SCTBI

It is cleared by hardware when this register is read.

Reserved

6

5

-

The value read from this bit is indeterminate. Do not change this bit or write 0.

Card current status

This bit is set when the output current goes out of the current range.

It is cleared by hardware when this register is read.

CIccERR

Card voltage status

This bit is set when the output voltage goes out of the voltage range specified

by CVcc field.

It is cleared by hardware when this register is read.

4

3

2

CVccERR

SCWTI

SCTI

Smart card wait Timeout interrupt

This bit is set by hardware when the Smart Card Timer 0 times out.

It is cleared by hardware when this register is read.

Smart card transmit interrupt

This bit is set by hardware when the Smart Card UART completes a

character transmission.

It is cleared by hardware when this register is read.

Smart card receive interrupt

This bit is set by hardware when the Smart Card UART completes a

character reception.

It is cleared by hardware when this register is read.

1

0

SCRI

SCPI

Smart card parity error interrupt

This bit is set at the same time as SCTI or SCRI if a parity error is detected.

It is cleared by hardware when this register is read.

Reset Value = 0X00 0000b

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4164G–SCR–07/06

Table 19. SCIER Register

SCIER (S:AEh, SCRS = 1)

Smart Card UART Interrupt Enable Register

7

6

-

5

4

3

2

1

0

ESCTBI

CIccER

ECVccER

ESCWTI

ESCTI

ESCRI

ESCPI

Bit

Bit Number Mnemonic Description

Smart Card UART Transmit Buffer Empty Interrupt Enable

7

6

5

ESCTBI

-

Clear this bit to disable the Smart Card UART Transmit Buffer Empty interrupt.

Set this bit to enable the Smart Card UART Transmit Buffer Empty interrupt.

Reserved

The value read from this bit is indeterminate. Do not change this bit .

Card Current Error Interrupt Enable

Clear this bit to disable the Card Current Error interrupt.

Set this bit to enable the Card Current Error interrupt.

CIccER

Card Voltage Error Interrupt Enable

4

3

2

1

0

ECVccER Clear this bit to disable the Card Voltage Error interrupt.

Set this bit to enable the Card Voltage Error interrupt.

Smart Card Wait Timeout Interrupt Enable

ESCWTI

ESCTI

ESCRI

ESCPI

Clear this bit to disable the Smart Card Wait timeout interrupt.

Set this bit to enable the Smart Card Wait timeout interrupt.

Smart Card Transmit Interrupt Enable

Clear this bit to disable the Smart Card UART Transmit interrupt.

Set this bit to enable the Smart Card UART Transmit interrupt.

Smart Card Receive Interrupt Enable

Clear this bit to disable the Smart Card UART Receive interrupt.

Set this bit to enable the Smart Card UART Receive interrupt.

Smart Card Parity Error Interrupt Enable

Clear this bit to disable the Smart Card UART Parity Error interrupt.

Set this bit to enable the Smart Card UART Parity Error interrupt.

Reset Value = 0X00 0000b

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A/T8xC5121

Table 20. SCSR Register

SCSR (S:ABh) Smart Card Selection Register

7

-

6

-

5

-

4

3

2

1

0

CREPSEL ALTKPS1

ALTKPS0

SCCLK1

SCRS

Bit

Number

Mnemonic Description

7

6

5

-

Reserved

Character repetition selection

4

CREPSEL Clear this bit to select 5 times repetition before parity error indication

Set this bit to select 4 times repetition before parity error indication

Alternate Card Clock prescaler factor

00ALTKPS = 0: prescaler factor equals 1

ALTKPS1

3-2

01ALTKPS = 1: prescaler factor equals 2

ALTKPS0

10ALTKPS = 2: prescaler factor equals 4 (reset value)

11ALTKPS = 3: prescaler factor equals 8

Alternate card clock selection

1

0

SCCLK1 Set to select the prescaled clock (CCLK1)

Clear to select the standard port configuration (P3.6)

Smart card register selection

SCRS

The SCRS bit selects which set of the SCIB registers is accessed.

Reset Value = XXX0 1000b

Table 21. SCTBUF Register

SCTBUF (S:AA, write-only, SCRS = 0) Smart Card Transmit Buffer Register

7

6

5

4

3

2

1

0

Bit Number Bit Mnemonic Description

Can store a new byte to be transmitted on the I/O pin when SCTBE is set.

Bit ordering on the I/O pin depends on the Convention (see SCICR

Register).

–

Reset Value = 0000 0000b

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4164G–SCR–07/06

Table 22. SCRBUF Register

SCRBUF (S:AA read-only, SCRS = 1)

Smart Card Receive Buffer Register

7

6

5

4

3

2

1

0

–

Bit

Number

Bit

Mnemonic Description

Provides the byte received from the I/O pin when SCRI is set.

Bit ordering on the I/O pin depends on the Convention (see SCICR Register).

–

Reset Value = 0000 0000b

Table 23. SCETU1 Register

SCETU1 (S:ADh, SCRS = 1)

Smart Card ETU Register 1

7

6

5

4

3

2

1

0

COMP

–

ETU10

ETU9

ETU8

Bit

Number

Mnemonic Description

Compensation

Clear this bit when no time compensation is needed (i.e. when the ETU to Card

CLK period ratio is close to an integer with an error less than 1/4 of Card CLK

period).

7

COMP

Set this bit otherwise and reduce the ETU period by 1 Card CLK cycle for even

bits.

Reserved

6-3

2-0

–

The value read from these bits is indeterminate. Do not change these bits .

ETU MSB

ETU[10:8]

Used together with the ETU LSB (see SCETU0 Register).

Reset Value = 0XXX X001b

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A/T8xC5121

Table 24. SCETU0 Register

SCETU0 (S:ACh, SCRS = 1)

Smart Card ETU Register 0

7

6

5

4

3

2

1

0

ETU7

ETU6

ETU5

ETU4

ETU3

ETU2

ETU1

ETU0

Bit

Number

Mnemonic Description

ETU LSB

The Elementary Time Unit is (ETU[10:0] - 0.5*COMP)/f, where f is the Card CLK

ETU[7:0] frequency.

7-0

According to ISO7816, ETU[10:0] can be set between 11 and 2047.

The default reset value of ETU[10:0] is 372 (F = 372, D = 1).

Reset Value = 0111 0100b

Table 25. SCGT1 Register

SCGT1 (S:B5h, SCRS = 1)

Smart Card Transmit Guard Time Register 1

7

6

5

4

3

2

1

0

–

GT8

Bit

Number

Mnemonic Description

Reserved

7-1

0

–

The value read from these bits is indeterminate. Do not change these bits .

Transmit Guard Time MSB

Used together with the Transmit Guard Time LSB (see SCGT0 Register).

GT8

Reset Value = XXXX XXX0b

Table 26. SCGT0 Register

SCGT0 (S:B4h, SCRS = 1)

Smart Card Transmit Guard Time Register 0

7

6

5

4

3

2

1

0

GT7

GT6

GT5

GT4

GT3

GT2

GT1

GT0

Bit

Number

Mnemonic Description

Transmit Guard Time LSB

The minimum time between two consecutive start bits in transmit mode is

GT[8:0] * ETU.

7-0

GT[7:0]

According to ISO 7816, GT can be set between 11 and 266 (11 to 254+12 ETU).

Reset Value = 0000 1100b

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4164G–SCR–07/06

Table 27. SCWT2 Register

SCWT2 (S:B6h, SCRS = 0)

Smart Card Character/Block Wait Time Register 2

7

6

5

4

3

2

1

0

WT23

WT22

WT21

WT20

WT19

WT18

WT17

WT16

Bit

Number

Mnemonic Description

Wait Time Byte 2

Used together with WT[15:0] (see SCWT0 Register).

7-0

WT[23:16]

Reset Value = 0000 0000b

Table 28. SCWT1 Register

SCWT1 (S:B5h, SCRS = 0) Smart Card Character/Block Wait Time Register 1

7

6

5

4

3

2

1

0

WT15

WT14

WT13

WT12

WT11

WT10

WT9

WT8

Bit

Number

Mnemonic Description

Wait Time Byte 1

Used together with WT[23:16] and WT[7:0] (see SCWT0 Register).

7-0

WT[15:8]

Reset Value = 0010 0101b

Table 29. SCWT0 Register

SCWT0 (S:B4h, SCRS = 0)

Smart Card Character/Block Wait Time Register 0

7

6

5

4

3

2

1

0

WT7

WT6

WT5

WT4

WT3

WT2

WT1

WT0

Bit

Number

Mnemonic Description

Wait Time Byte 0

WT[23:0] is the reload value of the Wait Time counter WTC.

The WTC is a general-purpose Timer 0. It is using the ETU clock and is

controlled by the WTEN bit (see Section “Waiting Time Counter (WT)”).

7-0

WT[7:0]

When UART bit of SCICR Register is set, the WTC is automatically reloaded at

each start bit of the UART. It is used to check the maximum time between to

consecutive start bits.

Reset Value = 1000 0000b

46

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A/T8xC5121

Interrupt System

Figure 23. Interrupt Control System

INT0

The T8xC5121 has a total of 6 interrupt vectors: four external interrupts (INT0, INT1/OE,

CPRES, RxD), two Timer 0 interrupts (Timer 0s 0 and 1), serial port interrupt and Smart

Card Interface interrupt. These interrupts are shown in Figure 23.

IPH0, IPL0

High Priority

0

Interrupt

IE0

EX0

ET0

1

TCON Reg. IT0

TF0

RXEN

RXIT

Rxd

OEEN

Interrupt

Polling

1

0

INT1/OE

0

IE1

EX1

1

Sequence

OELEV

TCON reg.

IT1

PRESIT

The selection bits

except IT1 (TCON)

are in ISEL Reg.

PRESEN

0

1

CPRES

TF1

CPLEV

ET1

ES

RI

TI

IPH1, IPL1

SCI

ESCI

Low Priority

Interrupt

Individual

Enable

Global

Enable

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register (see Figure 32). This register also contains a

global disable bit, which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one of four priority levels

by setting or clearing a bit in the Interrupt Priority register (see Figure 36) and in the

Interrupt Priority High register (see Figure 38). Table 30 shows the bit values and priority

levels associated with each combination.

Table 30. Priority Level Bit Values

IPH.x

IP.x

0

Interrupt Level Priority

0

1

0 (Lowest)

1

2

0

1

3 (Highest)

47

4164G–SCR–07/06

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of higher priority level is serviced. If interrupt requests of the same priority level

are received simultaneously, an internal polling sequence determines which request is

serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

Table 31. Interrupt Vector Addresses

Interrupt Source

Vector Address

0003h

IE0

TF0

000Bh

IE1 & RxIt & PrIt

TF1

0013h

001Bh

RI & TI

SCI

0023h

0053h

INT1 Interrupt Vector

The INT1 interrupt is multiplexed with the three following inputs:

•

INT1/OE: Standard 8051 interrupt input

Rxd: Received data on UART

CPRES: Insertion or removall of the main card

The setting configurations for each input is detailed below:

INT1/OE Input

This interrupt input is active under the following conditions:

•

It must be enabled thanks to OEEN Bit (ISEL Register)

It can be active on a level or falling edge: thanks to IT1 Bit (TCON Register)

If level triggering selection is set, the active level 0 or 1 can be selected with OELEV

Bit (ISEL Register)

The Bit IE1 (TCON Register) is set by hardware when external interrupt detected. It is

cleared when interrupt is processed.

Rxd Input

A second vector interrupt input is the reception of a character. UART Rx input can gen-

erate an interrupt if enabled with Bit RXEN (ISEL.0). The global enable bits EX1 and EA

must also be set.

Then, the Bit RXIT (ISEL Register) is set by hardware when a low level is detected on

P3.0/RXD input.

CPRES Input

The third input is the detection of a level change on CPRES input (P1.2). This input can

generate an interrupt if enabled with PRESEN (ISEL.1), EX1 (IE0.2) and EA (IE0.7) Bits.

This detection is done according to the level selected with Bit CPLEV (ISEL.7).

Then the Bit PRESIT (ISEL.5) is set by hardware when the triggering conditions are

met. This Bit must be cleared by software.

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A/T8xC5121

Table 32. IE0 Register

7

6

-

5

-

4

3

2

1

0

EA

ES

ET1

EX1

ET0

EX0

Bit

Mnemonic Description

Number

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

7

EA

If EA = 1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

Reserved

6

5

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Serial port Enable bit

4

3

2

1

0

ES

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

Clear to disable Timer 1 overflow interrupt.

Set to enable Timer 1 overflow interrupt.

ET1

EX1

ET0

EX0

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Clear to disable Timer 0 overflow interrupt.

Set to enable Timer 0 overflow interrupt.

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0XX0 0000b

Bit addressable

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4164G–SCR–07/06

Table 33. IE1 Register

7

-

6

-

5

-

4

-

3

2

-

1

-

0

-

ESCI

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SCI Interrupt Enable

3

ESCI

Clear to disable the SCI interrupt.

Set to enable the SCI interrupt.

Reserved

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = XXXX 0XXXb

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Table 34. TCON Register

TCON (S:88h)

Timer 0/Counter Control Register

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit

Number

Mnemonic Description

Timer 1 Overflow flag

Cleared by the hardware when processor vectors to interrupt routine.

Set by the hardware on Timer 0/Counter overflow when Timer 1 register

overflows.

7

6

5

TF1

TR1

TF0

Timer 1 Run Control bit

Clear to turn off Timer 0/Counter 1.

Set to turn on Timer 0/Counter 1.

Timer 0 Overflow flag

Cleared by the hardware when processor vectors to interrupt routine.

Set by the hardware on Timer 0/Counter overflow when Timer 0 register

overflows.

Timer 0 Run Control bit

4

3

2

1

0

TR0

IE1

IT1

IE0

IT0

Clear to turn off Timer 0/Counter 0.

Set to turn on Timer 0/Counter 0.

Interrupt 1 Edge flag

Cleared by the hardware when interrupt is processed if edge-triggered (see IT1).

Set by the hardware when external interrupt is detected on the INT1 pin.

Interrupt 1 Type Control bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1).

Set to select falling edge active (edge triggered) for external interrupt 1.

Interrupt 0 Edge flag

Cleared by the hardware when interrupt is processed if edge-triggered (see IT0).

Set by the hardware when external interrupt is detected on INT0 pin.

Interrupt 0 Type Control bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0).

Set to select falling edge active (edge triggered) for external interrupt 0.

Reset Value = 0000 0000b

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Table 35. ISEL Register

7

6

5

4

3

2

1

0

CPLEV

OEIT

PRESIT

RXIT

OELEV

OEEN

PRESEN

RXEN

Bit

Number

Mnemonic Description

Card presence detection level

This bit indicates which CPRES level will bring about an interrupt

Set this bit to indicate that Card Presence IT will appear if CPRES is at high

level.

7

CPLEV

Clear this bit to indicate that Card Presence IT will appear if CPRES is at low

level.

Reserved

6

5

-

The value read from this bit is indeterminate. Do not set this bit.

Card presence detection interrupt flag

Set by hardware

PRESIT

Must be cleared by software

Received data interrupt flag

Set by hardware

4

3

2

1

RXIT

OELEV

OEEN

Must be cleared by software

OE/INT1 signal active level

Set this bit to indicate that high level is active.

Clear this bit to indicate that low level is active.

OE/INT1 Interrupt Disable bit

Clear to disable INT1 interrupt

Set to enable INT1 interrupt

Card presence detection Interrupt Enable bit

PRESEN Clear to disable the card presence detection interrupt coming from SCIB.

Set to enable the card presence detection interrupt coming from SCIB.

Received data Interrupt Enable bit

Clear to disable the RxD interrupt.

Set to enable the RxD interrupt (a minimal bit width of 0.1 ms is required to

0

RXEN

wake up from Power-Down).

Reset Value = 0000 0100b

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Table 36. IPL0 Register

7

-

6

-

5

-

4

3

2

1

0

PSL

PT1L

PX1L

PT0L

PX0L

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Serial port Priority bit

Refer to PSH for priority level.

PSL

PT1L

PX1L

PT0L

PX0L

Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

Reset Value = XXX0 0000b

Bit addressable

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Table 37. IPL1 Register

7

-

6

-

5

-

4

-

3

2

-

1

-

0

-

PSCIL

Bit

Number

Mnemonic

Description

Reserved

7

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

PSCIL

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = XXXX 0XXXb

Bit addressable

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Table 38. IPH0 Register

7

-

6

-

5

-

4

3

2

1

0

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Number

Mnemonic

Description

Reserved

7

6

5

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Serial port Priority High bit

PSH PS Priority Level

0

1

0

1

0

1

Lowest

4

3

2

1

0

PSH

PT1H

PX1H

PT0H

PX0H

Highest

Timer 1 overflow interrupt Priority High bit

PT1H PT1 Priority Level

0

1

0

1

0

1

Lowest

Highest

External interrupt 1 Priority High bit

PX1H PX1 Priority Level

0

1

0

1

0

1

Lowest

Highest

Timer 0 overflow interrupt Priority High bit

PT0H PT0 Priority Level

0

1

0

1

0

1

Lowest

Highest

External interrupt 0 Priority High bit

PX0 HPX0 Priority Level

0

1

0

1

0

1

Lowest

Highest

Reset Value = XXX0 0000b

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4164G–SCR–07/06

Table 39. IPH1 Register

7

-

6

-

5

-

4

-

3

2

-

1

-

0

-

PSCIH

Bit

Number

Mnemonic

Description

Reserved

7

6

5

4

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SCI Interrupt Priority level most significant bit

PSCIH PSCIL Priority level

0

1

0

1

0

1

Lowest

3

PSCIH

Highest priority

Reserved

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = XXXX 0XXXb

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LED Ports

Configuration

The current source of the LED Ports can be adjusted to 3 different values: 2, 4 or 10 mA.

The LED output is an alternate function of P3.6 an P3.7 and cannot be used while the

alternate card function is used.

The control register LEDCON is detailed below.

Registers Definition

Table 40. LEDCON Register

7

-

6

-

5

-

4

-

3

2

1

0

LED1[1]

LED1[0]

LED0[1]

LED0[0]

Bit

Number

Mnemonic Description

Reserved

7 - 4

-

The value read from this bit is indeterminate. Do not set this bit.

Port LED1 configuration:

LED1[1] LED1[0] Configuration

0

1

0

1

0

1

Standard C51 port

3 - 2

LED1[1,0]

LED0[1,0]

2 mA current source when P3.7 is at Low Level

4 mA current source when P3.7 is at Low Level

10 mA current source when P3.7 is at Low Level

Port LED0 configuration:

LED0[1] LED0[0] Configuration

0

1

0

1

0

1

standard C51 port

1 - 0

2 mA current source when P3.6 is at Low Level

4 mA current source when P3.6 is at Low Level

10 mA current source when P3.6 is at Low Level

Reset Value = XXXX 0000b

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Dual Data Pointer

T8xC5121 contains a Dual Data Pointer accelerating data memory block moves. The

Standard 80C52 Data Pointer is a 16-bit value that is used to address off-chip data RAM

or peripherals. In T8xC5121, the standard 16-bit data pointer is called DPTR and

located at SFR location 82H and 83H. The second Data Pointer named DPTR1 is

located at the same address than the previous one. The DPTR select bit (DPS / bit0)

chooses the active pointer and it is located into the AUXR1 register. It should be ser-

viced in those sections of code that will periodically be executed within the time required

to prevent a WDT reset.

The user switches between data pointers by toggling the LSB of the AUXR1. The incre-

ment (INC) is a solution for this. All DPTR-related instructions use the currently selected

DPTR for any activity. Therefore only one instruction is required to switch from a source

to a destination address. Using the Dual Data Pointer saves code and resources when

moves of blocks need to be accomplished.

The second Data Pointer can be used to address the on-chip XRAM.

Table 41. DPL Register

DPL - Low Byte of DPTR1 (82h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Reset value = 0000 0000b

Table 42. DPH Register

DPH - High Byte of DPTR1 (83h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Reset value = 0000 0000b

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Table 43. AUXR1 Register

AUXR1 - Dual Pointer Selection Register (A2h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

DPS

Bit

Number

Mnemonic

Description

Reserved

7

6

5

4

3

2

1

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Data pointer 1

Clear to select DPTR0 as Data Pointer.

0

DPS

Set to select DPTR1 as Data Pointer.

Reset value = XXXX XXX0b

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Memory Management

Program Memory

All the T8xC5121 versions implement 16 Kbytes of ROM memory, 256 Bytes RAM and

256 Bytes XRAM.

The hardware configuration byte and the split of internal memory spaces depends on

the product and is detailed below.

ROM Configuration Byte

Table 44. ROM Configuration Byte Hardware Register

7

-

6

5

-

4

-

3

-

2

-

1

-

0

BLJRB

Bit

Number

Mnemonic Description

7

Reserved

Bootloader Jump RAM Bit

6

BLJRB

Set to configure User Code in ROM

Clear to configure Bootlader in ROM

5-0

Reserved

The BLJRB depends of the product version:

•

1: ROM mask version

0: EEPROM/CRAM versions

This bit defines if, after reset, either the Customer ROM program or the Bootloader pro-

gram is executed (for In System programming).

Program ROM Lock Bits

The program Lock system protects the on-chip program against software piracy.

The T8xC5121 products are delivered with the highest protection level.

Table 45. T8xC5121 Products Protection Level

Program Lock Bits

Protection Description

Security

Level

LB1

LB2

SSOP24 version:

Read function is disabled.But checksum control is still enabled

PLCC52 version:

MOVC instruction executed from external program memory are disabled

from fetching code bytes from internal memory,

3

P

EA is sampled and latched on reset.

But checksum control is still enabled.

External execution is possible.

P = Programmed

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Memory Mapping

In the products versions, the following internal spaces are defined:

•

RAM

XRAM

CRAM: 16 KBytes Program RAM Memory

ROM

The specific accesses from/to these memories are:

•

XRAM: if the bit RPS in RCON (described below) is reset, MOVX instructions

address the XRAM space.

•

CRAM: if the bit RPS in RCON is set, MOVX instructions address the CRAM

space.

Table 46. RCON Register

7

6

-

5

-

4

3

2

1

0

RPS

Bit

Number

Mnemonic Description

Reserved

7-4

3

-

The value read from this bit is indeterminate. Do not set this bit.

CRAM space map bit

Set to map the CRAM space during MOVX instructions

RPS

-

Clear to map the Data space during MOVX. This bit has priority over the EXTRAM

bit.

Reserved

2-0

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = XXXX 0XXXb

T89C5121 Flash ROM Version Three memory blocks are implemented

•

An internal serial EEPROM can be loaded from external with the application

program.

•

The ROM memory contains the Bootloader program. The entry point is located at

address F800h. The lower 14K Bytes between address C000h and F7FFh is, also,

used for the Bootloader program.

•

The CRAM is the application program memory. This memory is mapped in the

External RAM space. The bit RPS in RCON (SFR address 0D1h) is set to map the

CRAM space during MOVX instructions

For first programming or an update, the program can be downloaded in the internal

EEPROM (and in the CRAM) from an external device:

•

Either an external EEPROM if detected

or from a host through RS232 serial communication.

For this purpose, an In-System Programming (ISP) is supplied in a Bootloader. This

Bootloader is program masked in ROM space.

The Hardware Byte BLJRB value is 0.

As described on page 7, after Reset, the Bootloader program is executed.

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4164G–SCR–07/06

If a serial communication device (as described above: TWI or RS232) is detected, the

program download its content in the internal EEPROM and in CRAM.

Else, the program is internally downloaded from the internal EEPROM into the program

CRAM memory (16 Kbytes)

Then, in the two cases, the Bootloader executes a Long Jump at address 0000h which

initializes the Program counter at the lower address (0000h) of the executable CRAM.

Figure 24. CRAM with ROM and EEPROM Memory Mappings

FFFFh

F800h

entry point

Bootloader

C000h

3FFFh

0000h

16 Kbytes

256 bytes

XRAM

256 bytes

RAM

ROM

CRAM

T85C121 Code RAM Version

Two memory blocks are implemented:

•

The ROM memory contains the Bootloader program.

The CRAM is the Application program memory.

After Reset, the program is downloaded, as described in last paragraph, from either an

external EEPROM or from an host connected on RS232 serial link into the program

CRAM memory of 16 Kbytes. Then the Program Counter is set at address 0000h of the

CRAM space and the program is executed.

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Figure 25. CRAM and ROM Mappings

FFFFh

F800h

entry point

Bootloader

C000h

3FFFh

0000h

16K bytes

256 bytes

RAM

256 bytes

XRAM

ROM

CRAM

T83C5121 with Mask ROM

Version

In this version, the customer program is masked in 16 Kbytes ROM.

•

The customer program is masked in ROM during the final production phase. The

ROM size will be determined at mask generation process depending of the program

size.

In-System Programming The In-System Programming (ISP) mode is only implemented in the following product

versions:

•

EEPROM version

CRAM version

(The ROM product version is masked with the customer program and does not need

ISP mode)

The ISP is used to download an Application program in the device and to run it.

The communication protocols which are implemented are: UART and TWI.

Hardware Interface

The hardware in relation with the two communication protocols is detailed below:

•

TWI protocol

Serial protocol

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Figure 26. Hardware in Relation with the Two Communication Protocols

DV_CCor Ext. V_CC(3V)

Optional

DV_CC

Thanks to internal pull-ups

TWI

SDA

P3.2/INT0

P3.7/CRST1

SCL

V_CC

EEPROM external

AT24C128

Address = 01h

(A0 = 1,A1 = 0)

DVss Wp = 1

TWI

P2.1

P2.0

SDA

SCL

DV_CCor Ext.V_CC(3V)

Internal EEPROM

AT24C128

Address = 00h

A0 = A1 = 0

wp = 0

BOOTLOADER

V_CC

V_SS

(default values if not tied)

UART

ISP Software Tool

EEPROM Mapping

The 16K Bytes EEPROM mapping is the following:

0000h

3FFD

Reserved address

3FFE

3FFF

The three last bytes are reserved respectively:

•

Software Security Byte: address 3FFDh

CRC Bytes: address 3FFEh and 3FFFh

The use of these bytes is described in the following paragraphs.

Therefore, the User Program must be mapped from 0000h to 3FFCh address.

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Bootloader Functional

Diagram

As described in Section “ROM Configuration Byte”, page 60a ROM bit BLJRB (Boot

Loader Jump ROM Bit) defines which product version is. The Bootloader program is

mapped in ROM space from address C000h up to FFFFh and the entry point is located

at address F800h.

Figure 27. Bootloader Flowchart

RESET

Versions:

RAM+ROM

RAM,ROM,EEPROM

versions:

RAM+ROM (Pre-prod: Application Program)

ROM (Prod)

BLJRB = 1

ROM Bit

Bootloader

Execution

ROM

F800h

SSB & P3.7 test

TWI

ext.bypassed?

bypassed?

ROM

ROM program

0000h

Execution

ACK?

E2PROM at 01

Program is downloaded from

External EEPROM into internal

EEPROM and CRAM

and executed.

External E2PROM (at 01) is detected

SSB & P3.6 test

UART bypassed

bypassed?

U Character

received on UART

An ISP Software can be used from

a PC to program the part.

Atmel FLIP software is available

Serial communication is detected thanks to

Autobaud feature (Table52)

Time Elapsed

Program is downloaded from

internal EEPROM in CRAM and

executed

ACK?

E2PROM at 00

Internal E2PROM (at 00) is detected

RD port = Error code =

22h

Error: No TWI or serial device detected

A serial code is sent on RD pin (P3.7)

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In-System Programming

Timings

The download from the internal EEPROM to CRAM is executed after 4 seconds when

operating at 12 MHz frequency.

Protection Mechanisms

Transfer Checks

In order to verify that the transfers are free of errors, a CRC check is implemented dur-

ing the download of the program in CRAM.

This test is done at the end of the 16K space programming.

As detailed in the next algorithms:

•

in ISP mode, if CRC test pass, a character Y is returned before the CRLF

characters else a character Z is retuned.

•

in download mode, a serial data AA is sent on P3.7 port and CRAM is not executed.

For this purpose, the user program must include in the two last upper bytes (address

3FFEh and 3FFFh) the CRC of the previous bytes (calculated from the address 0000h

to 3FFFDh).

The following frames are examples including the CRC in the two last upper bytes:

Data Bytes

HSB LSB

2 Bytes CRC

Address: 3FFE,3FFF

•

FF 03 C0 21 04 00 00 08 07 02 08 02 2D DB (CRC = 2DDBh)

FF 03 80 21 02 04 00 0A 03 06 C0 A8 70 01 E3 3D (CRC = E33Dh)

FF 03 C0 21 02 01 00 10 02 06 00 00 00 00 05 06 00 00 76 55 49 AC (CRC =

49ACh)

The CRC algorithm is the following :

***************************************************************************************************

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A/T8xC5121

***************************************************************************************************

Table 47. Synthesis of Transfer Protection Mechanisms

Source

MCU

Target

CRAM

MCU

Check

CRC computed during CRAM Write operation: if error an error code is applied

on P3.7 and Code execution by LJMP000 is not done.

Intern. EEP

MCU

This Read operation is secured by the Write sequence described above

Same protection as in first row above because CRAM is written in sequence

after each page programming of EEP

Intern. EEP

MCU

Ext. EEP

Same as above as data are transferred to EEP INT and then to CRAM

Notes: 1. The transfer of SSB Byte is also secured by CRC as the CRC is computed on all the

16K data.

2. If a Bad transfer has occurred in the Internal EEPROM (CRC is bad), as the CRC

check is finally done at the end of CRAM programming, application program will NOT

be executed after any Reset.

Read/Write Protection

Lock Byte

In order to protect the content of the internal EEPROM, a Software Security Byte (SSB)

defines two security levels:

•

level 0: SSB = 0xFF: Write and Read are allowed

level 1: SSB = 0xFE: Write is disabled

level 2: SSB = 0xFC: Write and Read are disabled

This SSB Byte is located at address 3FFDh.

When the level 2 is set, the command to set level 1 is disabled. The security levels can

only be increased.

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4164G–SCR–07/06

The only mean to remove the security level 2 is to send a Full Chip Erase command.

SSB

Data Bytes

Address

3FFD

Table 48. Synthesis of Security Mechanisms

Source

Function Protection

Internal

EEPROM

The first protection level of the SSB Byte IN the internal EEPROM protects

against ISP Write command

Write

Read

Write

Read

Internal

EEPROM

The second protection level of the SSB Byte IN the internal EEPROM protects

against ISP Read commands

The first protection level of the SSB Byte IN the internal EEPROM protects

against ISP Write command in CRAM

CRAM

The second protection level of the SSB Byte IN the CRAM protects against ISP

Read commands

Configuration Bits

The Bootloader tests that TWI components are connected as slave components on the

TWI external bus and later in the algorithm if characters are received on the UART input.

This default configuration can be changed, after a first programming, in order:

–

to disable new programming in download mode from external serial

EEPROM to disable ISP programming using UART and

–

to avoid any conflict with the target hardware on external TWI bus or UART.

This can be configured with the two higher bits of the SSB Byte detailed in the previous

paragraph.

The bit 7 is used to bypass (if 0) the External TWI Acknowledge test.

The bit 6 is used to bypass (if 0) the UART receipt test.

These two bypass modes can be disabled if a level 0 is applied on, respectively, P3.5

and P3.6 pins. This allows to force and use ISP even if the device has been configured

as programmed device.

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Table 49. Valid Software Security Byte Values

SSB Values

Functions

FE

No bypass and level1 security

No bypass and level2 security

UART bypass and security levels

FC

BF,BE,BC

7F,7E,7C

3F,3E,3C

External TWI bypass and security levels

UART and Ext. TWI bypass

UART Protocol

Overview

The serial protocol used is described below.

Physical Layer

The UART is used to transmit information with the following configuration:

•

Character: 8-bit data

Parity: none

Stop: 1 bit

Flow control: none

Baudrate: autobaud is performed by the bootloader to compute the baudrate

chosen by the host.

Datas and Limits

As described in Section “Transfer Checks”, the downloaded program include the CRC

values in the last two upper bytes of the 16K bytes space.

An update of a part of the 16K program cannot be done because the CRC value would

have to be updated with a value which depends of the actual value of the rest of the

program.

So the Program function of the PC Software Tool include the individual program com-

mands (with 64 data bytes) from address 0000h to address 3FFFh.

Frame Description

The Serial Protocol is based on the Intel Hex-type records.

Intel Hex records consist of ASCII characters used to represent hexadecimal values and

are summarized below:

Table 50. Intel Hex Type Frame

Record Mark ‘:’

Reclen

Load Offset

Record Type

Data or Info

Checksum

1-byte

1-byte = 40h

2-byte

1-byte

64-byte

1-byte

•

Record Mark:

Record Mark is the start of frame. This field must contain’:’.

Reclen:

Reclen specifies that the number of bytes of information or data that follow

the Record Type field of the record.

Load Offset:

Load Offset specifies the 16-bit starting load offset of the data bytes,

therefore this field is used only for Program Data Record (see Table 51).

–

•

–

69

4164G–SCR–07/06

•

Record Type:

Record Type specifies the command type. This field is used to interpret the

–

remaining information within the frame. The encoding for all the current

record types are described in Table 51.

•

Data/Info:

Data/Info is a 64 bytes length field. It consists of 64 bytes encoded as pairs

of hexadecimal digits. The meaning of data depends on the Record Type.

Checksum:

The two’s complement of the 8-bit bytes that result from converting each pair

–

of ASCII hexadecimal digits to one byte of binary, and including the Reclen

field to and including the last byte of the Data/Info field. Therefore, the sum

of all the ASCII pairs in a record after converting to binary, from the Reclen

field to and including the Checksum field, is zero.

Notes: 1. A data byte is represented by two ASCII characters.

2. When the field Load Offset is not used, it should be coded as 2 bytes (00h 00h).

Command Description

Table 51. Frame Description

Command

Command Name

Program Data

End Of File

data[0]

data[1]

Command Effect

Program 64 Data Bytes

End of File

00h

01h

-

Full Chip Erase

07h

05h

03h

Program SSB level1

Program SSB level2

00h

01h

03h

Write Function

LJMP(data[2],data[3])

(LJMP0000h)

Data[0:1] = start address

Data [2:3] = end address

Display Data

Data[4] = 00h -> Display

data

04h

Display Function

Data[4] = 01h -> Blank

check

Data[4] = 03h -> Display

CRAM

07h

0Fh

00h

Read SSB

05h

06h

Read Function

Read Bootloader Version

Direct Load of Baud Rate

HSB

LSB

Not implemented

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Autobaud

The ISP feature allows a wide range of baud rates in the user application. It is also

adaptable to a wide range of oscillator frequencies. This is accomplished by measuring

the bit-time of a single bit in a received character. This information is then used to pro-

gram the baud rate in terms of timer counts based on the oscillator frequency. The ISP

feature requires that an initial character (an uppercase U) be sent to the T8xC5121 to

establish the baud rate. Table show the autobaud capability.

Table 52. Autobaud Performances

Frequency (MHz)

Baudrate (kHz)

6.176

8

OK

-

11.0592

OK

12

OK

-

14.3

OK

Ok

OK

-

14.7456

OK

16

-

9600

OK

19200

OK

-

38400

-

OK

57600

-

OK

115200

-

OK

-

Protection Mechanisms

Transfer Checks

Table 53. Synthesis of the Communication Protection Mechanisms

Source

Target

Check

Checksum included in commands is tested with calculated checksum: if

bad, X echo returned to ISP

UART ISP

MCU

CRC computed during CRAM Write operation: if error an error code is

applied on P3.7. Error code’Z’ is returned to ISP.

MCU

CRAM

Same protection as above because CRAM is written in sequence after

each page programming of EEP

Intern. EEP

Notes: 1. The transfer of SSB Byte is also secured by CRC as the CRC is computed on all the

16K data.

2. If a bad transfer has occurred in the Internal EEPROM (CRC is bad), as the CRC

check is finally done at the end of CRAM programming, application program will NOT

be executed after any Reset.

Security

Table 54. Synthesis of the Security Mechanisms

Source

Target

Case

Protection

SSB level 2 must be set (done, if

selected, at ISP Programming or Ext

EEP Download)

UART ISP

Intern. EEP

Read access

SSB level 2 IN CRAM must be set (SSB

is downloaded from Int EEP after Reset)

UART ISP

CRAM

Read access

SSB level 1 must be set (done, if

selected, at ISP Programming or Ext

EEP Download)

Partial Programming

which would not fit

with old CRC

Intern. EEP

Then the EEP must be, first, erased

before reprogramming.

Programming is done on all the memory

space

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Source

Target

Case

Protection

SSB level 1 must be set (done, if

selected, at ISP Programming or Ext

EEP Donwload)

UART ISP

Intern. EEP

Programming

SSB level 1 IN Int EEP protects as, first,

the Int EEP is programmed before

CRAM

UART ISP

CRAM

Program access

SSB in EEP and

CRAM

UART ISP

level 2 to level 1

level 1 to level 0

Protected by Bootloader

SSB in EEP and

CRAM

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Timers/Counters

Introduction

The T8xC5121 implements two general-purpose, 16-bit Timer 0s/Counters. Although

they are identified as Timer 0, Timer 1, you can independently configure each to operate

in a variety of modes as a Timer 0 or as an event Counter. When operating as a Timer 0,

a Timer 0/Counter runs for a programmed length of time, then issues an interrupt

request. When operating as a Counter, a Timer 0/Counter counts negative transitions

on an external pin. After a preset number of counts, the Counter issues an interrupt

request.

The Timer 0 registers and associated control registers are implemented as addressable

Special Function Registers (SFRs). Two of the SFRs provide programmable control of

the Timer 0s as follows:

•

Timer 0/Counter mode control register (TMOD) and Timer 0/Counter control register

(TCON) control respectively Timer 0 and Timer 1.

The various operating modes of each Timer 0/Counter are described below.

Timer 0/Counter

Operations

For example, a basic operation is Timer 0 registers THx and TLx (x = 0, 1) connected in

cascade to form a 16-bit Timer 0. Setting the run control bit (TRx) in the TCON register

(see Figure 55) turns the Timer 0 on by allowing the selected input to increment TLx.

When TLx overflows it increments THx and when THx overflows it sets the Timer 0 over-

flow flag (TFx) in the TCON register. Setting the TRx does not clear the THx and TLx

Timer 0 registers. Timer 0 registers can be accessed to obtain the current count or to

enter preset values. They can be read at any time but the TRx bit must be cleared to

preset their values, otherwise the behavior of the Timer 0/Counter is unpredictable.

The C/Tx# control bit selects Timer 0 operation or Counter operation by selecting the

divided-down system clock or the external pin Tx as the source for the counted signal.

The TRx bit must be cleared when changing the operating mode, otherwise the behavior

of the Timer 0/Counter is unpredictable.

For Timer 0 operation (C/Tx# = 0), the Timer 0 register counts the divided-down system

clock. The Timer 0 register incremented once every peripheral cycle.

Exceptions are the Timer 0 2 Baud Rate and Clock-Out modes in which the Timer 0 reg-

ister is incremented by the system clock divided by two.

For Counter operation (C/Tx# = 1), the Timer 0 register counts the negative transitions

on the Tx external input pin. The external input is sampled during every S5P2 state. The

Programmer’s Guide describes the notation for the states in a peripheral cycle. When

the sample is high in one cycle and low in the next one, the Counter is incremented. The

new count value appears in the register during the next S3P1 state after the transition

has been detected. Since it takes 12 states (24 oscillator periods) to recognize a nega-

tive transition, the maximum count rate is 1/24 of the oscillator frequency. There are no

restrictions on the duty cycle of the external input signal, but to ensure that a given level

is sampled at least once before it changes, it should be held for at least one full periph-

eral cycle.

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Timer 0

Timer 0 functions as either a Timer 0 or an event Counter in four operating modes.

Figure 28 through Figure 31 show the logic configuration of each mode.

Timer 0 is controlled by the four lower bits of the TMOD register (see Figure 56) and bits

0, 1, 4 and 5 of the TCON register (see Figure 55). The TMOD register selects the

method of Timer 0 gating (GATE0), Timer 0 or Counter operation (T/C0#) and the oper-

ating mode (M10 and M00). The TCON register provides Timer 0 control functions:

overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit

(IT0).

For normal Timer 0 operation (GATE0 = 0), setting TR0 allows TL0 to be incremented

by the selected input. Setting GATE0 and TR0 allows external pin INT0 to control Timer 0

operation.

Timer 0 overflow (count rolls over from all 1s to all 0s) sets the TF0 flag and generates

an interrupt request.

It is important to stop the Timer 0/Counter before changing modes.

Mode 0 (13-bit Timer 0)

Mode 0 configures Timer 0 as a 13-bit Timer 0 which is set up as an 8-bit Timer 0 (TH0

register) with a module-32 prescaler implemented with the lower five bits of the TL0 reg-

ister (see Figure 28). The upper three bits of the TL0 register are indeterminate and

should be ignored. Prescaler overflow increments the TH0 register.

Figure 28. Timer 0/Counter x (x = 0 or 1) in Mode 0

FCLK_Periph

0

Timer 0 x

Interrupt

Request

Overflow

THx

(8 bits)

TLx

(5 bits)

TFx

TCON reg

1

Tx

C/Tx#

TMOD reg

INTx#

GATEx

TRx

TMOD reg

TCON reg

Mode 1 (16-bit Timer 0)

Mode 1 configures Timer 0 as a 16-bit Timer 0 with the TH0 and TL0 registers con-

nected in a cascade (see Figure 29). The selected input increments the TL0 register.

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Figure 29. Timer 0/Counter x (x = 0 or 1) in Mode 1

FCLK_Periph

0

Timer 0 x

Interrupt

Request

Overflow

THx

(8 bits)

TLx

(8 bits)

TFx

TCON reg

1

C/Tx#

TMOD reg

Tx

INTx#

GATEx

TMOD reg

TRx

TCON reg

Mode 2 (8-bit Timer 0 with

Auto-Reload)

Mode 2 configures Timer 0 as an 8-bit Timer 0 (TL0 register) that automatically reloads

from the TH0 register (see Figure 30). TL0 overflow sets the TF0 flag in the TCON reg-

ister and reloads TL0 with the contents of TH0, which is preset by the software. When

the interrupt request is serviced, the hardware clears TF0. The reload leaves TH0

unchanged. The next reload value may be changed at any time by writing it to the TH0

register.

Figure 30. Timer 0/Counter x (x = 0 or 1) in Mode 2

FCLK_Periph

0

Timer 0 x

Interrupt

Request

Overflow

TLx

(8 bits)

TFx

TCON reg

1

Tx

C/Tx#

TMOD reg

INTx#

THx

(8 bits)

GATEx

TMOD reg

TRx

TCON reg

Mode 3 (Two 8-bit Timer 0s)

Mode 3 configures Timer 0 so that registers TL0 and TH0 operate as 8-bit Timer 0s (see

Figure 31). This mode is provided for applications requiring an additional 8-bit Timer 0 or

Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in the TMOD register, and

TR0 and TF0 in the TCON register in the normal manner. TH0 is locked into a Timer 0

function (counting F_UART) and takes over use of the Timer 1 interrupt (TF1) and run con-

trol (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3.

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Figure 31. Timer 0/Counter 0 in Mode 3: Two 8-bit Counters

FCLK_Periph

0

Timer 0

Interrupt

Request

Overflow

TL0

(8 bits)

TF0

TCON.5

1

T0

C/T0#

TMOD.2

INT0

GATE0

TMOD.3

TR0

TCON.4

Timer 1

Interrupt

Request

FCLK_Periph

Overflow

TH0

(8 bits)

TF1

TCON.7

TR1

TCON.6

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Timer 1

Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The fol-

lowing comments help to understand the differences:

•

Timer 1 functions as either a Timer 0 or an event Counter in the three operating

modes. Figure 28 through Figure 30 show the logical configuration for modes 0, 1,

and 2. Mode 3 of Timer 1 is a hold-count mode.

•

Timer 1 is controlled by the four high-order bits of the TMOD register (see Figure 56)

and bits 2, 3, 6 and 7 of the TCON register (see Figure 55). The TMOD register

selects the method of Timer 0 gating (GATE1), Timer 0 or Counter operation

(C/T1#) and the operating mode (M11 and M01). The TCON register provides Timer

1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and

the interrupt type control bit (IT1).

•

Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best

suited for this purpose.

For normal Timer 0 operation (GATE1 = 0), setting TR1 allows TL1 to be

incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1

to control Timer 0 operation.

•

Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag and

generates an interrupt request.

When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit

(TR1). For this situation, use Timer 1 only for applications that do not require an

interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in

and out of mode 3 to turn it off and on.

•

It is important to stop the Timer 0/Counter before changing modes.

Mode 0 (13-bit Timer 0)

Mode 1 (16-bit Timer 0)

Mode 0 configures Timer 1 as a 13-bit Timer 0, which is set up as an 8-bit Timer 0 (TH1

register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 regis-

ter (see Figure 28). The upper 3 bits of TL1 register are ignored. Prescaler overflow

increments the TH1 register.

Mode 1 configures Timer 1 as a 16-bit Timer 0 with TH1 and TL1 registers connected in

cascade (see Figure 29). The selected input increments the TL1 register.

Mode 2 (8-bit Timer 0 with

Auto-Reload)

Mode 2 configures Timer 1 as an 8-bit Timer 0 (TL1 register) with automatic reload from

the TH1 register on overflow (see Figure 30). TL1 overflow sets the TF1 flag in the

TCON register and reloads TL1 with the contents of TH1, which is preset by the soft-

ware. The reload leaves TH1 unchanged.

Mode 3 (Halt)

Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt

Timer 1 when the TR1 run control bit is not available i.e., when Timer 0 is in mode 3.

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Registers

Table 55. TCON Register

TCON (S:88h) - Timer 0/Counter Control Register

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit

Number

Mnemonic Description

Timer 1 Overflow flag

Cleared by the hardware when processor vectors to interrupt routine.

Set by the hardware on Timer 0/Counter overflow when Timer 1 register

overflows.

7

6

5

TF1

TR1

TF0

Timer 1 Run Control bit

Clear to turn off Timer 0/Counter 1.

Set to turn on Timer 0/Counter 1.

Timer 0 Overflow flag

Cleared by the hardware when processor vectors to interrupt routine.

Set by the hardware on Timer 0/Counter overflow when Timer 0 register

overflows.

Timer 0 Run Control bit

4

3

2

1

0

TR0

IE1

IT1

IE0

IT0

Clear to turn off Timer 0/Counter 0.

Set to turn on Timer 0/Counter 0.

Interrupt 1 Edge flag

Cleared by the hardware when interrupt is processed if edge-triggered (see IT1).

Set by the hardware when external interrupt is detected on the INT1 pin.

Interrupt 1 Type Control bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1).

Set to select falling edge active (edge triggered) for external interrupt 1.

Interrupt 0 Edge flag

Cleared by the hardware when interrupt is processed if edge-triggered (see IT0).

Set by the hardware when external interrupt is detected on INT0 pin.

Interrupt 0 Type Control bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0).

Set to select falling edge active (edge triggered) for external interrupt 0.

Reset Value = 0000 0000b

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Table 56. TMOD Register

TMOD (S:89h) - Timer 0/Counter Mode Control Registers

7

6

5

4

3

2

1

0

GATE1

C/T1#

M11

M01

GATE0

C/T0#

M10

M00

Bit Number Bit Mnemonic Description

Timer 1 Gating Control bit

Clear to enable Timer 1 whenever TR1 bit is set.

7

GATE1

Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set.

Timer 1 Counter/Timer 0 Select bit

6

5

C/T1#

M11

Clear for Timer 0 operation: Timer 1 counts the divided-down system clock.

Set for Counter operation: Timer 1 counts negative transitions on external pin T1.

Timer 1 Mode Select bits

M11

0

1

M01

0

1

0

1

Operating mode

Mode 0:8-bit Timer 0/Counter (TH1) with 5-bit prescaler (TL1).

Mode 1:16-bit Timer 0/Counter.

Mode 2:8-bit auto-reload Timer 0/Counter (TL1). Reloaded from TH1 at overflow.

Mode 3:Timer 1 halted. Retains count.

4

3

M01

Timer 0 Gating Control bit

Clear to enable Timer 0 whenever TR0 bit is set.

Set to enable Timer 0/Counter 0 only while INT0 pin is high and TR0 bit is set.

GATE0

Timer 0 Counter/Timer 0 Select bit

2

1

C/T0#

M10

Clear for Timer 0 operation: Timer 0 counts the divided-down system clock.

Set for Counter operation: Timer 0 counts negative transitions on external pin T0.

Timer 0 Mode Select bit

M10

M00 Operating mode

0

1

0

1

0

Mode 0:8-bit Timer 0/Counter (TH0) with 5-bit prescaler (TL0).

Mode 1:16-bit Timer 0/Counter

Mode 2:8-bit auto-reload Timer 0/Counter (TL0). Reloaded from TH0 at overflow.

Mode 3:TL0 is an 8-bit Timer 0/Counter.

0

M00

1

TH0 is an 8-bit Timer 0 using Timer 1’s TR0 and TF0 bits.

Reset Value = 0000 0000b

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Table 57. TH0 Register

TH0 (S:8Ch) - Timer 0 High Byte Register.

7

6

5

4

3

2

1

0

Bit

Number

Bit

Mnemonic Description

7:0

High Byte of Timer 0

Reset Value = 0000 0000b

Table 58. TL0 Register

TL0 (S:8Ah) - Timer 0 Low Byte Register.

7

6

5

4

Bit

Number

Bit

Mnemonic Description

7:0

Low Byte of Timer 0

Reset Value = 0000 0000b

Table 59. TH1 Register

TH1 (S:8Dh) - Timer 1 High Byte Register.

7

6

5

4

Bit

Number

Bit

Mnemonic Description

7:0

High Byte of Timer 1

Reset Value = 0000 0000b

Table 60. TL1 Register

TL1 (S:8Bh) - Timer 1 Low Byte Register.

7

6

5

4

Bit

Number

Mnemonic Description

7:0

Low Byte of Timer 1

Reset Value = 0000 0000b

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Serial I/O Port

The serial I/O port is entirely compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as

an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex

modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-

taneously and at different baud rates.

Serial I/O port includes the following enhancements:

•

Framing error detection and Automatic Address Recognition

Internal Baud Rate Generator

Figure 32. Serial I/O UART Port Block Diagram

IB Bus

Read SBUF

Load SBUF

Write SBUF

SBUF

Receiver

SBUF

TXD

Transmitter

Mode 0 Transmit

Receive

Shift register

RXD

Serial Port

Interrupt Request

RI

TI

Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register.

Figure 33. Framing Error Block Diagram

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

Set FE bit if stop bit is 0 (framing error)

SM0 to UART mode control

POF

To UART framing error control

SMOD1 SMOD0

GF1

GF0

PD

IDL

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register bit is set.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a reset clear FE bit. Subsequently received frames with valid stop bits

cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last

data bit (See Figure 34 and Figure 35).

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Figure 34. UART Timings in Mode 1

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Stop

Bit

Start

Bit

Data Byte

RI

SMOD0 = X

FE

SMOD0 = 1

Figure 35. UART Timings in Modes 2 and 3

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start

Bit

Data Byte

Ninth Stop

Bit

RI

SMOD0 = 0

RI

SMOD0 = 1

FE

SMOD0 = 1

Automatic Address

Recognition

The automatic address recognition feature is enabled when the multiprocessor commu-

nication feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor

communication feature by allowing the serial port to examine the address of each

incoming command frame. Only when the serial port recognizes its own address, the

receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU

is not interrupted by command frames addressed to other devices.

If desired, you may enable the automatic address recognition feature in mode 1. In this

configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the

received command frame address matches the device’s address and is terminated by a

valid stop bit.

To support automatic address recognition, a device is identified by a given address and

a broadcast address.

Note:

The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e., setting SM2 bit in SCON register in mode 0 has no effect).

Given Address

Each device has an individual address that is specified in SADDR register; the SADEN

register is a mask byte that contains don’t care bits (defined by zeros) to form the

device’s given address. The don’t care bits provide the flexibility to address one or more

slaves at a time. The following example illustrates how a given address is formed.

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To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Slave C:SADDR1111 0011b

SADEN1111 1101b

Given1111 00X1b

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To commu-

nicate with slave A only, the master must send an address where bit 0 is clear (e.g.

1111 0000b).

For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both

set (e.g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set,

bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t care bits, e.g.:

SADDR0101 0110b

SADEN1111 1100b

SADDR OR SADEN1111 111Xb

The use of don’t care bits provides flexibility in defining the broadcast address, however

in most applications, a broadcast address is FFh. The following is an example of using

broadcast addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 1X11B,

Slave C:SADDR = 1111 0010b

SADEN1111 1101b

Given1111 1111b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the slaves, the master must send an address FFh. To communicate with slaves A

and B, but not slave C, the master can send and address FBh.

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Reset Addresses

On reset, the SADDR, SADEN register are initialized to 00h, i.e. the given and broad-

cast addresses are XXXX XXXXb(all don’t care bits). This ensures that the serial port is

backwards compatible with the 80C51 microcontrollers that do not support automatic

address recognition.

UART Output Configuration

Voltage Level

The I/O Ports of UART are powered by the EV_CCRegulator. The voltage of this regulator

can be:

•

Automatically controlled by the microcontroller which adapt the power supply level

versus the OE input voltage level.

•

Set at three defined levels (1.8V, 2.3V or 2.8V)

These configurations are defined with the EVAUTO and VEXT0,VEXT1 Bits of SIOCON

Register.

Output Enable Function

The UART outputs (Tx, T0) can be controlled by the Output Enable input.

The Bits PMOSEN0 and PMOSEN1 in SIOCON Register are used to control this output.

SFR

Value

0

1

0

1

0

PMOSEN0

PMOS Command

(Active at 1)

1

PMOSEN1

0

1

OE

(P3.3)

PMOSEN0

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UART Control Registers Table 61. SADEN Register

SADEN

Slave Address Mask Register (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Table 62. SADDR Register

SADDR

Slave Address Register (A9h)

7

6

5

Reset Value = 0000 0000b

Table 63. SBUF Register

SBUF

Serial Buffer Register (99h)

7

6

5

Reset Value = XXXX XXXXb

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4164G–SCR–07/06

UART Timings

The following description will be included in L version:

Mode Selection

SM0 and SM1 bits in SCON register (see Table 67) are used to select a mode among

the single synchronous and the three asynchronous modes according to Table 64.

Table 64. Serial I/O Port Mode Selection

SM0

SM1

Mode

Description

Baud Rate

Fixed / Variable

Variable

0

1

0

1

0

1

0

1

2

3

Synchronous Shift Register

8-bit UART

9-bit UART

Fixed

9-bit UART

Variable

Baud Rate Generator

Depending on the mode and the source selection, the baud rate can be generated from

either the Timer 1 or the Internal Baud Rate Generator. The Timer 1 can be used in

Modes 1 and 3 while the Internal Baud Rate Generator can be used in Modes 0, 1 and

3.

The addition of the Internal Baud Rate Generator allows freeing of the Timer 1 for other

purposes in the application. It is highly recommended to use the Internal Baud Rate

Generator as it allows higher and more accurate baud rates than with Timer 1.

Baud rate formulas depend on the modes selected and are given in the following mode

sections.

Timer 1

When using the Timer 1, the Baud Rate is derived from the overflow of the timer. As

shown in Figure 36 the Timer 1 is used in its 8-bit auto-reload mode (detailed in

Section “Timer 0/Counter Operations”, page 73). SMOD1 bit in PCON register allows

doubling of the generated baud rate.

Figure 36. Timer 1 Baud Rate Generator Block Diagram

PER

CLOCK

÷ 6

0

1

Overflow

TL1

(8 bits)

÷ 2

0

1

T1

CLOCK

To Serial Port

T1

C/T1#

TMOD.6

SMOD1

PCON.7

INT1

TH1

(8 bits)

GATE1

TMOD.7

TR1

TCON.6

Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the over-

flow of the timer. As shown in Figure 37, the Internal Baud Rate Generator is an 8-bit

auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6

depending on the SPD bit in BDRCON register (see Table 68). The Internal Baud Rate

Generator is enabled by setting BBR bit in BDRCON register. SMOD1 bit in PCON reg-

ister allows doubling of the generated baud rate.

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A/T8xC5121

Figure 37. Internal Baud Rate Generator Block Diagram

PER

CLOCK

÷ 6

0

1

Overflow

BRG

(8 bits)

÷ 2

0

1

IBRG

CLOCK

To Serial Port

SPD

BDRCON.1

BRR

BDRCON.4

SMOD1

PCON.7

BRL

(8 bits)

Synchronous Mode (Mode 0)

Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0

capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of

eight clock pulses while the receive data (RXD) pin transmits or receives a byte of data.

The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur

at a fixed Baud Rate. Figure 38 shows the serial port block diagram in Mode 0.

Figure 38. Serial I/O Port Block Diagram (Mode 0)

SCON.6

SCON.7

SM1

SM0

SBUF Tx SR

SBUF Rx SR

RXD

Mode Decoder

M3 M2 M1 M0

Mode

Controller

PER

CLOCK

Baud Rate

Controller

TI

SCON.1

RI

SCON.0

TXD

BRG

CLOCK

Transmission (Mode 0)

To start a transmission mode 0, write to SCON register clearing bits SM0, SM1.

As shown in Figure 39, writing the byte to transmit to SBUF register starts the transmis-

sion. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle

composed of a high level then low level signal on TXD. During the eighth clock cycle the

MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to

indicate the end of the transmission.

Figure 39. Transmission Waveforms (Mode 0)

TXD

Write to SBUF

RXD

TI

D0

D1

D2

D3

D4

D5

D6

D7

87

4164G–SCR–07/06

Reception (Mode 0)

To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits

and setting the REN bit.

As shown in Figure 40, Clock is pulsed and the LSB (D0) is sampled on the RXD pin.

The D0 bit is then shifted into the shift register. After eight sampling, the MSB (D7) is

shifted into the shift register, and hardware asserts RI bit to indicate a completed recep-

tion. Software can then read the received byte from SBUF register.

Figure 40. Reception Waveforms (Mode 0)

TXD

Set REN, Clear RI

D0 D1 D2

Write to SCON

RXD

RI

D3

D4

D5

D6

D7

Baud Rate Selection (Mode 0) In mode 0, baud rate can be either fixed or variable.

As shown in Figure 41, the selection is done using M0SRC bit in BDRCON register.

Figure 42 gives the baud rate calculation formulas for each baud rate source.

Figure 41. Baud Rate Source Selection (Mode 0)

PER

CLOCK

÷ 6

0

To Serial Port

1

IBRG

CLOCK

M0SRC

BDRCON.0

Figure 42. Baud Rate Formulas (Mode 0)

2^SMOD1⋅ F_PER

Baud_Rate

6^(1-SPD)⋅ 32 ⋅ (256 -BRL)

F_PER

2^SMOD1⋅ F_PER

Baud_Rate =

6

BRL = 256

6^(1-SPD)⋅ 32 ⋅ Baud_Rate

a. Fixed Formula

b. Variable Formula

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A/T8xC5121

Asynchronous Modes

(Modes 1, 2 and 3)

The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 43

shows the Serial Port block diagram in such asynchronous modes.

Figure 43. Serial I/O Port Block Diagram (Modes 1, 2 and 3)

SCON.6

SCON.7

SCON.3

SM1

SM0

TB8

SBUF Tx SR

Rx SR

TXD

RXD

Mode Decoder

M3 M2 M1 M0

T1

CLOCK

IBRG

CLOCK

Mode & Clock

Controller

SBUF Rx

RB8

SCON.2

PER

CLOCK

SM2

SCON.4

TI

SCON.1

RI

SCON.0

Mode 1

Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 44) consists of

10 bits: one start, eight data bits and one stop bit. Serial data is transmitted on the TXD

pin and received on the RXD pin. When a data is received, the stop bit is read in the

RB8 bit in SCON register.

Figure 44. Data Frame Format (Mode 1)

Mode 1

D0

D1

D2

D3

D4

D5

D6

D7

Start Bit

8-bit Data

Stop Bit

Modes 2 and 3

Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 45)

consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one

programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin

and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON

register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alterna-

tively, you can use the ninth bit as a command/data flag.

Figure 45. Data Frame Format (Modes 2 and 3)

Modes 2 and 3

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start Bit

9-bit Data

Stop Bit

Transmission (Modes 1, 2

and 3)

To initiate a transmission, write to SCON register, setting SM0 and SM1 bits according

to Table 64, and setting the ninth bit by writing to TB8 bit. Then, writing the byte to be

transmitted to SBUF register starts the transmission.

Reception (Modes 1, 2 and 3)

To prepare for a reception, write to SCON register, setting SM0 and SM1 bits according

to Table 64, and setting REN bit. The actual reception is then initiated by a detected

high-to-low transition on the RXD pin.

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4164G–SCR–07/06

Framing Error Detection

(Modes 1, 2 and 3)

Framing error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register as shown in

Figure 46.

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two devices. If a valid stop bit is not found, the software sets FE bit in

SCON register.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a chip reset clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on

stop bit instead of the last data bit as detailed in Figure 36.

Figure 46. Framing Error Block Diagram

Framing Error

Controller

FE

1

0

SM0/FE

SCON.7

SM0

SMOD0

PCON.6

Baud Rate Selection (Modes 1 In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud

and 3)

Rate Generator and allows different baud rate in reception and transmission.

As shown in Figure 47 the selection is done using RBCK and TBCK bits in BDRCON

register.

Figure 48 gives the baud rate calculation formulas for each baud rate source while

Table 65 details Internal Baud Rate Generator configuration for different peripheral

clock frequencies and giving baud rates closer to the standard baud rates.

Figure 47. Baud Rate Source Selection (Modes 1 and 3)

T1

CLOCK

0

1

To Serial

Reception Port

To serial

Transmission Port

÷ 16

1

IBRG

CLOCK

RBCK

BDRCON.2

TBCK

BDRCON.3

Figure 48. Baud Rate Formulas (Modes 1 and 3)

^SMOD1⋅ F_PER

2^SMOD1⋅ F_PER

6 ⋅ 32 ⋅ (256 -TH1)

Baud_Rate

6^(1-SPD)⋅ 32 ⋅ (256 -BRL)

2^SMOD1⋅ F_PER

192 ⋅ Baud_Rate

BRL = 256

TH1 = 256

6^(1-SPD⋅ 32 ⋅ Baud_Rate

a. BRG Formula

b. T1 Formula

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A/T8xC5121

Table 65. Internal Baud Rate Generator Value

F_PER= 6 MHz¹

F_PER= 8 MHz¹

Baud Rate

115200

57600

38400

19200

9600

SPD

SMOD1

BRL

-

Error %

-

SPD

SMOD1

BRL

-

Error %

-

1

247

243

230

204

152

3.55

0.16

1

246

236

217

178

2.34

0.16

4800

F

_PER= 12 MHz²

F_PER= 16 MHz²

Baud Rate

115200

57600

38400

19200

9600

SPD

SMOD1

BRL

-

Error %

-

SPD

SMOD1

BRL

247

239

230

204

152

48

Error %

3.55

-

1

243

236

217

178

100

0.16

2.34

0.16

2.12

0.16

4800

0.16

Notes: 1. These frequencies are achieved in X1 mode, F_PER= F_OSC÷ 2.

2. These frequencies are achieved in X2 mode, F_PER= F_OSC

.

Baud Rate Selection (Mode 2) In mode 2, the baud rate can only be programmed to two fixed values: 1/16 or 1/32 of

the peripheral clock frequency.

As shown in Figure 49, the selection is done using SMOD1 bit in PCON register.

Figure 50 gives the baud rate calculation formula depending on the selection.

Figure 49. Baud Rate Generator Selection (Mode 2)

PER

CLOCK

³ 2

0

1

³ 16

To Serial Port

SMOD1

PCON.7

Figure 50. Baud Rate Formula (Mode 2)

2SMOD1 ⋅ FPER

Baud_Rate =

32

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4164G–SCR–07/06

Table 66. BRL (S:91h)

BRL Register

Baud Rate Generator Reload Register

7

6

5

4

3

2

1

0

BRL7

BRL6

BRL5

BRL4

BRL3

BRL2

BRL1

BRL0

Bit

Number

Mnemonic Description

7 - 0

BRL7:0 Baud Rate Reload Value.

Reset Value = 0000 0000b

92

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A/T8xC5121

Table 67. SCON Register

SCON (S:98h)

Serial Control Registe

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Number

Mnemonic

Description

Framing Error bit

To select this function, set SMOD0 bit in PCON register.

Set by hardware to indicate an invalid stop bit.

Must be cleared by software.

FE

7

Serial Port Mode bit 0

To select this function, clear SMOD0 bit in PCON register.

Software writes to bits SM0 and SM1 to select the Serial Port operating mode.

Refer to SM1 bit for the mode selections.

SM0

SM1

Serial Port Mode bit 1

To select this function, set SMOD0 bit in PCON register.

Software writes to bits SM1 and SM0 to select the Serial Port operating mode.

SM0

SM1 Mode Description

Baud Rate

6

5

0

1

0

1

Shift Register F_OSC/12 or variable if SRC bit in BDRCON is set

8-bit UART

9-bit UART

Variable

1

0

1

2

3

F_OSC/32 or F_OSC/64

Variable

Serial Port Mode bit 2

Software writes to bit SM2 to enable and disable the multiprocessor communication and automatic address

recognition features.

SM2

This allows the Serial Port to differentiate between data and command frames and to recognize slave and broadcast

addresses.

Receiver Enable bit

4

3

REN

TB8

Clear to disable reception in mode 1, 2 and 3, and to enable transmission in mode 0.

Set to enable reception in all modes.

Transmit bit 8

Modes 0 and 1: Not used.

Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.

Receiver bit 8

Mode 0: Not used.

2

RB8

Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit received.

Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit received.

Transmit Interrupt flag

1

0

TI

Set by the transmitter after the last data bit is transmitted.

Must be cleared by software.

Receive Interrupt flag

Set by the receiver after the stop bit of a frame has been received.

Must be cleared by software.

RI

Reset Value = XXX0 0000b

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4164G–SCR–07/06

Table 68. BDRCON Register

BDRCON

Baud Rate Control Register (9Bh)

7

-

6

-

5

-

4

3

2

1

0

BRR

TBCK

RBCK

SPD

SRC

Bit

Number Mnemonic Description

Reserved

7

6

5

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Baud Rate Run Control bit

Clear to stop the Baud Rate.

Set to start the Baud Rate.

4

3

2

1

0

BRR

TBCK

RBCK

SPD

Transmission Baud rate Generator Selection bit for first UART

Clear to select Timer 1 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Reception Baud Rate Generator Selection bit for first UART

Clear to select Timer 1 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Baud Rate Speed Control bit for first UART

Clear to select the SLOW Baud Rate Generator when SRC = 1.

Set to select the FAST Baud Rate Generator when SRC = 1.

Baud Rate Source select bit in Mode 0 for first UART

Clear to select F_OSC/12 as the Baud Rate Generator.

Set to select the internal Baud Rate Generator.

SRC

Reset Value = XXX0 0000b

94

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4164G–SCR–07/06

A/T8xC5121

Table 69. SIOCON Register

Serial Input Output Configuration Register

Register (91h)

7

6

5

4

3

2

1

0

CPRES

RES

PMSOEN1 PMSOEN0

-

EVAUTO

VEXT0

VEXT1

Bit

Number Mnemonic Description

Output Enable function on Txd/P3.1 and T0/P3.4:

PMSOEN1 PMSOEN0

PMOSEN1 0

0

1

0

1

PMOS is always off (reset value)

7 - 6

PMOSEN0 0

PMOS is always driven according to P3.1 or P3.4 value

PMOS is driven only when OE is high

1

PMOS is driven only when OE is low

Reserved

5 - 4

-

The value read from this bit is indeterminate. Do not set this bit.

Card Presence pull-up resistor

0 Internal pull-up is connected

1 Internal pull-up is disconnected

CPRES

RES

3

EVCC Auto setup

2

EVAUTO Set to enable the Automatic mode of EV_CCregulator

Clear to disable the Automatic mode of EV_CCregulator

EVCC voltage configuration:

VEXT0 VEXT1

VEXT0

VEXT1

0

1

0

1

0

1

Power-down, EV_CCis external (reset value)

1 - 0

EV_CC= 1.8V

EV_CC= 2.3V

EV_CC= 2.7V

Reset Value = 00XX 0000b

95

4164G–SCR–07/06

Hardware Watchdog

Timer

The WDT is intended as a recovery method in situations where the CPU may be sub-

jected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer

ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable

the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location

0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator

is running and there is no way to disable the WDT except through reset (either hardware

reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH

pulse at the RST-pin.

Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR

location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH

and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it

reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will

increment every machine cycle while the oscillator is running. This means the user must

reset the WDT at least every 16383 machine cycle. To reset the WDT the user must

write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter

cannot be read or written. When WDT overflows, it will generate an output RESET pulse

at the RST-pin. The RESET pulse duration is 96 x T_{CLK PERIPH}, where T_{CLK PERIPH}= 1/F_CLK

_PERIPH. To make the best use of the WDT, it should be serviced in those sections of code

that will periodically be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 2⁷counter has been added to extend the Time-out

capability, ranking from 16 ms to 2s @ F_OSCA= 12 MHz. To manage this feature, refer to

WDTPRG register description, Table 70. The WDTPRG register should be configured

before the WDT activation sequence, and can not be modified until next reset.

Table 70. WDTRST Register

WDTRST - Watchdog Reset Register (0A6h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Reset Value = XXXX XXXXb

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in

sequence.

96

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A/T8xC5121

Table 71. WDTPRG Register

WDTPRG - Watchdog Timer Out Register (0A7h)

7

-

6

-

5

-

4

-

3

-

2

1

0

S2

S1

S0

Bit

Number

Mnemonic Description

7

6

5

4

3

2

1

0

-

Reserved

-

The value read from this bit is undetermined. Do not try to set this bit.

-

S2

S1

S0

WDT Time-out select bit 2

WDT Time-out select bit 1

WDT Time-out select bit 0

S2 S1 S0

Selected Time-out

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(2¹⁴- 1) machine cycles, 16. 3 ms @ F_OSCA=12 MHz

(2¹⁵- 1) machine cycles, 32.7 ms @ F_OSCA=12 MHz

(2¹⁶- 1) machine cycles, 65. 5 ms @ F_OSCA=12 MHz

(2¹⁷- 1) machine cycles, 131 ms @ F_OSCA=12 MHz

(2¹⁸- 1) machine cycles, 262 ms @ F_OSCA=12 MHz

(2¹⁹- 1) machine cycles, 542 ms @ F_OSCA=12 MHz

(2²⁰- 1) machine cycles, 1.05 ms @ F_OSCA=12 MHz

(2²¹- 1) machine cycles, 2.09 ms @ F_OSCA=12 MHz

Reset Value = XXXX X000

WDT during Power-down In Power-down mode the oscillator stops, which means the WDT also stops. While in

Power-down mode the user does not need to service the WDT. There are 2 methods of

and Idle

exiting Power-down mode: by a hardware reset or via a level activated external interrupt

which is enabled prior to entering Power-down mode. When Power-down is exited with

hardware reset, servicing the WDT should occur as it normally should whenever the

T8xC5121 is reset. Exiting Power-down with an interrupt is significantly different. The

interrupt is held low long enough for the oscillator to stabilize. When the interrupt is

brought high, the interrupt is serviced. To prevent the WDT from resetting the device

while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.

It is suggested that the WDT be reset during the interrupt service routine.

To ensure that the WDT does not overflow within a few states of exiting of powerdown, it

is better to reset the WDT just before entering powerdown.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the

T8xC5121 while in Idle mode, the user should always set up a timer that will periodically

exit Idle, service the WDT, and re-enter Idle mode.

97

4132C–SCR–07/06

Electrical Characteristics

Absolute Maximum Ratings

Note:

Stresses at or above those listed under “ Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions above those indicated in the operational

sections of this specification is not implied. Exposure

to absolute maximum rating conditions may affect

device reliability.

Ambiant Temperature Under Bias ......................-25°C to 85°C

Storage Temperature ................................... -65°C to + 150°C

Voltage on V_CCto V_SS........................................-0.5V to + 6.0V

Voltage on Any Pin to V_SS.......................... -0.5V to V_CC+ 0.5V

DC Parameters

T_A= -40°C to +85°C; V_SS= 0 V; V_CC= 2.85V to 5.4V; F = 7.36 to 16 MHz

Table 72. Core DC Parameters (XTAL, RST, P0, P2, ALE, PSEN, EA)

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

V_IL

Input Low Voltage

-0.5

0.2 V_CC- 0.1

V

Input High Voltage

except XTAL1, RST

V_IH

V_IH1

V_OL

.2 V_CC+ .9

0.7 V_CC

V_CC+ 0.5

0.45

V

Input High Voltage,

XTAL1, RST

Output Low Voltage,

Port 0 and 2

I_{OL =}1.6 mA

Output High Voltage,

Port 0 and 2

V_OH

0.9 x V_CC

I_OH= -40 µA

Digital Supply Output

Current

DI_CC

6

10

mA C_L= 100 nF

C_L= 100 nF

Digital Supply

Voltage

DV_CC

Icc

2.5

2 .9

80

3.0

100

30

V

DIcc=10mA

Normal Power Down

mode

µA

25°C

Pulsed Power Down

mode

Icc

20

50°C Vcc=3V

V_CC= 5.4V and

Bootloader

execution

Iccop

I_ccop= 0.25 Freq (MHz) +4 mA

Power Supply

current

I_ccIDLE= 0.03 Freq (MHz) +5 mA

Power-fail high level

threshold

V_PFDP

V_PFDM

t_G

2 .55

2 .45

50

V

Power-fail low level

threshold

Power Fail glitch

time

ns

V_DDrise and fall

time

t_rise,t_fall

1 μs

600

sec.

98

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4164G–SCR–07/06

A/T8xC5121

The operating conditions for I_CCTests are the following:

Figure 51. I_CCTest Condition, Active Mode

V_CC

I_CC

V_CC

P0

EA

LI

V_CC

RST

XTAL2

XTAL1

(NC)

CLOCK SIGNAL

V_SS

PLCC52 configuration

All other pins are disconnected.

Figure 52. I_CCTest Condition, Idle Mode

V_CC

I_CC

V_CC

LI

V_CC

P0

EA

RST

(NC)

CLOCK SIGNAL

XTAL2

XTAL1

V_SS

PLCC52 configuration

All other pins are disconnected.

Figure 53. I_CCTest Condition, Power-down Mode

V_CC

I_CC

V_CC

LI

V_CC

P0

RST

EA

(NC)

XTAL2

XTAL1

V_SS

PLCC52 configuration

All other pins are disconnected.

99

4164G–SCR–07/06

Table 73. Serial Interface DC parameters (P3.0, P3.1, P3.3 and P3.4)

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

-0.5

0.4

0.5

V

EV_CC= 1.8V

EV_CC= 2.3V

V_IL

Input Low Voltage

EV_CC= 2.8V

External EVcc

Automatic EVcc

2.3

2.8

3.3

1.4

1.6

V

EV_CC= 1.8V

EV_CC= 2.3V

EV_CC= 2.8V

External EV_CC

Automatic EVcc

V_IH

Input High Voltage

2.0

EV_CC

0.5

+

0.7 x EV_CC

EV_CC

Output Low

Voltage

V_OL

V_OH

EI_CC

0.4

V

I_OL= 1.2 mA

1.6

1.8

2.3

2.7

V

EV_CC= 1.8V I_OH= 1 μA

EV_CC= 2.3V

Output High

Voltage

2.2

EV_CC= 2.8V I_OH= 10μA

External EV_CC

0.8 x EV_CC

EV_CC

Extra Supply

Current

+3

mA C_L= 100 nF

1.6

2.1

2.6

1.6

1.7

2.2

2.7

1.8

2.3

2.8

V_CC

V

C_L= 100 nF, 1.8V

C_L= 100 nF, 2.3V

C_L= 100 nF, 2.8V

External EV_CC

Extra Supply

Voltage

EV_CC

Automatic EVcc

Ts

Sampling time

Automatic EVcc

Table 74. LED outputs DC Parameters (P3.6 and P3.7)

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

1

2

5

2

4

8

mA

2 mA configuration

4 mA configuration

Output Low

Current, P3.6 and

P3.7 LED modes

I_OL

10

20

10 mA configuration

(T_A= -20°C to +50°C, V_CC

-

V_OL= 2V 20%)

100

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4164G–SCR–07/06

A/T8xC5121

Table 75. Smart Card 5V Interface DC Parameters

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

121

105

102

V_CC= 5.4V

Card Supply

Current

CI_CC

60

mA V_CC= 4V

V_CC= 2.85V

Card Supply

Voltage

CV_CC

4.6

5.4

V

CIcc = 60 mA

Ripple on CVcc

200

mV 0<CIcc<60 mA

Maxi. charge 20 nA.s

Max. duration 400 ns

CV_CC

Spikes on CVcc

5.4

V

Max. variation CIcc 100 mA

(1)

CIcc = 0

T_VHLl

Note:

CVcc to 0

750

μs

CVcc = 5V to 0.4V (1)

1. Capacitor = 10 µF, X7R type. Maximum ESR value is 250 mohm, Inductor = 4.7 µH.

Table 76. Smart Card 3V Interface DC Parameters

Symbol

Parameter

Min

Typ

Max

Unit Test Conditions

110

89

V

_CC= 5.4V

mA V_CC= 4V

V_CC= 2.85V

Card Supply

Current

CI_CC

60

110

Card Supply

Voltage

CV_CC

2.76

3.24

200

V

CIcc = 60 mA

Ripple on CVcc

mV 0<CIcc<60 mA

Max. charge 10 ns

CV_CC

Spikes on CVcc

3.24

750

V

Max. duration 400 ns

Max. variation CIcc 50 mA

CIcc = 0

T_VHLl

Note:

CVcc to 0

μs

CVcc = 5V to 0.4V (1)

1. Capacitor = 10 µF, X7R type. Maximum ESR value is 250 mohm, Inductor = 4.7 µH.

Table 77. Smart Card 1.8V Interface DC Parameters

Symbol

Parameter

Min

Typ

Max

Unit Test Conditions

109

100

82

V_CC= 5.4V

mA V_CC= 4V

V_CC= 2.85V

Card Supply

Current

CI_CC

20

Card Supply

Voltage

CV_CC

T_VHLl

1.68

1.92

750

V

CIcc = 20 mA

Spikes on CVcc

CVcc to 0

CIcc = 0

μs

CVcc = 5V to 0.4V (1)

Note:

1. Capacitor = 10 µF, X7R type. Maximum ESR value is 250 mohm, Inductor = 4.7 µH.

101

4164G–SCR–07/06

Table 78. Smart Card Clock DC Parameters (Port P1.4)

Symbol Parameter

Min

Typ

Max

Unit Test Conditions

0(1)

0.2 x CV_CC

0.4

V

I_OL= 20 μΑ (1.8,3 V)

_OL= 50 μA (5V)

Output Low

Voltage

V_OL

I

Output Low

Current

I_OL

15

mA

0.7 x CV_CC

CV_CC- 0.5

CV_CC

V

I_OH= 20 μA (1.8V)

I_OH= 20 μA (3V)

I_OH= 50 μA (5V)

Output High

Voltage

V_OH

Output High

Current

I_OH

15

mA

16

22.5

50

C_IN= 30 pF(5V)

C_IN= 30 pF(3V)

C_IN= 30 pF(1.8V)

t_Rt_F

Rise and Fall time

ns

V

0.4 x CV_CC

-0.25

Low level

High level

CV_CC

0.25

+

Voltage Stability

CV_CC-0.5

Note:

1. The voltage on CLK should remain between -0.3V and CV_CC+ 0.3V during dynamic

operation.

Table 79. Alternate Card Clock DC parameters (Port P3.6): 5V tolerant

Symbol Parameter

Min

Typ

Max

Unit Test Conditions

0 (1)

0(1)

V

I_OL= 20 μA

I_OL= -200 μA

Output Low

Voltage

0.2 x DV_CC

0.5

V_OL

Output High

Voltage

V_OH

0.7 x DV_CC

DV_CC(1)

18

V

I_OH= 20 μA

Rise and Fall

times

t_Rt_F

ns

C_IN= 30 pF

Note:

1. The voltage on CLK should remain between -0.3V and V_CC+ 0.3V during dynamic

operation.

102

A/T8xC5121

4164G–SCR–07/06

A/T8xC5121

Table 80. Smart Card I/O DC Parameters (P1.0)

Symbol Parameter

Min

Typ

Max

Unit

Test Conditions

0.5

0(1)

V

I_IL= 500 μA

I_IL= 20 μA

V_IL

Input Low Voltage

0.15 x

CV_CC

I_IL

V_IH

I_IH

Input Low Current

Input High Voltage

Input High Current

500

CV_CC

μA

V

0.7 x CV_CC

I_IH= -20 μA

-20 / +20

μA

0.4

0.3

I_OL= 1μA (5V)

I_OL= 1 mA (3V)

Output Low

Voltage

V_OL

0(1)

V

I_OL= 1 mA (1.8V)

Output Low

Current

I_OL

V_OH

I_OH

15

CV_CC(1)

15

mA

V

Output High

Voltage

0.8 x CV_CC

I_OH= 20 μA (5V,3V,1.8V)

Output High

Current

mA

μs

Rise and Fall

times

t_Rt_F

0.8

C_IN= 30 pF Output

Note:

1. The voltage on RST should remain between -0.3V and CV_CC+ 0.3V during dynamic

operation.

Table 81. Alternate Card I/O DC Parameters (P3.5) : 5V tolerant

Symbol Parameter

Min

-0.3

Typ

Max

Unit

V

Test Conditions

I_IL= 1 mA

I_IH= -20 μA

_OL= 1000 μA

V_IL

V_IH

Input Low Voltage

0.2 x DV_CC

DV_CC+ 0.3

Input High Voltage

0.7 x DV_CC

V

Output Low

Voltage

V_OL

V_OH

t_Rt_F

0(1)

0.3

DV_CC(1)

1

V

I

Output High

Voltage

0.7 x DV_CC

I_OH= 20 μA

Rise and Fall

delays

μs

C_IN= 30 pF

Note:

1. The voltage on I/O should remain between -0.3V and DV_CC+ 0.3V during dynamic

operation.

103

4164G–SCR–07/06

Table 82. Smart Card RST, CC4, CC8, DC Parameters (Port P1.5, P1.3, P1.1)

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

0.12 x

CV_CC

0(1)

I_OL= 20 μΑ

I_OL= 50 μΑ

V_OL

Output Low Voltage

V

0.4

I_OL

Output Low Current

Output High Voltage

15

mA

V

CV_CC- 0.5

0.8 x CV_CC

CV_CC

I_OH= 50 μΑ

V_OH

CV_CC(1)

I_OH= 20 μΑ

I_OH

Output High Current

Rise and Fall delays

15

0.8

mA

t_Rt_F

μs C_IN= 30 pF

0.4 x CV_CC

-0.25

Low level

High level

CV_CC

0.25

+

Voltage stability

CV_CC-0.5

Note:

1. The voltage on RST should remain between -0.3V and CV_CC+ 0.3V during dynamic

operation.

Table 83. Alternate Card RST DC Parameters (Port P3.7) : 5V tolerant

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

V_OL

Output Low Voltage

0 (1)

0.2 x DV_CC

V

I_OL= 200 μΑ

_OH= 20 μΑ (1.8V)

I_OH= 200 μΑ (3V)

0.8 x DV_CC

DV_CC(1)

DV_CC

I

V_OH

Output High Voltage

Rise and Fall delays

V

t_Rt_F

400

μs C_IN= 30 pF

Note:

1. The voltage on RST should remain between -0.3V and DV_CC+ 0.3V during dynamic

operation.

Table 84. Card Presence DC Parameters (P1.2)

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

P1.2 = 1, short to V_SS

CPRES weak pull-

up output current

I_OL1

3

10

25

μA

(internal pull-up enabled)

104

A/T8xC5121

4164G–SCR–07/06

A/T8xC5121

Typical Application

Figure 54. Typical Application Diagram

EV_CC

DV

L1

V_CC

LI

^CCC2

C3

V_CC

C1

100nF

4.7 µF

V_SS

4.7 µH

V_SS

(1)(2)(3)

CV_CC

CVCC

CVSS

(4)

DV_CC

or V_CC

LED0

LED1

10µF

C4

P3.6

P3.7

100nF

C5

10 kohm

V_SS

CIO

I/O

P1.0

P1.1

P1.3

C8

CC8

CC4

Serial Interface

T0

P3.4

P3.3

C4

RTS

OE

INT1/OE

TxD

CLK⁽⁵⁾

P1.4

CCLK

22 pF

C6

P3.1

P3.0

82 pF

TxD

RxD

C7

RxD

V_SS

CRST

P1.5

P1.2

RST

Vcc

CPRES

1Mohm

(optional resistor)

Positive

Detection

Mode

V_CC

V_SS

CIO1

P3.5

I/O

Alternate

Card

CRST1

CCLK1

P3.7

P3.6

RST

CLK

V_SS

XTAL2

XTAL1

Resonator

or Quartz with standard

capacitors

V_SS

Y1

V_SS

Notes: 1. C4 and C5 must be placed near IC and have low ESR (<250mΩ)

2. Straight and short connections avoid any loop between:

- CVSS and V_SS

- CV_CCand C4, C5

3. V_CCconnection of the master card must be placed as follows:

cV_CC

to card V_CC

C4, C5

CVSS

4. Current is limited to 10 mA.

5. CCLK should be routed far from CRST, CIO, CC4, CC8 and armored by ground plane.

105

4164G–SCR–07/06

6. Distance between Device pads and Smart Card connector must be less than 4

centimeters.

7. C6,C7 should be as close as possible to the Smart Card connector to reduce noise

and interferences.

106

A/T8xC5121

4164G–SCR–07/06

A/T8xC5121

Ordering Information

Code Memory

Size (Bytes)

Temperature

Range

Product

Marking

Part Number

Supply Voltage

Max Frequency

Package

Packing

T83C5121xxx-

ICSIL

16K ROM

2.85 - 5.4V

Industrial

16 MHz

SSOP24

Stick

83C5121-IL

T83C5121xxx-

ICRIL

16K ROM

2.85 - 5.4V

16 MHz

SSOP24

PLCC52⁽¹⁾

Tape & Reel

Stick

83C5121-IL

T83C5121xxx-

S3SIL

T83C5121xxx-

S3RIL

Tape & Reel

T85C5121-ICSIL

T85C5121-ICRIL

T85C5121-S3SIL

T85C5121-S3RIL

T89C5121-ICSIL

T89C5121-ICRIL

16K RAM

2.85 - 5.4V

Industrial

16 MHz

SSOP24

PLCC52

SSOP24

Stick

Tape & Reel

Stick

85C5121-IL

89C5121-IL

16K RAM

Tape & Reel

Stick

16K Flash RAM

Tape & Reel

AT83C5121xxx-

ICSUL

Industrial &

Green

16K ROM

2.85 - 5.4V

16 MHz

SSOP24

QFN32

Stick

Tape & Reel

Tray

83C5121-UL

85C5121-UL

89C5121-UL

AT83C5121xxx-

ICRUL

Industrial &

Green

AT83C5121xxx-

PUTUL

Industrial &

Green

16K ROM

AT83C5121xxx-

PURUL

Industrial &

Green

16K ROM

QFN32

Tray

AT83C5121xxx-

S3SUL

Industrial &

Green

16K ROM

PLCC52⁽¹⁾

SSOP24

PLCC52

SSOP24

Stick

AT83C5121xxx-

S3RUL

Industrial &

Green

16K ROM

Tape & Reel

Stick

AT85C5121-

ICSUL

Industrial &

Green

16K RAM

AT85C5121-

ICRUL

Industrial &

Green

16K RAM

Tape & Reel

Stick

AT85C5121-

S3SUL

Industrial &

Green

16K RAM

AT85C5121-

S3RUL

Industrial &

Green

16K RAM

Tape & Reel

Stick

AT89C5121-

ICSUL

Industrial &

Green

16K Flash RAM

AT89C5121-

ICRUL

Industrial &

Green

Tape & Reel

Note:

1. Contact Atmel for availability.

107

4164G–SCR–07/06

Package Drawings

SSOP24

108

A/T8xC5121

4164G–SCR–07/06

A/T8xC5121

PLCC52

109

4164G–SCR–07/06

QFN32

110

A/T8xC5121

4164G–SCR–07/06

A/T8xC5121

Document Revision History for T8xC5121

Changes from 4164B -

06/02 to 4164C - 07/03

1. Ports description update.

2. Added Bootloader Autobaud table.

3. Modified I_CCtest conditions Figure 51.

4. Added I_CCOPpower supply current characteristics.

5. Added I_CCOpulsed power down mode current characteristics.

6. Modified Smart card characteristics : V_CC/CV_CCmixed.

Changes from 4164C -

07/03 to 4164D - 12/03

1. Changed value of EMV to EMV2000. Section “Features”, page 1.

Changes from 4164D -

12/03 to 4164E - 01/04

1. DVcc Min/Max values changed, page 96.

2. Alternate Card Pads are 5V tolerant, page 99.

Changes from 4164E -

01/04 to 4164F 11/05

1. Added green product ordering information.

Changes from 4164F

11/05 to 4164F 07/06

1. Added QFN32 package to ordering information.

111

4164G–SCR–07/06

Table of

Contents

Features ................................................................................................. 1

Description ............................................................................................ 2

Block Diagram ...................................................................................... 2

Pin Description ..................................................................................... 3

Signals...................................................................................................................5

Port Structure Description....................................................................................10

SFR Mapping ....................................................................................... 12

PowerMonitor ...................................................................................... 14

Description.......................................................................................................... 14

PowerMonitor Diagram....................................................................................... 14

Power Monitoring and Clock Management ...................................... 16

Idle Mode............................................................................................................ 16

Power-down Mode.............................................................................................. 16

Clock Management............................................................................. 22

Functional Block Diagram................................................................................... 22

X2 Feature...........................................................................................................23

Clock Prescaler....................................................................................................24

Clock Control Registers...................................................................................... 24

DC/DC Clock ....................................................................................... 27

Clock Control Register........................................................................................ 27

Clock Prescaler................................................................................................... 27

Smart Card Interface Block (SCIB) ................................................... 29

Introduction......................................................................................................... 29

Main Features..................................................................................................... 29

Block Diagram .....................................................................................................30

Functional Description ........................................................................................ 30

Other Features.....................................................................................................35

DC/DC Converter.................................................................................................37

Registers Description...........................................................................................38

Interrupt System ................................................................................. 47

INT1 Interrupt Vector .......................................................................................... 48

LED Ports Configuration .................................................................... 57

Registers Definition............................................................................................. 57

Dual Data Pointer ................................................................................ 58

i

A/T8xC5121

4164G–SCR–07/06

A/T8xC5121

Memory Management ......................................................................... 60

Program Memory................................................................................................ 60

In-System Programming..................................................................................... 63

Protection Mechanisms ...................................................................................... 66

Autobaud ............................................................................................................ 71

Protection Mechanisms ...................................................................................... 71

Timers/Counters ................................................................................. 73

Introduction......................................................................................................... 73

Timer 0/Counter Operations ............................................................................... 73

Timer 0.................................................................................................................74

Timer 1.................................................................................................................77

Registers............................................................................................................. 78

Serial I/O Port ...................................................................................... 81

Framing Error Detection ..................................................................................... 81

Automatic Address Recognition.......................................................................... 82

UART Output Configuration................................................................................ 84

UART Control Registers..................................................................................... 85

UART Timings ..................................................................................... 86

Mode Selection................................................................................................... 86

Baud Rate Generator.......................................................................................... 86

Asynchronous Modes (Modes 1, 2 and 3)...........................................................89

Hardware Watchdog Timer ................................................................ 96

Using the WDT ................................................................................................... 96

WDT during Power-down and Idle...................................................................... 97

Electrical Characteristics ................................................................... 98

Absolute Maximum Ratings ............................................................................... 98

DC Parameters................................................................................................... 98

Typical Application ........................................................................... 105

Ordering Information........................................................................ 107

Package Drawings............................................................................ 108

SSOP24............................................................................................................ 108

PLCC52 .............................................................................................................109

QFN32 ...............................................................................................................110

Document Revision History for T8xC5121..................................... 111

Changes from 4164B -06/02 to 4164C - 07/03................................................. 111

Changes from 4164C - 07/03 to 4164D - 12/03................................................ 111

Changes from 4164D - 12/03 to 4164E - 01/04................................................ 111

ii

4164G–SCR–07/06

Changes from 4164E - 01/04 to 4164F 11/05 .................................................. 111

Changes from 4164F 11/05 to 4164F 07/06..................................................... 111

Table of Contents .................................................................................. i

iii

A/T8xC5121

4164G–SCR–07/06

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

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Literature Requests

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Printed on recycled paper.

4164G–SCR–07/06


型号：	AT85C5121-ICSIL
厂家：	ATMEL
描述：	Microcontroller, 8-Bit, CRAM, 16MHz, CMOS, PDSO24, SSOP-24 微控制器
文件：	总115页 (文件大小：840K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT85C5121-ICSIL [ATMEL]

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