AT84AS004VTP_技术文档

Features

• 10-bit Resolution

• 2 Gsps Sampling Rate

• Selectable 1:2 or 1:4 Demultiplexed Output

• 500 mVpp Differential 100Ω or Single-ended 50Ω Analog Input

• 100Ω Differential or Single-ended 50Ω Clock Input

• LVDS Output Compatibility

• Functions:

– ADC Gain Adjust

10-bit

2 Gsps ADC

With

– Sampling Delay Adjust

– 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs

– Data Ready Output with Asynchronous Reset

– Out-of-range Output Bit (11th Bit)

• Power Consumption: 6.5W

• Power Supplies: -5V, -2.2V, 3.3V and V_PLUSDOutput Power Supply

• Package

1:4 DMUX

– Cavity Down EBGA 317 (Enhanced Ball Grid Array)

– 25 × 35 mm Dimensions

AT84AS004

Performances

• 3 GHz Full Power Analog Input Bandwidth

• -0.5 dB Gain Flatness from DC up to 1.5 GHz

• Single-tone Performance at Fs = 2 Gsps, Full First and Second Nyquist (- 1 dBFS)

– ENOB = 7.8 Effective Bits, F_IN= 1000 MHz

– SNR = 51 dBc, SFDR = -55 dBc, F_IN= 1000 MHz

– ENOB = 7.5 Effective Bits, F_IN= 2 GHz

– SNR = 50 dBc, SFDR = -54 dBc, F_IN= 2 GHz

• Dual-tone Performance (IMD3) at Fs = 2 Gsps (-7 dBFS Each Tone)

– Fin1 = 945 MHz, Fin2 = 955 MHz: IMD3 = -60 dBF_S

– Fin1 = 1545 MHz, Fin2 = 1555 MHz: IMD3 = -60 dBF_S

Screening

• Temperature Range:

– T_amb> 0°C; T_J< 90°C (Commercial C Grade)

– T_amb> -40°C; T_J< 110°C (Industrial V Grade)

Applications

• Direct RF Down Conversion

• Broadband Digital Receivers

• Test Instrumentation

• High Speed Data Acquisition

• High Energy Physics

5431C–BDC–01/06

1. Description

The AT84AS004 combines a 10-bit 2 Gsps analog-to-digital converter with a 1:4 DMUX,

designed for accurate digitization of broadband signals in either first or second Nyquist zone. It

features 7.8 Effective Number of Bits (ENOB) and -55 dBFS Spurious Free Dynamic Range

(SFDR) at 2 Gsps over the full first Nyquist zone and 7.5-bit with 54 dB SFDR over full second

Nyquist.

The 1:4 demultiplexed digital outputs are LVDS logic compatible, allowing easy interfacing with

standard FPGAs or DSPs. The AT84AS004 operates at up to 2 Gsps.

The AT84AS004 comes in a 25 × 35 mm EBGA317 package. This package has the same TCE

as FR4 boards, offering excellent reliability when subjected to large thermal shocks.

2. Block Diagram

Figure 2-1. Block Diagram

BIST

ASYNRST

PGEB

DRRB

SDA

2

20

CLK/CLKN

Port A

SDA

2

AOR/AORN

Port B

20

2

BOR/BORN

VIN

Demultiplexer

1:2 or 1:4

20

2

Port C

S/H

COR/CORN

VINN

20

2

Port D

DOR/DORN

DR/DRN

2

GA

B/GB

SLEEP

STAGG

RS

DRTYPE

2

AT84AS004

5431C–BDC–01/06

AT84AS004

3. Functional Description

The AT84AS004 is a 10-bit 2 Gsps ADC combined with a 1:4 demultiplexer (DMUX) allowing to

lower the 11 bit output data stream (10-bit data and one out-of-range bit) by a selectable factor

of 4 or 2. The ADC works in fully differential mode from analog input through to digital outputs.

The ADC should be 50Ω reverse terminated, as close as possible to the EBGA Package input

pin (1 mm maximum). The ADC Clock input is on-chip 100Ω differentially terminated. The output

clock and the output data are LVDS logic compatible, and should be 100Ω differentially

terminated.

The AT84AS004 ADC features two asynchronous resets:

– DRRB, which ensures that the first digitized data corresponds to the first acquisition.

– ASYNCRST, which ensures that the first digitized data will be output on port A of the

DMUX.

The ADC gain can be tuned-in to unity gain by the means of the GA analog control input A Sam-

pling Delay Adjust function (SDA analog control input, activated via the SDAEN signal) may be

used to fine-tune the ADC aperture delay by 120 ps around its center value. The SDA function

may be of interest for interleaving multiple ADCs.The control pin B/GB is provided to select

either a binary or gray data output format.

A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and the DMUX

on the clock path to fine tune the data vs. clock alignment at the interface between the ADC and

the DMUX. This delay can be tuned from -275 to 275 ps around default center value, featuring a

550 ps typical delay tuning range. An extra standalone delay cell is also provided, (controlled via

DACTRL analog control input and activated via DAEN). The tuning range is typically 550 ps.

A pattern generator (PGEB) is integrated in the ADC part for debug or acquisition setup. Simi-

larly, a Built-in Self Test (BIST) is provided for quick debug of the DMUX part. The output

demultiplexing 1:4 or 1:2 ratio can be selected by the means of RS digital control input.

Two modes for the output clock (via DRTYPE) can be selected:

• DR mode: only the output clock rising edge is active, the output clock rate is the same as the

output data rate

• DR/2 mode: both the output clock rising and falling edges are active, the output clock rate is

half the output data rate

The data outputs are available at the output of the AT84AS004 in two different modes:

• Staggered: even and odd bits come out with half a data period delay

• Simultaneous: even and odd bits come out at the same time

A Power reduction mode (SLEEP control input) is provided to reduce the DMUX power

consumption.

The ADC junction temperature monitoring is made possible through the DIODE input by sensing

the voltage drop across 1 diode implemented on the ADC close to chip hot point.

The AT84AS004 is delivered in an Enhanced Ball Grid Array (EBGA), very suitable for applica-

tions subjected to large thermal variations (thanks to its TCE which is similar to FR4 material

TCE).

3

5431C–BDC–01/06

Table 3-1.

Name

Functions Description

Function

V_CCA

Analog 3.3V power supply

VCCA VEEVMINUSD VCCDVPLUSD

V_CCD

Digital 3.3 V power supply

Analog -5V power supply

Output 2.5 V power supply

Output -2.2V power supply

Analog ground

3.3V -5V -2.2V

3.3V 2.5V

20

V_EE

[A0…A9]

2

[A0N…A9N]

AOR/DRAN,

AORN/DRA

2

VIN, VINN

V_PLUSD

CLK, CLKN

DRRB

20

2

[B0…B9]

V_MINUSD

AGND

[B0N…B9N]

BOR/DRBN,

BORN/DRB

ASYNCRST

SDAEN

SDA

20

2

[C0…C9]

GA

[C0N…C9N]

COR/DRCN,

CORN/DRC

DGND

Digital ground

PGEB

AT84AS004

B/GB

CLK, CLKN

VIN, VINN

DRRB

Input clock signals

2

DACTRL, CLKDACTRL

20

2

[D0…D9]

[D0N…D9N]

2

DAI, DAIN

DOR/DRDN,

Analog input data

SLEEP

STAGG

CLKTYPE

RS

DORN/DRD

2

ADC reset

DR, DRN

DAO, DAON

DIODE ADC

DAEN

ASYNCRST

DR/DRN

DMUX asynchronous reset

Output clock signals

BIST

DRTYPE

AGND

DGND

A0…A9

Output data port A

A0N…A9N

Additional output bit port A

AOR/DRAN,

AORN/DRA

or output clock in staggered mode for

port A

Name

Function

B0…B9

Output data port B

DAI, DAIN

Input signals for standalone delay cell

B0N…B9N

Output signals for standalone delay

cell

DAO, DAON

BOR/DRBN,

BORN/DRB

Additional output bit port B or output

clock in staggered mode for Port B

GA

ADC gain adjust

SDAEN

SDA

ADC SDA enable

C0…C9

Output data Port C

C0N…C9N

ADC sampling delay adjust

Additional output bit port C

COR/DRCN,

CORN/DRC

PGEB

ADC pattern generator

or Output clock in staggered mode for

Port C

B/GB

Binary or gray output code selection

Sleep mode selection signal

D0…D9

Output data Port D

D0N…D9N

SLEEP

DOR/DRDN,

DORN/DRD

Additional output bit Port D or output

clock in staggered mode for Port D

Staggered mode selection for data

outputs

STAGG

Input clock type selection signal (to be

connected to V_CCDor left floating)

RS

DMUX ratio selection signal

CLKTYPE

CLKDACTRL

DACTRL

Control signal for clock delay cell

DRTYPE

BIST

Output clock type selection signal

Built-in Self Test

Control signal for standalone delay cell

Diode for die junction temperature

monitoring (ADC)

DAEN

Enable signal for standalone delay cell

DIODE ADC

4

AT84AS004

5431C–BDC–01/06

AT84AS004

4. Specifications

4.1

Absolute Maximum Ratings

Table 4-1.

Parameter

Absolute Maximum Ratings

Symbol

V_CCA

Value

Unit

V

Analog positive supply voltage

Digital positive supply voltage

Analog negative supply voltage

Digital positive supply voltage

Digital negative supply voltage

Maximum difference between

GND to 6

GND to 3.6

GND to -5.5

GND to 3

GND to -3

V_CCD

V

V_EE

V

V_PLUSD

V_MINUSD

V

V_PLUSD- V_MINUSD

5

V

V_PLUSDand V_MINUSD

Analog input voltages

V

_INor V_INN

-1.5 to 1.5

-1 to 1

Maximum difference between

V_INand V_INN

V_INor V_INN

Clock input voltage

V

_CLKor V_CLKN

V

Maximum difference between

V_CLKand V_CLKN

V_CLK- V_CLKN

-1 to 1

Vpp

Control input voltage

Digital input voltage

ADC reset voltage

GA, SDA

SDAEN, B/GB, PGEB, DECB

DRRB

-1 to 0.8

-5 to 0.8

V

-0.3 to V_CCA+0.3

RS, CLKTYPE, DRTYPE, SLEEP,

STAGG, BIST, DAEN

DMUX function input voltage

-0.3 to V_CCD+0.3

V

DMUX asynchronous reset

DMUX input voltage

ASYNCRST

DAI, DAIN

-0.3 to V_CCD+0.3

V

DMUX control voltage

CLKDACTRL, DACTRL

DIODE ADC

T_J

-0.3 to V_CCD+0.3

Maximum input voltage on DIODE

Maximum input current on DIODE

Junction temperature

700

1

mV

mA

°C

135

Notes: 1. Absolute maximum ratings are short term limiting values (referenced to GND = 0 V), to be applied individually, while other

parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability.

2. All integrated circuits have to be handled with appropriate care to avoid damage due to ESD. Damage caused by inappropri-

ate handling or storage could range from performance degradation to complete failure.

5

5431C–BDC–01/06

Table 4-2.

Parameter

Recommended Condition of Use

Symbol

Comments

Recommended Value

Unit

Positive supply voltage

V_CCA

V_CCD

3.3

V

Positive supply voltage

Negative supply voltage

V_EE

-5.0

-2.2

500

V

Positive negative supply voltage

Differential analog input voltage

V_MINUSD

V_IN- V_INN

V

mVpp

50Ω single-ended

(V_INNgrounded through 50Ω)

125

500

mV

Differential clock input level

Vinclk

mVpp

50Ω single-ended clock input

or

Clock input power level

(ground common mode)

P_CLKP_CLKN

GA, SDA

0

dBm

100Ω differential clok

(recommended)

ADC control input voltage

ADC functions

-0.5 to 0.5

V

SDAEN, B/GB,

PGEB, DECB

GND or VEE

ADC reset

DRRB

GND to 3.3V

V

DMUX standalone delay cell inputs

DAI, DAIN

SLEEP, STAGG,

ASYNCRST,

BIST, RS, DAEN,

DRTYPE,

DMUX control inputs

GND to 3.3V

V

CLKDACTRL,

DACTRL

0°C < T_C; T_J< 90°C

-20°C < T_C; T_J< 110°C

Commercial C grade industrial

V grade

Operating temperature range

T_{C ;}T_J

°C

Storage temperature

T_stg

T_J

-65 to 150

125

°C

Maximum junction temperature

6

AT84AS004

5431C–BDC–01/06

AT84AS004

4.2

Electrical Operating Characteristics

• V_CCA= V_CCD= 3.3V, V_EE= -5V, V_MINUSD= -2.2V

• V_INN- V_INN= 1 dBFS ( single-ended driven with V_INNconnected to ground via 50Ω)

• P_CLK= 0 dBm (differential driven)

Table 4-3.

DC Electrical Characteristics at Ambient Temperature and Hot Temperature (T_JMax)

Test

Parameter

Level

Symbol

Min

Typ

Max

Unit

Resolution

10

Bit

Power Requirements

Positive

Supply

-analog

V_CCA

V_CCD

3.15

2.4

3.3

2.5

3.45

2.6

V

-digital

1

Voltages

-digital outputs

V_PLUSD

-analog V_CCA= 3.3V

I_VCCA

I_VCCD

80

100

590

620

470

mA

Positive

Supply

Current

-digital V_CCD= 3.3V (1:2 DMUX)

-digital V_CCD= 3.3V (1:4 DMUX)

-output V_PLUSD= 2.5V

535

565

450

I_VCCD

I_VPLUSD

Negative supply voltage V_EE

Negative supply current

Negative supply voltage

Negative supply current

Power Dissipation (1:2 DMUX)

Analog Inputs

V_EE

I_VEE

-5.25

-2.3

-5

-4.75

660

-2.1

200

7.1

V

mA

V

620

-2.2

190

6.5

1

V_MINUSD

IV_MINUSD

P_D

mA

W

Full-scale input voltage range

V_IN

-125

125

mV

Differential mode 0V common mode voltage

V_INN

Full-scale input voltage range

Single-ended input option

0V common mode voltage

V_IN, V_INN

-250

0

250

mV

4

Analog input power level (50Ω single-ended)

Analog input capacitance (die)

Input leakage current

P_IN

C_IN

I_IN

-2

0.3

10

50

dBm

pF

µA

Ω

R_IN

49

98

51

-single-ended

Input resistance

-differential

R_IN

100

102

Ω

7

5431C–BDC–01/06

Table 4-3.

DC Electrical Characteristics at Ambient Temperature and Hot Temperature (T_JMax) (Continued)

Test

Parameter

Level

Symbol

Min

Typ

Max

Unit

Clock Inputs

Logic common mode

Differential ECL to LVDS

(AC coupling)

compatibility for clock inputs

Clock input common voltage range

(V_CLKor V_CLKN

)

V_CM

-1.2

-4

0

0.3

4

V

(0V common mode)

Clock input power level

(low-phase noise sinewave input) 50Ω

single-ended or 100Ω differential

P_CLK

0

dBm

mV

4

Clock input swing

V_CLK

200

141

320

500

354

(single ended with CLKN = 50Ω to GND)

Clock input swing

V

_CLK, V_CLKN

226

0.3

mV

pF

(differential voltage) on each clock input

Clock input capacitance (die)

C_LK

Clock input resistance

- Single-ended

R_CLK

45

90

50

55

Ω

- Differential ended

100

110

Digital Data Outputs

Logic compatibility

LVDS

50Ω transmission lines, 100Ω (2 × 50Ω)

differential termination)

- Logic low

V_OL

V_OH

–

1.075

1.425

350

1.25

–

V

1

- Logic high

1.25

250

- Differential output

- Common mode

V_ODIFF

V_OCM

500

1.375

mV

V

1.125

1.25

Control Function Inputs

DRRB and ASYNCRST

- Logic low

V

1

4

V_IL

V_IH

0

1.0

3.3

- Logic high

1.6

RS, DRTYPE, SLEEP, STAGG, BIST, DAEN

V_IL

R_IL

V_IH

R_IH

0.5

10

V

Ω

V

Ω

- Logic low

- Logic high

0

2

10 K

Infinite

SDAEN, PGEB, B/GB

- Logic low

1

V_IL

V_IH

V_EE

0

- 3

0

V

- Logic high

-2

DAI, DAIN

- Differential input

- Common mode

V_IDIFF

V_ICM

1

1.25

350

1.6

-

V

100

mV

8

AT84AS004

5431C–BDC–01/06

AT84AS004

Table 4-3.

DC Electrical Characteristics at Ambient Temperature and Hot Temperature (T_JMax) (Continued)

Test

Parameter

Level

Symbol

Min

-0.5

Typ

Max

0.5

Unit

V

GA, SDA

1

CLKDACTRL, DACTRL

DC accuracy

1/3 × V_CCD

2/3 × V_CCD

V

DNLrms

1

4

1

DNLrms

DNL⁺

INL^-

0.2

0.8

-2

0.3

1.5

LSB

Differential non-linearity ⁽¹⁾

Integral non-linearity ⁽¹⁾

Gain central value ⁽²⁾

Gain error drift

-4

INL⁺

2

4

1.05

35

0.95

-10

1

23

ppm/°C

Input offset voltage

10

mV

Note:

1. Histogram testing at Fs = 390 Msps Fin = 100 MHz.

2. This range of gain can be set to 1 thanks to the gain adjust function.

9

5431C–BDC–01/06

Table 4-4.

AC Electrical Characteristics at Ambient Temperature and Hot Temperature (T_JMax)

Test

Parameter

Level

Symbol

Min

Typ

Max

Unit

AC Analog Inputs

Full power input bandwidth ⁽¹⁾

FPBW

SSBW

3

GHz

Small signal input bandwidth (10% full-scale) ⁽¹⁾

3.3

4

Gain flatness ⁽²⁾

BF

- 0.5

dB

Input voltage standing wave ration ⁽³⁾

VSWR

1.1: 1

1.2: 2

AC Performance: Nominal Condition

-1 dBF_Ssingle-ended input mode (unless otherwise specified); 50% clock duty cycle; 0 dBm differential clock (CLK,CLKN)

binary output data format.

Effective Number of Bits

Fs = 1 Gsps

Fs = 1.5 Gsps

Fs = 2 Gsps

Fin = 100 MHz

Fin = 750MHz

Fin = 1000 MHz

Fin = 2 GHz

1

4

7.4

7.3

7.1

8

ENOB

SNR

Bit

7.8

7.5

Signal to Noise Ratio

Fs = 1 Gsps

Fs = 1.5 Gsps

Fs = 2 Gsps

Fin = 100 MHz

Fin = 750MHz

Fin = 1000 MHz

Fin = 2 GHz

1

4

50

49

48

52

51

50

dBc

Total Harmonic Distortion

Fs = 1 Gsps

Fs = 1.5 Gsps

Fs = 2 Gsps

Fin = 100 MHz

1

4

46

45

52

49

Fin = 750MHz

Fin = 1000 MHz

Fin = 2 GHz

|THD|

Spurious Free Dynamic Range

Fs = 1 Gsps

Fs = 1.5 Gsps

Fs = 2 Gsps

Fin = 100 MHz

1

4

50

48

58

55

54

Fin = 750MHz

Fin = 1000 MHz

Fin = 2 GHz

|SFDR|

|IMD3|

dBc

Two-tone Third-order Inter-modulation Distortion

Fs = 2 Gsps

Fin1 = 945 MHz, Fin2 = 955 MHz [-7 dBFS]

Fin1 = 1545 MHz, Fin2 = 1555 MHz [- 7 dBFS]

4

60

dBFS

Note:

1. See ”Definitions of Terms” on page 41.

2. From DC to 1.5 GHz.

3. Specified from DC up to 2.5 GHz input signal. Input VSWR is measured on a soldered device. It assumes an external

50Ω 2Ω controlled impedance line, and a 50Ω driving source impedance (S₁₁≤ 30 dB).

10

AT84AS004

5431C–BDC–01/06

AT84AS004

Table 4-5.

Parameter

Transient and Switching Performances

Test

Level

Symbol

Min

Typ

Max

Unit

Transient Performance

10^-11

Error/

sample

Bit error rate ⁽¹⁾

4

BER

ADC setting time (V_IN-V_INN= 400 mVpp)

Overvoltage recovery time

ADC step response rise/fall time (10 –90%)

Overshoot

4

5

TS

400

ps

%

ORT

500

100

80

4

Ringback

2

%

Switching Performance and Characteristics

Maximum clock frequency ⁽²⁾

Minimum clock frequency ⁽²⁾

Maximum clock pulse width (high)

Minimum clock pulse width (low)

Aperture delay ⁽²⁾

F_SMax

F_{S Min}

TC1

2

Gsps

Msps

ns

150

200

2.5

0.22

TC2

ns

4

TA

160

150

ps

Aperture uncertainty

Jitter

fs rms

ns

DRRB pulse width

1

ASYNCRST pulse width

ns

Output Data

Data Output Delay ⁽³⁾

TOD

T_skew

7.1

ns

ps

Data output delay Skew

400

650

Data pipeline delay

- Synchronized 1:2 ratio

- Synchronized 1:4 ratio

- Staggered 1:2 ratio

- Staggered 1:4 ratio

5.5

7.5

4

Clock

TPD

cycles

4.5/5.5

4.5/5.5/6.5/7.5

Data output rise/fall time (20% –80%)

Output Clock

TR/TF

ps

Output clock delay ⁽³⁾

TDR

6.6

ns

ps

Output clock rise/fall time (20% –80%)

TR/TF

650

600

4

TD2-TD1

TOD-TDR

Output data to output clock propagation

delay

200

500

ps

11

5431C–BDC–01/06

Table 4-5.

Parameter

Transient and Switching Performances (Continued)

Test

Level

Symbol

Min

Typ

Max

Unit

Standalone Delay Cell (DACTRL) and Tunable Delay cell (CLKDACTRL)⁽⁴⁾

Input frequency

Input duty cycle

FMSDA

600

40

MHz

%

4

DCYCSDA

50

60

Propagation delay with

TSDAMIN

1.70

2.00

2.30

ns

CLKDACTRL or DACTRL = V_CCD/3

Propagation delay

4

TSDAMAX

2.1

2.50

550

2.90

600

ns

ps

with CLKDACTRL or DACTRL = 2 × V_CCD/3

Tuning range ⁽⁴⁾

SDARANGE

400

Note:

1. Output error amplitude < 6 LSB. Fs = 2 Gsps T_J= 110°C.

2. See ”Definitions of Terms” on page 41.

3. TOD and TDR propagation times are defined at package input/outputs. They are given for reference only. See ”Definitions of

Terms” on page 41.

4. The delay cell used in both standalone delay cell and input clock path (DR) has a characteristic that is not linear with junction

temperature. The largest tuning range is obtained near ambient temperature.

4.3

Explanation of Test Levels

Level

Comments

1

2

3

4

5

100% production tested at 25°C (for C Temperature range ).

100% production tested at 25°C, and sample tested at specified temperatures (for V and M temperature

ranges).

Sample tested only at specified temperatures

Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified

temperature).

Parameter is a typical value only guaranteed by design only

Note:

Unless otherwise specified:

Only minimum and maximum values are guaranteed (typical values are issued from characterization results).

12

AT84AS004

5431C–BDC–01/06

AT84AS004

4.4

Digital Coding

Differential

Analog Input

Voltage Level

Digital Output

Binary (B/GB = GND or floating)

MSB…LSB out-of-range

GRAY (B/GB = V_EE

)

MSB………..LSB out-of-range

> 250.25 mV

250.25 mV

249.75 mV

125.25 mV

124.75 mV

0.25 mV

>Top end of full-scale + ½ LSB

Top end of full-scale + ½ LSB

Top end of full-scale - ½ LSB

3/4 full-scale + ½ LSB3/4

full-scale - ½ LSB

1 1 1 1 1 1 1 1 1 1

1

0

1

1 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 1

1 0 1 0 0 0 0 0 0 0

1 1 1 0 0 0 0 0 0 0

1 1 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0

0 1 1 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0

1

0

1

1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 0

1 1 0 0 0 0 0 0 0 0

1 0 1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0 0 0

01 1 1 1 1 1 1 1 1

0 1 0 0 0 0 0 0 0 0

0 0 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0

Mid scale + ½ LSB

-0.25 mV

Mid scale - ½ LSB

- 124.75 mV

- 124.25 mV

- 249.75 mV

- 250.25 mV

≤ 250.25 mV

1/4 full-scale + ½ LSB

1/4 full-scale - ½ LSB

Bottom end of full-scale + ½ LSB

Bottom end of full-scale - ½ LSB

< Bottom end of full-scale - ½ LSB

13

5431C–BDC–01/06

5. Characterization Results

5.1

Nominal Conditions

Unless otherwise specified:

• V_CCA= 3.3V, V_CCD= 3.3V, V_EE= -5V, V_PLUSD= 2.5V, V_MINUSD= -2.2V

• T_J= 80°C

• 50% clock duty cycle, binary output data format

• -1 dBFS analog input

5.2

Full Power Input Bandwidth

• Analog input level = -1 dBFS

• Gain flatness at -0.5 dB from DC to 1.5 GHz

Figure 5-1. Full Power Input Bandwidth at -3 dB

0,0

-0,5

-1,0

-1,5

-2,0

-2,5

-3,0

-3,5

-4,0

-4,5

-5,0

-5,5

-6,0

-0.5 dB Gain Flatness

-3 dB

Bandwidth

Fin (MHz)

14

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5431C–BDC–01/06

AT84AS004

5.3

VSWR Versus Input Frequency

Figure 5-2. VSWR Curve for the Analog Input (VIN) and Clock (CLK)

2,60

2,40

2,20

2,00

1,80

1,60

1,40

1,20

1,00

CLK

VIN

0

500

1000

1500

2000

2500

3000

3500

Frequency (MHz)

5.4

Step Response

• Tr measured = 114.8 ps = sqrt (Tr_{PulseGenerator}² + Tr_ADC²)

• Tr_{PulseGenerator}(estimated) = 41 ps

• Actual Tr_ADC= 107 ps

Figure 5-3. Step Response Rise Time (Fs = 2 Gsps, Fin = 1 GHz)

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

100%

90%

10%

0%

-100

-200

0

100

200

300

400

500

600

700

800

900

1000 1100

Time (ps)

15

5431C–BDC–01/06

5.5

Dynamic Performance Versus Sampling Frequency

Figure 5-4. Dynamic Parameters Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)

-20

10

-30

-40

-50

-60

-70

-80

-90

9

8

7

6

5

4

3

2

1

0

Signal dependent and independent SFDR

SFDR without the first 4 Harmonics

1000

1200

1400

1600

1800

2000

1000

1200

1400

1600

1800

2000

Fs (Msps)

90

80

70

60

50

40

30

20

-20

-30

-40

-50

-60

-70

-80

-90

1000

1200

1400

1600

1800

2000

1000

1200

1400

1600

1800

2000

Fs (Msps)

5.6

Dynamic Performance Versus Input Frequency

Figure 5-5. Dynamic Parameters Versus Input Frequency at Fs = 2 Gsps

10

-20

-30

-40

-50

-60

-70

-80

-90

9

8

7

6

0

400

800

1200

Fin (MHz)

1600

2000

0

400

800

1200

Fin (MHz)

1600

2000

60

58

56

54

52

50

48

46

44

42

40

-20

-30

-40

-50

-60

-70

-80

-90

0

400

800

1200

Fin (MHz)

1600

2 000

0

400

800

1200

Fin (MHz)

1600

2000

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5431C–BDC–01/06

AT84AS004

5.7

Signal Spectrum

Figure 5-6. Fs = 2 Gsps, Fin = 998 MHz -1 dBFS Analog Input, 1:4 Demultiplexing Factor, 32

kpoint FFT

20

H1 Fundamental (998 MHz)

ENOB = 7.8

0

-20

SFDR (H2) = - 58 dBFS

-40

F

S/4

-60

-80

-100

-120

-140

0

100

200

300

400

500

600

700

800

900

1000

MHz

Figure 5-7. Fs = 2 Gsps, Fin = 1998 MHz -1 dBFS Analog Input, 1:4 Demultiplexing Factor,

32 kpoint FFT

20

H1 Fundamental image (2 GHz - 1.998 GHz = 2 MHz)

0

ENOB = 7.5

-20

SFDR (H4)

= - 58 dBFS

-40

-60

F

S/4

-80

-100

-120

-140

-160

0

100

200

300

400

500

600

700

800

900

1000

MHz

17

5431C–BDC–01/06

5.8

Dynamic Performance Sensitivity Versus Temperature and Power Supply

Figure 5-8. Dynamic Parameters Versus Junction Temperature at Fs = 2 Gsps, Fin = 998 MHz,

-1 dBFS Analog Input

-20

-30

10

9

-40

-50

-60

-70

-80

-90

8

7

6

5

4

3

2

10

20

30

40

50

60

70

80

90 100 110

10

20

30

40

50

60

70

80

90 100 110

Tj (˚C)

-20

-30

-40

-50

-60

-70

-80

-90

90

80

70

60

50

40

30

20

10

20

30

40

50

60

70

80

90 100 110

10

20

30

40

50

60

70

80

90 100 110

Tj (˚C)

Figure 5-9. Dynamic Parameters at Min., Typ. and Max. Power Supplies, Fs = 2 Gsps, Fin = 998 MHz,

-1 dBFS Analog Input

10

-40

-42

-44

9

-46

-48

8

-50

-52

7

-54

-56

6

-58

-60

5

-62

-64

4

-66

-68

3

-70

2

Min. Power Supplies

Typ. Power Supplies

Max. Power Supplies

Min. Power Supplies Typ. Power Supplies Max. Power Supplies

-40

-42

-44

-46

-48

-50

-52

-54

-56

-58

-60

-62

-64

-66

-68

-70

60

58

56

54

52

50

48

46

44

42

40

Min. Power Supplies Typ. Power Supplies Max. Power Supplies

Note:

Minimum power supplies: V_CC= 3.45,V V_EE= -4.75V

Typical power supplies: V_CC= 3.3V, V_EE= - 5V

Maximum power supplies: V_CC= 3.15V, V_EE= -5.25V

18

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5431C–BDC–01/06

AT84AS004

5.9

Dual Tone Performance

Figure 5-10. Dual Tone Signal Spectrum at Fs = 2 Gsps, Fin1 = 1545 MHz,

Fin2 = 1555 MHz (-7 dBFS)

20

F2 =Fs - Fin2 = 445 MHz

F1 = Fs - Fin1 = 455 MHz

-7 dBFS

0

-20

IMD3

-40

-60

2F1 - Fin2

= 435 MHz

2F2 - F1

= 465 Mz

F1 + F2

= 900 Mz

-80

-100

-120

-140

-160

0

100

200

300

400

500

MHz

600

700

800

900

1000

5.10 NPR Performance

Figure 5-11. Digitizing of 575 MHz Broadband Pattern at 1.4 Gsps, 25 MHz Notch Centered

Around 290 MHz, -12 dBFS Loading Factor

0

NPR = 40.22 dB

-20

25MHz

Input antiliasing

Filter roll-off

25MHz

-40

-60

-80

-100

-120

0

50 100 150 200 250 300 350 400 450 500 550 600 650 700

F(MHz)

19

5431C–BDC–01/06

6. Pin Description

Figure 6-1. EBGA317 Pinout Table (View from Bottom Package)

20

AT84AS004

5431C–BDC–01/06

AT84AS004

Table 6-1.

Symbol

Pin Description

Pin Number

Function

Power Supplies

C17, C18, D17, D18, F3, F4, H3, H4, M3,

M4, P3, P4, R18, T18, U16, U17

DGND

Digital ground

B21, B23, C21, C23, D21, D23, E21, E23,

F21, F23, F26, F27, G25, G26, G27, H25,

H26, J25, J26, K27, N25, P25, R22, R23,

R24, R25, R26, R27, T22, t23, T24, T25,

T26, T27, U22, U23, U24, U25, U26, U27,

V21, V23, V24, V26, V27, W22, W25,

W26, W27

AGND

Analog ground

A24, A26, A27, B24, B26, B27, C24, C26,

C27, D24, D26, D27, E24, E26, F25, L25,

L26, M27, R21, T21, U21,

V_CCA

ADC analog positive power supply

A25, B22, B25, C20, C22, C25, D20, D22,

D25, E20; E22, E25, F20, F22, F24, K25,

K26, L27, M25, M26, N26, N27, R20, T20

V_EE

ADC analog negative power supply

Connect to V_EE

SUB

D14, D15, R17

C4, C5, C6, C7, C9, C11, C13, C14, C15,

C16, C19, D5, D6, D7, D9, D11, D13,

D19, E3, E19, F19, J3, J4, L3, L4, N3, N4,

R3, R4, R19, T6, T7, T9, T11, T13, T14,

T15, T19, U4, U5, U6, U7, U9, U11, U13,

U14, U15

V_PLUSD

ADC and DMUX output power supply

C3, C8, C10, C12, D3, D4, D8, D10, D12,

D16, E4, E17, G3, G4, K3, K4, R16, T3,

T4, T5, T8, T10, T12, T16, T17, U3, U8,

U10, U12

V_CCD

DMUX digital power supply

V_MINUSD

A19, A20, B19, B20, E18, F18, U19, U20

ADC digital negative power supply (-2.2V)

Inputs

ADC clock differential Inputs

ECL/PECL/LVDS compatible

CLK, CLKN

VIN

H27, J27

V25, W24

ADC in-phase analog input (double pin:

one of the two has to be terminated via

50Ω to ground)

ADC Inverted-phase analog input (double

pin: one of the two has to be terminated

via 50Ω to ground)

VINN

V22, W23

Outputs

In-phase digital outputs port A

LVDS compatible

B16, B15, B14, B13, B12, B11, B10, B9,

B8, B7

A0…A9

Inverted-phase digital outputs port A

LVDS compatible

A16, A15, A14, A13, A12, A11, A10, A9,

A8, A7

A0N…A9N

Port additional bit or port A output clock in

staggered mode

AOR/DRAN, AORN/DRA

B6, A6

21

5431C–BDC–01/06

Table 6-1.

Symbol

Pin Description (Continued)

Pin Number

Function

In-phase digital outputs port B

LVDS compatible

B0…B9

B5, B4, B3, B2, C2, D2, E2, F2, G2, H2

Inverted-phase digital outputs port B

LVDS compatible

B0N…B9N

A5, A4, A3, A2, B1, C1, D1, E1, F1, G1

J2, H1

Port B additional bit or port B output clock

in staggered mode

BOR/DRBN, BORN/DRB

C0…C9

In-phase digital outputs port C

LVDS compatible

M2, N2, P2, R2, T2, U2, V1, V2, V3, V4

L1, M1, N1, P1, R1, T1, U1, W2, W3, W4

V5, W5

Inverted-phase digital outputs port C

LVDS compatible

C0N…C9N

Port C additional bit or port V output clock

in staggered mode

COR/DRCN, CORN/DRC

D0…D9

In-phase digital outputs port D

LVDS compatible

V6, V7, V8, V9, V10, V11, V12, V13, V14,

V15

Inverted-phase digital outputs port D

LVDS compatible

W6, W7, W8, W9, W10, W11, W12, W13,

W14, W15

D0N…D9N

Port D additional bit or port D output clock

in staggered mode

DOR/DRDN, DORN/DRD

V16, W16

J1, K2

DR, DRN

Differential output clock LVDS compatible

Control Functions Inputs

ADC data ready reset LVCMOS (3.3V)

compatible

DRRB

P27

B17

DMUX asynchronous reset

-Leave floating or connect to V_CCDfor

normal mode

ASYNCRST

-Connect to ground for reset mode

ADC sampling delay adjust enable

-SDA disabled when left floating or

connected to ground

SDAEN

SDA

P26

E27

A23

-SDA enabled when connected to V_EE

ADC sampling delay adjust

( 0.5V range)

Pattern generator enable

-Leave floating or connect to ground for

normal mode

PGEB

-Connect to V_EEfor test mode

Binary or gray output coding selection

-Leave floating or connect to ground for

binary coding

B/GB

A21

-Connect to V_EEfor gray coding

ADC gain adjust control pin ( 0.5V range)

Connect to V_CCD

GA

W21

V18

CLKTYPE

22

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5431C–BDC–01/06

AT84AS004

Table 6-1.

Symbol

Pin Description (Continued)

Pin Number

Function

DMUX SLEEP mode Enable

-leave floating or connect to V_CCDfor

normal mode

SLEEP

STAGG

DRTYPE

RS

A18

-connect to ground for SLEEP mode

DMUX staggered mode enable

-leave floating or connect to V_CCDfor

normal mode

A17

K1

-connect to ground for STAGG mode

DMUX output clock mode selection

-connect to ground for DR/2 type

-leave floating or connect to V_CCDfor

DR type

DMUX Ratio mode selection

-connect to ground for 1:2 ratio

L2

-leave floating or connect to V_CCDfor

1:4 ratio

DMUX BIST mode

-leave floating or connect to V_CCDfor

normal mode

BIST

V17

-connect to ground for BIST mode

DMUX clock delay control

(from 1/3 × V_CCDto 2/3 × V_CCD

CLKDACTRL

DACTRL

U18

)

Standalone delay cell control (from 1/3 ×

W18

V_CCDto 2/3 × V_CCD

)

Standalone delay cell enable

-delay cell disabled when left floating or

connected to V_CCD

DAEN

W17

-delay cell enabled when connected to

ground

Standalone delay cell differential inputs

LVDS compatible

DAI, DAIN

W19, V19

W20, V20

Control Functions Outputs

Standalone delay cell differential outputs

LVDS compatible

DAO, DAON

DIODE ADC

NC

A22

ADC die junction temperature monitoring

No connect (leave this pin floating)

A1, B18, W1

23

5431C–BDC–01/06

7. Main Features

7.1

Reset

There are two reset signals available: DRRB and ASYNCRST. DRRB is active low while ASYN-

CRST is active high. These reset signals are required to start the device properly. It is

recommended to apply both reset signals simultaneously. Please refer to the Application Sec-

tion for more information on how to implement the reset functions. In the case of multiple

channels, it is recommended to hold the input clock signal low during reset (as described in

Figure 7-1) to ensure synchronization of the channels.

The DRRB/ASYNCRST signal frequency should be 200 MHz maximum. The reset pulse should

be 1 ns minimum.

Figure 7-1. Asynchronous Reset Timing Diagram, 1:2 Mode, Simultaneous Mode (Principle of Operation)

T

= 160 ps

amb

1 ns min

TPD: 5.5 cycles

1 cycle

TOD

T

skew

N

N + 2

T

skew

N + 1

N + 3

TDR

TD1 TD2

24

AT84AS004

5431C–BDC–01/06

AT84AS004

Figure 7-2. Asynchronous Reset Timing Diagram, 1:4 Mode, Simultaneous Mode (Principle of Operation)

T

= 160 ps

amb

VIN

CLK

1 ns min

DRRB

TPD: 7.5 cycles

2 cycles

ASYNCRST

TOD

Tskew

A0..A9

B0..B9

C0..C9

D0..D9

N

Tskew

N + 1

N + 2

N + 3

TDR

DR (DR mode)

DR (DR/2 mode)

TD1

TD2

Note:

1. TPD time is the delay between the first raising edge after the reset signal and before the TOD

or TDR delay. This time is a number of clock cycle.

2. Definition of TOD: it is the time between the falling edge and the next point of change of data

3. Definition of TDR: it is the time between the falling edge and the next point of change of data

ready.

4. TOD - TDR is always lower to 600 ps over temperature and power supply

5. TD1 = 2 clock cycles + TOD - TDR.

6. TD2 = 2 clock cycles + TDR - TOD With TOD = 6.2 ns. This delay is long due to the several

delay lines in the DMUX.

25

5431C–BDC–01/06

7.2

Control Signal Settings

The SLEEP, RS, DAEN, STAGG, BIST and DRTYPE control signals use the same static buffer.

ASYNCRST is activated on logic high (tied/switched to V_CCD= 3.3V, or 10 kΩ to ground, or left

floating) and deactivated on logic low (grounded).

SLEEP, DAEN, STAGG, BIST are activated on logic low (10Ω grounded), and deactivated on

logic high (10 kΩ to ground, or tied to V_CCD= 3.3V, or left floating). This is illustrated in Figure

7-3.

Figure 7-3. Control Signal Setting

Not

Control signal

connected

10

KΩ

10Ω

GND

Low level

(‘0’)

GND

(‘1’)

High level

26

AT84AS004

5431C–BDC–01/06

AT84AS004

Table 7-1.

Function

DMUX Mode Settings - Summary

Logic Level

Electrical Level

10Ω to ground

10 kΩ to ground

N/C

Description

0

BIST

1

Normal conversion

0

Power reduction mode (the outputs

are fixed at an arbitrary LVDS level)

10Ω to ground

SLEEP

10Ω to ground

N/C

1

Normal conversion

Staggered mode

Simultaneous mode

Standalone delay adjust activated

Standalone delay adjust disabled

1:2 ratio

0

1

10Ω to ground

10 kΩ to ground

N/C

STAGG

DAEN

0

1

10Ω to ground

10 kΩ to ground

N/C

0

1

10Ω to ground

10 kΩ to ground

N/C

RS

1:4 ratio

0

1

10Ω to ground

10 kΩ to ground

N/C

Normal conversion

Reset

ASYNCRST

DRTYPE

0

1

10Ω to ground

10 kΩ to ground

N/C

DR/2 mode

DR mode

27

5431C–BDC–01/06

7.3

Programmable DMUX Ratio

The demultiplexer ratio is programmable thanks to the RS ratio selection signal:

RS

0

DMUX Ratio

1:2

1:4

1

Figure 7-4. DMUX in 1:2 Ratio

Input Words:

Output Words:

1, 2, 3, 4, 5, 6, 7, 8…

1:2

Port A

Port B

Port C

Port D

1

2

3

4

5

…

Not Used

Figure 7-5. DMUX in 1:4 Ratio

Input Words:

Output Words:

1, 2, 3, 4, 5, 6, 7, 8…

1:4

Port A

Port B

Port C

Port D

1

2

3

4

5

6

7

8

9

…

7.4

Output Mode (STAGG)

Two output mode are provided:

• Staggered: the output data come out of the DMUX the one after the other;

• Simultaneous: the output data come out of the DMUX at the same time.

In staggered mode, the output clock for each port is provided by the DRA, DRAN, DRB, DRBN,

DRC, DRCN and DRD, DRDN signals which corresponds respectively to the AORN, AOR,

BRON, BOR, CORN, COR, DORN and DOR.

The simultaneous mode is the default mode (STAGG left floating of at logic 1).

The staggered mode is activated by the means of the STAGG input (active low).

28

AT84AS004

5431C–BDC–01/06

AT84AS004

Figure 7-6. Simultaneous Mode in 1:4 Ratio (STAGG = 1)

DR

(in DR mode)

DR

(in DR/2 mode)

Data Out

Port A

N

N + 4

N + 5

Data Out

Port B

N + 1

N + 2

N + 3

Data Out

Port C

N + 6

N + 7

Data Out

Port D

Figure 7-7. Staggered Mode in 1:2 Ratio (STAGG = 0)

Data Out

N

N + 2

Port A

Data Out

Port B

N - 1

N + 1

N + 3

DRA (AORN)

in DR mode

DRA (AORN)

in DR/2 mode

DRB

in DR mode

DRB (BORN)

in DR/2 mode

DR

(in DR mode)

DR

(in DR/2 mode)

29

5431C–BDC–01/06

Figure 7-8. Staggered Mode in 1:4 Ratio (STAGG = 0)

Data Out Port A

N

N + 4

DRA (AORN)

in DR mode

DRA (AORN)

in DR/2 mode

Data Out Port B

N + 1

N + 5

DRB (BORN)

in DR mode

DRB (BORN)

in DR/2 mode

Data Out Port C

N

2

N + 2

N + 6

-

DRC (CORN

(in DR mode)

DRC (CORN

(in DR/2 mode)

Data Out Port D

N - 1

N + 3

DRD (DORN)

in DR mode

DRD (DORN)

in DR/2 mode

DR

in DR mode

DR

in DR/2 mode

7.5

Additional Bit

In simultaneous output mode:

The (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) and

(DOR/DRDN, DORN/DRD) signals are used to process the out-of-range bit from the ADC as the

ADC output data.

In 1:2 ratio, (AOR, AORN) and (BOR, BORN) will output this signal at half its initial speed.

In 1:4 ratio, (AOR, AORN), (BOR, BORN), (COR, CORN) and (DOR, DORN) will output this sig-

nal at ¼ of its initial speed.

In Staggered output mode: (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB),

(COR/DRCN, CORN/DRC) and (DOR/DRDN, DORN/DRD) will output a Data Ready signal for

each ports, centered on the corresponding data.

30

AT84AS004

5431C–BDC–01/06

AT84AS004

The frequency of the (DRA, DRAN), (DRB, DRBN), (DRC, DRCN) and (DRD, DRDN) depends

on the DRTYPE mode (same as data in DR mode, half in DR/2 mode).

In 1:2 ratio, DR/DRN and DRB/DRBN are the same.

In 1:4 ratio, DR/DRN and DRD/DRDN are the same.

7.6

Output Clock Type Selection

Two modes for the output clock type can be chosen:

• DR mode: only the output clock rising edge is active, the output clock rate is the same as the

output data rate;

• DR/2 mode: both the output clock rising and falling edges are active, the output clock rate is

half the output data rate.

This is illustrated in Figure 7-9 and Figure 7-10.

Figure 7-9. DR Mode

DR

Data Out

Figure 7-10. DR/2 Mode

DR

Data Out

Table 7-2.

Table 8. DMUX Output Clock Type Selection Settings

DRTYPE

DMUX Output Clock Type

1

0

DR

DR/2

When DRTYPE is left floating, the default mode is DR.

7.7

7.8

Power Reduction Mode (SLEEP)

The power reduction (SLEEP) mode allows the user to reduce the power consumption of the

device (demultiplexing part in Sleep mode). In this mode, the device's consumption is reduced to

5W. The Power reduction mode is active when SLEEP is low. The device is in normal mode

when SLEEP is high.

Standalone Delay Cell

A standalone delay cell is provided to allow the user to add a delay on the DAI/DAIN differential

input signal. The delay is controlled via the DACTRL. The tuning range is about 550 ps varying

from V_CCD/ 3 to (2 × V_CCD) / 3. This function results in a delayed output signal: DAO/DAON. The

DAI/DAIN and DAO/DAON are LVDS signals.

31

5431C–BDC–01/06

Figure 7-11. Standalone Delay Cell Block Diagram

2

Delay

(550 ps)

2

DAO/DAON

DAI/DAIN

DACTRL

7.9

Clock input Delay Cell

A delay cell is provided to allow the user to tune the delay between clock and data at the

DEMUX input. The delay is controlled via the CLKDACTRL. It ranges from -275 ps to 275 ps for

CLKDACTRL varying from V_CCD/ 3 to (2 × V_CCD) / 3.

This function results in a delayed internal clock signal.

Figure 7-12. Standalone Delay Cell Block Diagram

Delay

2

Internal clock

signal

(-275 to 275 ps)

CLK/CLKN

CLKDACTRL

7.10 Built-In Self Test

The Built-in Self Test allows to test rapidly the DMUX block of the device. It is activated via the

BIST bit (active low). When this signal is left floating, the BIST is inactive.

When in BIST mode, a clock must be applied to the device, which can be set to 1:2 or 1:4 mode.

The output clock mode DRTYPE can be either DR or DR/2. In the BIST mode, all the bits are

either all at low or high level (even and odd bits are in phase opposition) and transition every

new cycle. For proper operation of the Built-In Self Test, V_CCDshould be set to 3.3V minimum.

7.11 ADC Die Junction Temperature Monitoring

A die junction temperature measurement setting is available, for maximum junction temperature

monitoring (hot point measurement). The measurement method consists in forcing a 1 mA cur-

rent into a diode mounted transistor and sensing the voltage across the DIODE pin and the

closest available ground pin. The measurement setup is described in Figure 7-13 on page 33.

32

AT84AS004

5431C–BDC–01/06

AT84AS004

Figure 7-13. ADC Diode for Die Junction Temperature Monitoring Setup (10 in parallel of 3)

DIODE

10

1 mA

protection

diodes

AGND

Protection

Diodes

Caution:

Respect the current source polarity. In all cases, make sure that the maximum voltage compli-

ance of the current source is limited to a maximum of 1V or use a resistor mounted in series with

the current source to avoid damages, which may occur to the transistor device (this may occur

for instance if the current source is connected in reverse).

The diode VBE forward voltage versus junction temperature (in steady state conditions) charac-

teristic is given in Figure 7-14. The forward voltage drop, (V_DIODE) across diode component,

versus junction temperature, (including chip parasitic resistance), is given below (I_DIODE= 1 mA).

33

5431C–BDC–01/06

Figure 7-14. ADC Diode Characteristic (I = 1 mA)

Junction temperature Versus Diode Voltage for I= 1 mA

950

940

930

920

910

900

890

880

870

860

850

840

830

820

810

800

790

780

770

760

750

740

-20

-10

0

10

20

30

40

50

60

70

80

90

100

110

120

130

Jonction temperature (˚C)

Note:

The operating die junction temperature must be kept below 125°C, to ensure long term device

reliability.

7.12 Pattern Generator Function

The Pattern Generator function (enabled by connecting pin PGEB to V_EE= -5V) allows to check

rapidly the ADC operation thanks to a checker board pattern delivered internally to the ADC.

Each output bit of the ADC should toggle from 0 to 1 successively. At the AT84AS004 output, all

bits of each port are all 1 or all 0 and transition every cycle.

7.13 ADC Gain Control

The ADC gain is adjustable by the means of the pin W21 of the EBGA package.

The gain adjust transfer function is given below:

1.30

1.20

Typical

1.10

1.00

Min

0.90

0.80

0.70

0.60

0.50

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

V

Gain Adjust Voltage (V)

GA

34

AT84AS004

5431C–BDC–01/06

AT84AS004

7.14 Sampling Delay Adjust

Sampling delay adjust (SDA pin) allows to fine tune the sampling ADC aperture delay TAD

around its nominal value (160ps). This functionality is enabled thanks to the SDAEN signal,

which is active when tied to V_EEand inactive when tied to GND.

This feature is particularly interesting for interleaving ADCs to increase sampling rate.The varia-

tion of the delay around its nominal value as a function of the SDA voltage is shown in the

following graph (simulation result):

Figure 7-15. Typical Tuning Range is 120 ps for Applied Control Voltage Varying Between

-

0.5V to 0.5V on SDA pin.

400 p

Delay in the Variable Delay Cell at 60 C

300 p

200 p

100 p

-500 m

-400 m

-300 m

-200 m

-100 m

0.00

100 m

200 m

300 m

400 m

500 m

SDA Voltage

Note:

The variation of the delay in function of the temperature is negligible.

35

5431C–BDC–01/06

8. Equivalent Input/Output Schematics

8.1

Equivalent Analog Input Circuit and ESD Protection

Figure 8-1. AT8AS004 Analog Input Buffer Schematic (VIN/VINN)

VEE = - 5V

Double

Pad

260fF

ESD

50Ω

120fF

VIN

GND

1mA

50Ω Controlled

Transmission Lines

(Bonding + Package + Ball)

Package

Pins

Die Double Pads

50Ω Controlled

Transmission Lines

(Bonding + Package + Ball)

1mA

VINN

50Ω

ESD

120f

F

GND

VEE = - 5V

Note:

External 50Ω reverse termination are required.

8.2

Equivalent Clock Input Circuit and ESD Protection

Figure 8-2. AT84AS004 Clock Input Buffer Schematic (CLK/CLKN)

150Ω

CLK

400 µA

Double Pad

ESD

260fF

120fF

50Ω

VEE = -5V

40pF

GND

ESD

215fF

Double Pad

260fF

VEE =

-5V

50Ω

400 µA

CLKB

ESD

120fF

Double Pad

260fP

150Ω

VEE = -5V

Note:

The 100Ω termination mid point is on chip and AC coupled to ground through a 40 pF capacitor.

36

AT84AS004

5431C–BDC–01/06

AT84AS004

8.3

Equivalent Data/Clock Output Buffer Circuit and ESD Protection

Figure 8-3. AT84AS004 Data (Ai/AiN…Di/DiN), Clock (DR/DRN) and DAO/DAON Output

Buffer Schematic

VPLUSD (2.5V 5%)

200

vccdiode

ESD:

vccdiode

ESD:

vccdiode

C = 435 fF C = 435 fF

701

out

361

outn

ESD:

gnddiode

C = 272 fF

gnddiode

C = 272 fF

gnddiode

50.0

1.1K

1.4K

DGND (0V)

SUBST (-5V)

8.4

Standalone Delay Cell Data Input (DAI/DAIN) Buffer Circuit and ESD Protection

Figure 8-4. AT84AS004 Standalone Delay Cell Input DAI/DAIN Buffer Schematic

VCCD (3.3V 5%)

2.00K

npn

ESD:

vccdiode

C = 435 fF

ESD:

vccdiode

C = 435 fF

npn

in

49.9

1.25V 0.175V

49.9

inb

ESD:

gnddiode gnddiode

C = 272fF C = 272fF

4.00k

5.00p

DGND (0V)

SUBST (-5V)

37

5431C–BDC–01/06

8.5

Delay Cell (DACTRL/DACTRLN and CLKCTRL/CLKCTRLN) Control Input

Schematic and ESD Protection

Figure 8-5. AT84AS004 Delay Cell Control Input DACTRL/DACTRLN and CLKCTRL/CLKC-

TRLN Buffer Schematic

VCCD (3.3V 5%)

2.00K

ESD:

vccdiode

C = 435 fF

10.0K

2.00K

in

698

ESD:

gnddiode

C = 272 fF

600 µa

10.0K

2.00K

DGND (0V)

SUBST

8.6

DRRB Equivalent Input Schematic and ESD Protection

Figure 8-6. AT84AS004 DRRB Reset Input Buffer Schematic

VCC = 3.3V

1.4V

VCC = 3.3V

GND

8 K

Ω

DRRB

-2.6V

200

Ω

130 fF

Ω

10 K

5 KΩ

VEE =-5V GND

GND

VEE =-5V

38

AT84AS004

5431C–BDC–01/06

AT84AS004

8.7

ASYNCRST Equivalent Input Schematic and ESD Protection

Figure 8-7. AT84AS004 Asynchronous Reset ASYNCRST Buffer Schematic

VCCD (3.3V 5%)

4.00K

ESD:

vccdiode

C = 435 fF

12.7K

399

25.0K

in

ESD:

gnddiode

C = 272 fF

75 ua

9.32K

4.00K 4.00K

DGND (0V)

SUBST (-5V)

8.8

ADC Gain Adjust Equivalent Input Circuits and ESD Protection

Figure 8-8. AT84AS004 Gain Adjust Control Input Buffer Schematic (GA)

VCC = 5 V

ESD

65fF

0.9V

0V

1

kΩ

GA

20Ω

10p

PAD

130fF

ESD

75fF

F

VEE = -5V

GND

µ

100 A

µ

A

100

VEE = -5V

39

5431C–BDC–01/06

8.9

B/GB and PGEB Equivalent Input Schematics and ESD Protection

Figure 8-9. AT84AS004 B/GB and PGEB Control Buffer Schematic

GND

2kΩ

1kΩ

ESD

65fF

5kΩ

-1.3V

B/GB

ESD

75fF

µ

250 A

PAD

130fF

250 A

VEE = -5V

8.10 Control Signals Input Buffers and ESD Protection

Figure 8-10. AT84AS004 Control Signals Buffer Schematic (RS, DRTYPE, BIST, SLEEP,

STAGG, RS, DAEN)

VCCD (3.3V 5%)

10.0K

4.00K

1.2K

ESD:

vccdiode

C = 435 fF

in

8K

10.0K

16.00K

10Ω = 0

ESD:

10 KΩ = 1

gnddiode

C = 272 fF

DGND (0V)

SUBST (-5V)

40

AT84AS004

5431C–BDC–01/06

AT84AS004

9. Definitions of Terms

Maximum Sampling

Frequency

(Fs max)

(Fs min)

Sampling frequency for which ENOB < 6bit.s

Sampling frequency for which the ADC Gain has fallen by 0.5 dB with

respect to the gain reference value. Performances are not guaranteed

below this frequency.

Minimum Sampling

frequency

Probability to exceed a specified error threshold for a sample at

maximum specified sampling rate. An error code is a code that differs by

more than 4 LSB from the correct code.

(BER)

Bit Error Rate

Analog input frequency at which the fundamental component in the

digitally reconstructed output waveform has fallen by 3 dB with respect

to its low frequency value (determined by FFT analysis) for input at full-

scale -1 dB (-1 dBFS).

(FPBW)

Full Power Input Bandwidth

Analog input frequency at which the fundamental component in the

digitally reconstructed output waveform has fallen by 3 dB with respect

to its low frequency value (determined by FFT analysis) for input at full-

scale -10 dB (- 10 dBFS).

Small Signal Input

Bandwidth

(SSBW)

Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below

full-scale (- 1 dBFS), to the RMS sum of all other spectral components,

including the harmonics except DC.

Signal to Noise and

Distortion Ratio

(SINAD)

(SNR)

Ratio expressed in dB of the RMS signal amplitude, set to 1dB below

full-scale, to the RMS sum of all other spectral components excluding

the twenty five first harmonics.

Signal to Noise Ratio

Ratio expressed in dB of the RMS sum of the first twenty five harmonic

components, to the RMS input signal amplitude, set at 1 dB below full-

scale. It may be reported in dB (i.e, related to converter -1 dB full-scale),

or in dBc (i.e, related to input signal level).

(THD)

Total Harmonic Distortion

Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below

full-scale, to the RMS value of the highest spectral component (peak

spurious spectral component). The peak spurious component may or

may not be a harmonic. It may be reported in dB (i.e., related to

converter -1 dB full-scale), or in dBc (i.e, related to input signal level ).

Spurious Free Dynamic

Range

(SFDR)

(ENOB)

(DNL)

Where A is the actual

A

-------------

SINAD – 1⋅76 + 20 log

input amplitude and V is

the full-scale range of the

ADC under test.

FS ⁄ 2

ENOB = -----------------------------------------------------------------------------

Effective Number of Bits

Differential Non-Linearity

6⋅02

The Differential Non Linearity for an output code i is the difference

between the measured step size of code i and the ideal LSB step size.

DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i).

DNL error specification of less than 1 LSB guarantees that there are no

missing output codes and that the transfer function is monotonic.

The Integral Non Linearity for an output code i is the difference between

the measured input voltage at which the transition occurs and the ideal

value of this transition. INL (i) is expressed in LSBs, and is the maximum

value of all INL (i).

(INL)

(TA)

Integral Non-Linearity

Aperture Delay

Delay between the rising edge of the differential clock inputs

(CLK,CLKB) (zero crossing point), and the time at which (VIN,VINB) is

sampled.

41

5431C–BDC–01/06

Sample to sample variation in aperture delay. The voltage error due to

jitter depends on the slew rate of the signal at the sampling point.

(JITTER)

(TS)

Aperture Uncertainty

Settling Time

Time delay to achieve 0.2 % accuracy at the converter output when a

80% full-scale step function is applied to the differential analog input.

Over Voltage Recovery

Time

Time to recover 0.2% accuracy at the output, after a 150 % full-scale

step applied on the input is reduced to midscale.

(ORT)

Delay from the rising edge of the differential clock inputs (CLK,CLKB)

(zero crossing point) to the next point of change in the differential output

data (zero crossing) with specified load.

(TOD)

(TDR)

Digital Data Output Delay

Data Ready Output Delay

Delay from the falling edge of the differential clock inputs (CLK,CLKB)

(zero crossing point) to the next point of change in the differential output

data (zero crossing) with specified load.

Time Delay from Data

Transition to Data Ready

General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 =

1 encoding clock period.

(TD1)

(TD2)

(TC)

Time delay from Data

Ready to Data

General expression is TD2 = TC2 + TDR - TOD with TC = TC1 + TC2 =

1 encoding clock period.

TC1 = Minimum clock pulse width (high) TC = TC1 + TC2TC2 =

minimum clock pulse width (low).

Encoding Clock Period

Pipeline Delay

Number of clock cycles between the sampling edge of an input data and

the associated output data being made available, (not taking in account

the TOD).

(TPD)

Time delay for the output DATA signals to rise from 20% to 80% of delta

between low level and high level.

(TR)

Rise Time

Fall Time

Time delay for the output DATA signals to fall from 20% to 80% of delta

between low level and high level.

(TF)

Power Supply Rejection

Ratio

(PSRR)

Ratio of input offset variation to a change in power supply voltage.

When the input signal is larger than the upper bound of the ADC input

range, the output code is identical to the maximum code and the out-of-

range bit is set to logic one. When the input signal is smaller than the

lower bound of the ADC input range, the output code is identical to the

minimum code, and the out-of-range bit is set to logic one. (It is

assumed that the input signal amplitude remains within the absolute

maximum ratings).

(NRZ)

Non Return to Zero

The two tones inter modulation distortion (IMD) rejection is the ratio of

either input tone to the worst third order intermediation products.

(IMD)

Inter modulation distortion

Noise Power Ratio

The NPR is measured to characterize the ADC performance in

response to broad bandwidth signals. When applying a notch-filtered

broadband white-noise signal as the input to the ADC under test, the

Noise Power Ratio is defined as the ratio of the average out-of-notch to

the average in-notch power spectral density magnitudes for the FFT

spectrum of the ADC output sample test.

(NPR)

The VSWR corresponds to the ADC input insertion loss due to input

power reflection. For example a VSWR of 1.2 corresponds to a 20 dB

return loss (i.e.. 99% power transmitted and 1% reflected).

Voltage Standing Wave

Ratio

(VSWR)

42

AT84AS004

5431C–BDC–01/06

AT84AS004

10. Thermal and Moisture Characteristics

As there is no JEDEC standard definition for the thermal resistance applied to a multi-die device,

only the thermal resistance for each die (ADC block powered on only or DMUX block powered

on only) is provided. For easy understanding of the thermal behavior of the device, thermal data

with both devices powered on are however provided.

All results were computed with ANSYS thermal simulation tool and with the following

assumptions:

• Half geometry simulation

• DC heating zone = 1.9 × 1.9 mm²

• MUX heating 4.0 × 4.0 mm²

• No air, pure conduction, no radiation

10.1 Thermal Resistance from Junction To Bottom of Balls

When both blocks are powered on, the thermal simulation results in:

• Temperature at the center of the ADC block = 32.9°C

• Temperature at the center of the DMUX block = 13.6°C

When each block is powered on at a time, the resulting thermal resistance from junction to bot-

tom of balls is:

• Rth Junction-bottom of balls (ADC block on only) = 7°C/W

• Rth Junction-bottom of balls (DMUX block on only) = 3.9°C/W

10.2 Thermal Resistance from Junction To Top of Case

When both blocks are powered on, the resulting thermal resistance from junction to top of

case is:

• Temperature at the center of the ADC block = 18.5°C

• Temperature at the center of the DMUX block = 4.1°C

When each block is powered on at a time, the resulting thermal resistance from junction to top of

case is:

• Rth Junction- top of case (ADC block on only) = 4.1°C/W

• Rth Junction- top of case (DMUX block on only) = 1.5°C/W

10.3 Thermal Resistance from Junction To Board

When both blocks are powered on, the resulting thermal resistance from junction to board is:

• Temperature at the center of the ADC block = 57.6°C

• Temperature at the center of the DMUX block = 37.3°C

When each block is powered on at a time, the resulting thermal resistance from junction to board

is:

• Rth Junction- board (ADC block on only) = 8°C/W

• Rth Junction- board (DMUX block on only) = 4.9°C/W

Note:

Assumed board size = 53 × 43 mm²

43

5431C–BDC–01/06

10.4 Thermal Resistance from Junction To Ambient

When both blocks are powered on, the resulting thermal resistance from junction to ambient is:

• Temperature at the center of the ADC block = 106°C

• Temperature at the center of the DMUX block = 85.3°C

When each block is powered on at a time, the resulting thermal resistance from junction to ambi-

ent is:

• Rth Junction- ambient (ADC block on only) = 17.1°C/W

• Rth Junction- ambient (DMUX block on only) = 13.9°C/W

10.5 Thermal Management Recommendations

In still air and 25°C ambient temperature conditions, the maximum temperature of 106°C + 25°C

= 131°C is reached for the ADC block. It is consequently necessary to manage the heat from the

AT84AS004 very carefully to avoid permanent damages of the device due to over temperature

operation.

In no air cooling conditions, an external heatsink must be placed on top of package. An electrical

isolation may be necessary as the top of the package is at V_EE= -5V potential.

It is advised to use an external heatsink with intrinsic thermal resistance better than 4°C/Watt

when using air at room temperature 20~25°C.At 60°C, the external heatsink should have an

intrinsic thermal resistance better than 3°C/Watt. Figure 10-1 provides the outlines of the heat

sink used on the AT84AS004-EB evaluation board.

Figure 10-1. AT84AS004-EB Evaluation Board Heat Sink Outlines

50.4 x 50.7 x 16.5 heat sink

60 x

52

26

13 x

Note:

All units are in mm

44

AT84AS004

5431C–BDC–01/06

AT84AS004

10.6 Moisture Characteristics

This device is sensitive to the moisture (MSL3 according to JEDEC standard).

Shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH).

After this bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow, or

equivalent processing (peak package body temperature 220°C) must be:

– mounted within 168 hours at factory conditions of ≤30°C/60% RH, or

– stored at ≤20% RH

Devices require baking, before mounting, if Humidity Indicator is >20% when read at 23°C

5°C.

If baking is required, devices may be baked for:

– 192 hours at 40°C + 5°C/-0°C and <5% RH for low temperature device containers, or

– 24 hours at 125°C 5°C for high-temperature device containers.

11. Applying the AT84AS004

11.1 Bypassing, Decoupling and Grounding

All power supplies have to be decoupled to ground as close as possible to the signal accesses

to the board by 1 µF in parallel to 100 nF.

Figure 11-1. AT84AS004 Power supplies Decoupling and grounding Scheme

Power Supply

Plane

Supply Access

External Power

nF

100

1

µF

(V_CCD, V_CCA, V

,

EE

V

or V_MINUSD

)

PLUSD

Ground

Note:

V_CCDand V_CCAplanes should be separated but the two power supplies can be reunited by a strap

on the board.

Each group of neighboring power supply pins attributed to the same value should be bypassed

with at least one pair of 100 pF in parallel to 10 nF capacitors. These capacitors should be

placed as close as possible to the power supply package pins.

The minimum required pairs of capacitors by power supply type is:

– 10 for V_CCA

– 15 for V_CCD

– 11 for V_EE

– 22 for V_PLUSD

– 3 for V_MINUSD

45

5431C–BDC–01/06

Figure 11-2. AT84AS004 Power Supplies Bypassing Scheme

AT84AS004

3

V_CCD

pF

100

V

CCA

V_CCA

pF

100

X 15

X 22

X 3

(min)

10

nF

X 10

(min)

DGN

D

nF

10

AGND

V

D

PLUS

V

DGN

V_MINU

D

EE

X 11

pF

100

SD

AGND

(min)

nF

10

DGN

D

11.2 Analog Input Implementation

Two pins are available for each positive (VIN) and negative (VINN) inputs. It is necessary to ter-

minate one of each input pair by 50Ω to ground as close as possible to the EBGA package pins.

This is illustrated in Figure 11-3.

Figure 11-3. AT84AS004 Analog Input Reverse Termination Scheme

AT84AS004

Ω

50

VIN (V25)

GND

VIN (W24)

Differential or

50

Ω Lines

single-ended signal

VINN (W23)

50Ω

VINN (V22)

GND

The analog input of the AT84AS004 device can be indifferently entered in single-ended or differ-

ential mode.

46

AT84AS004

5431C–BDC–01/06

AT84AS004

Figure 11-4. AT84AS004 Analog Input Termination Scheme (Single-ended)

004

AT84AS

50Ω

Single ended signal

VIN (V25)

VIN (W24)

500 mVp-p

Full-scale amplitude =

on

GND

Centered

mV

50Ω Line

0V common mode

VI

N

250

VINN

(W23)

VINN

50

Ω

VINN (V22)

mV

-250

50Ω

GND

Note:

The two 50Ω terminations connected to the two negative inputs (VINN) can be replaced by one

25Ω resistor to ground.

Figure 11-5. AT84AS004 Analog Input Termination Scheme (Differential)

AT84AS004

50Ω

Differential signal

VIN (V25)

VIN (W24)

500

mVp-p

0V common mode

VIN

Full-scale amplitude =

Centered on

GND

50Ω Lines

VINN

125 mV

VINN (W23)

VINN (V22)

-125 mV

50Ω

GND

11.3 Clock Input Implementation

The AT84AS004 clock inputs (CLK/CLKN) are designed for either single-ended or differential

operation but it is recommended to drive the clock differentially to optimize the device's perfor-

mances at high frequencies. No external 50Ω termination are required for the clock inputs

(CLK/CLKN) as they are already on-chip terminated by two 50Ω resistors connected to ground

via an on-chip 40 pF capacitor.

The AT84AS004 input clock can be used in either DC coupled (0V common mode) or AC cou-

pled (ECL, LVDS for example) mode. It is recommended to use a differential sinewave signal

(0 dBm or 894 mVp-p differential) centered on 0V common mode to drive the clock signals. A

balun (with Sqrt(2) ratio) may then be necessary to convert the single-ended clock signal to a dif-

ferential clock signal.

Note:

If the clock frequency is fixed, then it is recommended to narrow-band filter the clock signal in

order to minimize its jitter and the integrated noise over the band of interest.

47

5431C–BDC–01/06

Figure 11-6. AT84AS004 Clock Input Termination Scheme (Single-ended)

AT84AS004

Single ended signal

-

632 mVp-p

Full-scale amplitude = 0 dBm =

CLK (H27)

common mode

Centered on 0V

50Ω Line

CLK

316

mV

CLKN

(J27)

CLKN

50Ω

-316

GND

Figure 11-7. AT84AS004 Clock Input Recommended Termination Scheme (Differential)

AT84AS004

Differential signal

Full-scale amplitude = 0 dBm = 894 mVp - p

CLK (H27)

Centered on common mode

CLK

50Ω Line

CLKN

223 mV

-223 mV

CLKN (J27)

11.4 LVDS Input Implementation

The DAI/DAIN input data of the standalone delay cell is LVDS compatible. It is 2 × 50Ω differen-

tially on-chip terminated as described in Figure 11-8.

Figure 11-8. AT84AS004 LVDS Input (DAI/DAIN) Termination Scheme

004

AT84AS

50Ω Line

DAI

50Ω Line

5 pF

50Ω Line

DAIN

48

AT84AS004

5431C–BDC–01/06

AT84AS004

11.5 LVDS Output Implementation

The data (Ai/AiN…Di/DiN, AOR/AORN…DOR/DORN and DAO/DAON) and clock outputs

(DR/DRN) are LVDS compatible. They have to be 100Ω differentially terminated as described in

Figure 11-9.

Figure 11-9. AT84AS004 LVDS Output Termination Scheme

AT84AS004

50Ω Line

Positive output signal

100Ω

50Ω Line

Negative output signal

11.6 DRRB and ASYNCRST Implementation

The DRRB and ASYNCRST are required to start the device properly. DRRB is active at low level

while ASYNCRST is active at high level.

As it is recommended to apply both reset signals simultaneously, one possible solution is to use

a differential driver so that DRRB and ASYNCRST are generated as the two signals of a differ-

ential pair. This would allow for both the simultaneous application of the signals to the device a

simple way to drive both signals. An example is provided below, Figure 11-10.

Figure 11-10. AT84AS004 DRRB and ASYNCRST Driver Scheme

DRRB

1 ns Pulse Source

ASYNCRST

Please refer to the AT84AS004 “Reset Implementation Application Note” for more information.

49

5431C–BDC–01/06

12. Package Information

Figure 12-1. .EBGA317 Package Outline

Note:

The two pads at the bottom of the EBGA package are the dice moldings and should not be soldered to the board.

50

AT84AS004

5431C–BDC–01/06

AT84AS004

13. Ordering Information

Table 13-1. Ordering Information

Part Number

Package

Temperature Range Screening

Comments

Commercial C

AT84AS004CTP

EBGA 317

0°C < T_amb

T_J< 90°C

Standard

Industrial V

-40°C < T_amb

T_J< 110°C

AT84AS004VTP

AT84XAS004TPY

AT84AS004CTPY

EBGA 317

Standard

Prototype

Please contact

your local Atmel

sales office

EBGA 317

RoHS

Ambient

Commercial C

0°C < T_amb

T_J< 90°C

Please contact

your local Atmel

sales office

EBGA 317

RoHS

Standard

Prototype

Industrial V

-40°C < T_amb

T_J< 110°C

Please contact

your local Atmel

sales office

EBGA 317

RoHS

AT84AS004VTPY

AT84AS004TP-EB

EBGA 317

Ambient

Evaluation kit

51

5431C–BDC–01/06

52

AT84AS004

5431C–BDC–01/06

AT84AS004

Table of Contents

Features..................................................................................................... 1

Performances............................................................................................ 1

Screening................................................................................................... 1

Applications .............................................................................................. 1

Description ............................................................................................... 2

Block Diagram .......................................................................................... 2

Functional Description ............................................................................ 3

Specifications ........................................................................................... 5

1

2

3

4

4.1

4.2

4.3

4.4

Absolute Maximum Ratings .................................................................................5

Electrical Operating Characteristics ....................................................................7

Explanation of Test Levels ................................................................................12

Digital Coding ....................................................................................................13

5

Characterization Results ....................................................................... 14

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

Nominal Conditions ...........................................................................................14

Full Power Input Bandwidth ...............................................................................14

VSWR Versus Input Frequency ........................................................................15

Step Response ..................................................................................................15

Dynamic Performance Versus Sampling Frequency .........................................16

Dynamic Performance Versus Input Frequency ................................................16

Signal Spectrum ................................................................................................17

Dynamic Performance Sensitivity Versus Temperature and Power Supply ......18

Dual Tone Performance ....................................................................................19

5.10 NPR Performance .............................................................................................19

Pin Description ....................................................................................... 20

Main Features ......................................................................................... 24

6

7

7.1

7.2

7.3

7.4

7.5

7.6

Reset .................................................................................................................24

Control Signal Settings ......................................................................................25

Programmable DMUX Ratio ..............................................................................27

Output Mode (STAGG) ......................................................................................27

Additional Bit .....................................................................................................29

Output Clock Type Selection .............................................................................30

i

5431C–BDC–01/05

7.7

7.8

7.9

Power Reduction Mode (SLEEP) ......................................................................30

Standalone Delay Cell .......................................................................................30

Clock input Delay Cell .......................................................................................31

7.10 Built-In Self Test ................................................................................................31

7.11 ADC Die Junction Temperature Monitoring .......................................................31

7.12 Pattern Generator Function ...............................................................................33

7.13A DC Gain Control ................................................................................................33

7.14 Sampling Delay Adjust ......................................................................................34

8

Equivalent Input/Output Schematics ................................................... 35

8.1 Equivalent Analog Input Circuit and ESD Protection ..........................................35

8.2 Equivalent Clock Input Circuit and ESD Protection ............................................35

8.3 Equivalent Data/Clock Output Buffer Circuit and ESD Protection ......................36

8.4

Standalone Delay Cell Data Input (DAI/DAIN) Buffer Circuit and

ESD Protection

36

8.5

Delay Cell (DACTRL/DACTRLN and CLKCTRL/CLKCTRLN) Control Input

Schematic and ESD Protection

37

8.6

8.7

8.8

8.9

DRRB Equivalent Input Schematic and ESD Protection ...................................37

ASYNCRST Equivalent Input Schematic and ESD Protection ..........................38

ADC Gain Adjust Equivalent Input Circuits and ESD Protection .......................38

B/GB and PGEB Equivalent Input Schematics and ESD Protection .................39

8.10 Control Signals Input Buffers and ESD Protection ............................................39

9

Definitions of Terms .............................................................................. 40

10 Thermal and Moisture Characteristics ................................................. 42

10.1 Thermal Resistance from Junction To Bottom of Balls ......................................42

10.2 Thermal Resistance from Junction To Top of Case ..........................................42

10.3 Thermal Resistance from Junction To Board ....................................................42

10.4 Thermal Resistance from Junction To Ambient .................................................43

10.5 Thermal Management Recommendations ........................................................43

10.6 Moisture Characteristics ....................................................................................44

11 Applying the AT84AS004 ...................................................................... 44

11.1 Bypassing, Decoupling and Grounding .............................................................44

11.2 Analog Input Implementation .............................................................................45

11.3 Clock Input Implementation ...............................................................................46

11.4 LVDS Input Implementation ..............................................................................47

11.5 LVDS Output Implementation ............................................................................48

ii

AT84AS004

5431C–BDC–01/05

AT84AS004

11.6 DRRB and ASYNCRST Implementation ...........................................................48

12 Package Information .............................................................................. 49

13 Ordering Information ............................................................................. 50

Table of Contents....................................................................................... i

iii

5431C–BDC–01/05

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

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Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

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Tel: 1(408) 441-0311

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Literature Requests

www.atmel.com/literature

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Printed on recycled paper.

5431B–BDC–01/05


型号：	AT84AS004VTP
厂家：	ATMEL
描述：	ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, Bipolar, PBGA317, 25 X 35 MM, MS-034, EBGA-317 ATM 异步传输模式转换器
文件：	总56页 (文件大小：954K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT84AS004VTP [ATMEL]

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