AT73C224-B_14_技术文档

Features

• DC/DC Step-up Converter (BOOST) 3.3V to 5.2V, 1A, up to 90% Efficiency. Can be Used

as BUCK/BOOST in SEPIC Configuration

• DC/DC Step-down (BUCK) Synchronous Converter 0.9V to 3.4V, 500mA, up to 90%

Efficiency, Pulse Skipping Capabilities for High Efficiency at Light Load Currents

• Two Low-Drop-Out Regulators 1.3V, 1.5V to 1.8V, 2.5V to 2.8V (100 mV Step), 3.3V,

200 mA Maximum Load

• Ultra-low Power Real-time Clock (RTC) and Backup Battery Management

– 2.6V RTC LDO for Backup Battery Charging

Power

– 32 kHz Crystal RTC Oscillator (1 µA)

– RTC Circuit for Time and Date Information

Management

and Analog

Companions

(PMAAC)

• Activation of the Power Management Modules via Dedicated Enable Pin

• Automatic Start-up Sequences, POK Signal Indicating When Start-up is Completed

• Activation and Control of the Power Management Modules in Dynamic Mode (via SPI or

TWI) or in Static Mode (On/Off of the Four Power Supplies)

• ITB Signal Indicating Short-circuits in DC/DC Converters

• Very Low Quiescent Current

• Minimum External Components Count

• Supply: from 2.8V to 5.25V (typ: Li-Ion Battery 3V to 4.2V)

• Available in a 32-pin 5x5 QFN Package

• Applications Include:

AT73C224-A

AT73C224-B

AT73C224-C

AT73C224-D

AT73C224-E

AT73C224-F

AT73C224-G

AT73C224-H

– WLAN Portable Devices

– Multimedia Devices

– Portable Music Players

1. Description

The AT73C224-x is a family of ultra low cost Power Management Unit, available in a

small outline QFN 5x5mm package.

The AT73C224-x family is optimized for portable applications, typically powered by a

Li-Ion battery. The AT73C224-x device is also suitable to operate from a standard

3.3V to 5.25V voltage rail. It includes four power supplies and a very low power Real-

time Clock (RTC). In normal mode (main battery present), the backup battery is

recharged through a 2.6V RTC LDO.

The AT73C224-x series offer different automatic start-up sequences (with varying

orders of power-on and specific default output values) and different soft management

modes: dynamic (via SPI or TWI) with register access or static, with access to power

on/off of the four power supplies.

4x Channels

Power Supply:

DC/DC BOOST

Each AT73C224-x device is equipped with a very low power bandgap reference, low

power 32 kHz and 1 MHz oscillators and an internal LDO used to generate the internal

supply (VINT) equal to 2.8V. Auxiliary cells, such as a power-on reset (POR) and a

voltage monitor are used to control the system power-on (battery plugged in) and

power-off (battery unplugged).

DC/DC BUCK

.

2x LDOs

RTC

The four power supplies are named: BOOST1, BUCK2, LDO3 and LDO4.

Table 1-1 lists the different devices available in the AT73C224-x series.

6266A–PMAAC–08-Sep-08

For more details concerning the Automatic start-up sequences, see Section 5.2.

For more details concerning the Management Modes, see Section 5.3.

.

Table 1-1.

AT73C224-x device series

Part Number

Automatic Start-up Sequence

Management Mode Comments

Order of power-on and output default values.

1 - BUCK2= 1.8V

2 - LDO4 = 2.8V

3 - LDO3 = 2.7V

BOOST1 can be activated after Start-up

sequence by a user command.

AT73C224-A

AT73C224-B

AT73C224-C

AT73C224-D

Dynamic

1 - BUCK2 = 1.2V

2 - LDO4 = 1.8V

3 - LDO3 = 1.8V

BOOST1 can be activated after Start-up

sequence by a user command.

1 - LDO4 = 2.8V

2 - BUCK2 = 1.8V

3 - LDO3 = 2.7V

BOOST1 can be activated after Start-up

sequence by a user command.

1 - LDO4 = 1.8V

2 - BUCK2 = 1.2V

3 - LDO3 = 1.8V

BOOST1 can be activated after Start-up

sequence by a user command.

BUCK2 can be activated after Start-up

sequence by a user command.

1 - BOOST11 = 5.2V

2 - LDO4 = 3.3V

3 - LDO3 = 3V

AT73C224-E

Dynamic

LDO3 & LDO4 are supplied by BOOST1.

(See Section 4. “Application examples”, Figure

4-3 on page 7: Application Schematic 3.)

1 - BUCK2 = 1.8V

2 - LDO4 = 2.8V

3 - LDO3 = 2.7V

AT73C224-F

AT73C224-G

AT73C224-H

Static

Same as AT73C224-A.

Same as AT73C224-C.

Same as AT73C224-E.

1 - LDO4 = 2.8V

2 - BUCK2= 1.8V

3- LDO3 = 2.7V

1 - BOOST1 = 5.2V

2 - LDO4 = 3.3V

3 - LDO3 = 3V

2

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

2. Block Diagram

Figure 2-1. Block Diagram

LDO3

VOUT

1.3V

1.5V-1.8V

2.5V-2.8V

3.3V

VDD1

22

VDD3

2

1

3

VO3

VSENSE1

BOOST1

21

20

GNDANA

VOUT

3.3V-5.2V

ILOAD

1A

ILOAD

200 mA

DL1

VO1

LDO4

VDD4

VO4

23

24

VOUT

1.3V

18

1.5V-1.8V

2.5V-2.8V

3.3V

ILOAD

200 mA

VBAT_LDORTC

10

32

30

31

VDD2

SW2

POR RTC

RTC LDO

RTC OSC

9

VBACKUP

XOUT

P

N

XIN

BUCK2

CK32

29

VOUT

0.9V-3.4V

ILOAD

16

VDDIO

D1

25

26

27

500 mA

GND2

VO2

Digital

Interface

(TWI / SPI)

17

11

D2

D3

28

13

14

15

PMC

D4

Status

Register

POK

ITB

Die

Paddle

GND/AVSS

VBG

OSC 900kHz

8

POR,

VMON

(Voltage Monitor)

LPVBG

(Low power VBG)

VINT

Regulator

VDD0

6

EN

12

VCAPP

VCAPN

VINT

7

5

4

3

6266A–PMAAC–08-Sep-08

3. Pinout

Table 3-1.

Pin Name

VO3

AT73C224 Pinout

I/O

O

Pin #

Type

Analog LDO3 output voltage

Power LDO3 supply voltage

Function

Comments

1

2

3

4

5

Ext. 2.2 µF capacitor (mandatory)

VDD3

PS

I/O

PS

GNDANA

VCAPP

VINT

Ground Analog ground

Analog Not connected

Power

Output of the internal LDO

Ext. 470 nF capacitor (mandatory)

Must be connected to the main

battery (mandatory)

VDD0

PS

6

Analog Supply of the internal LDO

VCAPN

VBG

I/O

O

7

8

9

Analog Not connected

Analog Bandgap reference voltage

Should not be resistively loaded

VDD2

PS

Power

BUCK2 supply voltage

Must be connected to the main

battery (mandatory)

VBAT_LDORTC

PS

10

LDO_RTC Supply voltage

VO2

I

11

12

13

14

15

16

17

18

19

20

21

Analog BUCK2 output voltage

EN

Digital

Enable signal

Internal 100 KΩ pull up

D4

I

Digital interface

POK

O

I/O

O

PS

I

Power Ok: indicates when start-up is completed

User Interrupt, GPIO and Shutdown control

ITB/RDY

SW2

GND2

VO1

Internal 100 KΩ pull up

Analog BUCK2 inductor (NMOS switcher output)

Ground BUCK2 ground

Analog BOOST1 output voltage

DH1

O

I

Analog Not connected

DL1

Analog BOOST1 NMOS control signal

Analog BOOST1 current limitation sense voltage

VSENSE1

Must be connected to the main

battery

VDD1

PS

22

Power

BOOST1 supply voltage

VDD4

VO4

PS

O

23

24

Power

LDO4 supply voltage

Analog LDO4 output voltage

Digital

Ext. 2.2 µF capacitor (mandatory)

VDDIO

PS

25

Supply voltage for Digital I/O

supply

Digital

D1

I

26

27

28

29

30

31

32

Digital interface

open drain

D2

I/O

I

Digital interface

D3

Digital interface

CK32

XOUT

XIN

O

32 kHz RTC output clock

I/O

O

Analog RTC crystal oscillator output

Analog RTC crystal oscillator input

Analog Backup Battery and RTC supply

VBACKUP

die paddle connected to ground

(mandatory)

GND/AVSS

PS

33

Ground Main G_NDand AV_SSground

4

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

4. Application examples

Figure 4-1. Application Schematic 1: Microcontroller with 5V VBUS for 2 USB Host Transceivers

LDO3 = 2.7V

R2

(AUX ADC, PLL)

V_BAT

C9

Rechargeable

Backup

Battery

X1

C11

C12

C4

uP

32

(NBL type)

LDO4 = 2.8V

VDDIO

1

V_BAT

C6

VO4

VDD4

VDD1

VSENSE1

DL1

VO3

V_BAT

R1

VDD3

C3

C8

D1

GNDANA

L1

VO1

Microcontroller

nc

VCAPP

C1

AT73C224-A

VINT

C14

V_BAT

Q1

DH1

nc

VDD0

VCAPN

C5

nc

VO1

USB HOST

transceiver

GND2

VBG

BOOST1 = 5V

(VBUS USB)

C10

GND/AVSS

Die

Paddle

uP

USB HOST

transceiver

V_BAT

C13

V_BAT

C7

V_BAT

Pushbutton

L2

3V

to

4.2V

SPI / TWI

BUCK2 = 1.8V

Li-Ion

Battery

VO2

C2

VCORE

C16

POK

D1 D2 D3 D4

ITB/RDY

In the Application Schematic 1, the AT7373C224-A is used: the BOOST(VO1) supplies the

“VBUS” of two USB transceivers, the BUCK(VO2) supplies the digital core of the microcontroller,

the LDO3 supplies the I/Os of the microcontroller and LDO4 supplies analog cells, such as aux-

iliary ADC or PLL.

For external components, see Table 4-1.

5

6266A–PMAAC–08-Sep-08

Figure 4-2. Application Schematic 2: Supply of a Microprocessor and External Analog Cells

BOOST1 = 5V

Analog Cells

R2

V_BAT

C9

VO4

Rechargeable

Backup

Battery

X1

C11

C12

C4

uP

32

(NBL type)

LDO4 = 1.8V

VDDIO

1

V_BAT

C6

VO4

VDD4

VDD1

VSENSE1

DL1

VO3

V_BAT

R1

VDD3

C3

C8

D1

GNDANA

L1

VO1

nc

VCAPP

C1

VINT

AT73C224-B

C14

Q1

V_BAT

nc

VDD0

VCAPN

DH1

C5

VO1

Microcontroller

BOOST1 = 5V

BUCK2 = 1.2V

GND2

VBG

C10

GND/AVSS

Die

Paddle

uP

V_BAT

C13

V_BAT

C7

V_BAT

L2

BUTTON

SPI / TWI

3V

to

4.2V

Li_Ion

Battery

VO2

C2

VCORE

C16

POK

D1 D2 D3 D4

ITB/RDY

In the Application Schematic 2, the AT73C224-B is used: the BOOST (VO1) supplies the

“VBUS” of one USB transceiver and supplies also LDO3 and LDO4. The BUCK(VO2) supplies

the digital core of the microcontroller and the LDOs supply the I/Os and Analog cells, such as

auxiliary ADC or PLL.

For external components, see Table 4-1.

6

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

Figure 4-3. Application Schematic 3: BOOST in SEPIC Configuration (BUCK/BOOST)

BOOST1 = 3.3V

Analog Cells

R2

V_BAT

C9

VO4

Rechargeable

Backup

Battery

X1

C11

C12

C4

uP

32

(NBL type)

LDO4 = 1.8V

VDDIO

1

V_BAT

C6

VO4

VDD4

VDD1

VSENSE1

DL1

VO3

V_BAT

R1

VDD3

C3

C8

D1

GNDANA

C15

L1

VO1

nc

VCAPP

C1

VINT

AT73C224-B

C14

L3

Q1

V_BAT

nc

VDD0

VCAPN

DH1

C5

VO1

Microcontroller

BOOST1 = 3.3V

BUCK2 = 1.2V

GND2

VBG

C10

GND/AVSS

Die

Paddle

uP

V_BAT

C13

V_BAT

C7

V_BAT

L2

BUTTON

SPI / TWI

3V

to

4.2V

Li_Ion

Battery

VO2

C2

VCORE

C16

POK

D1 D2 D3 D4

ITB/RDY

In the Application Schematic 3, the BOOST (VO1) is in SEPIC configuration (BUCK/BOOST)

and generates a 3.3V output voltage for analog cells. The BUCK (VO2) supplies the core of the

microcontroller, and LDO4 supplies the I/Os.

Note that, in the SEPIC configuration, the maximum load current on VO1 should not exceed 300

mA.

For external components, see Table 4-1.

7

6266A–PMAAC–08-Sep-08

Table 4-1.

External Components

Schematic reference

Reference

Manufacturer

AVX^®

Value

100 µF

33 µF

C1

C2

Tantalum TPS Case B

Tantalum TPS Case A

AVX

GRM155R60J225ME15

C1005X5R0J225MT

Murata^®

TDK

C3, C4

2.2 µF

22 µF

1 µF

GRM21BR60J226ME39

C2012X5R0J226MT

Murata

TDK

C6

GRM155R60J105KE19

C1005X5R0J105KT

Murata

TDK

C5, C7, C8, C9, C11, C13

GRM155R61A104KA01

C0603X5R0J104KT

Murata

TDK

C10

100 nF

470 nF

4.7 µF

10 µF

GRM155R60J474KE18

C1005X5R1A474KT

Murata

TDK

C12, C14

C15

GRM188R60J475KE19

C1608X5R0J475KT

Murata

TDK

GRM188R60J106ME47

C1608X5R0J106MT

Murata

TDK

C16

L1

744773022

744773068

Wurth^®Elektronik

Wurth Elektronik

Epcos^®

On Semiconductor^®

Vishay^®

2.2 µH

6.8 µH

L1, L3 (in SEPIC config.)

L2

B82467-G0682-M

MBRM120LT1

Si1470DH

D1

Q1

X1

FX135B-327

Fox

32.768 kHz

50 mΩ

R1 (can be printed on the

board (Cu line))

LR2010R050J

Welwyn

R2

MR-CRG0402J2k2

Tyco^™Electronics

2 kΩ

8

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

5. Detailed Description

The AT73C224-x is a family of Power Management Units with four power supplies and an ultra

low-power Real-time Clock.

By choosing a specific ordering code “x” from A to H, different automatic start-up sequences and

management modes can be selected.

The start-up sequence includes the order of power-on, as well as the default value of the power

supplies (see Section 5.2 ”Automatic Start-up Sequences and Shut-down”). The user can after-

wards change this default value via SPI or TWI, if the dynamic mode has been chosen (see

Section 5.3 ”Digital Control and Protocol”).

5.1

Core

The core of the AT73C224-x device integrates the following blocks:

• Power-On-Reset for the backup battery.

• Internal switch and LDO dedicated to the backup battery. The output of the LDO_RTC is set

to 2.6V and the switch is on when the main battery higher than 2.8V (charge of the backup

battery).See Section 7.7 for electrical details.

• Real-Time-Clock digital bloc + 32 kHz oscillator.

• Power-On-Reset for the main battery.

• Voltage Monitor (VMON) of the main battery.

• Digital Power Management Control (PMC) for automatic start-up sequences. Digital output

POK indicates when start-up is completed, whereas ITB digital output signal informs the user

(typically the microcontroller) of a default in the DC/DCs (short-circuit) or too low main battery

value.

• TWI and SPI protocol blocs.

• DC/DC Step-up converter BOOST1: A 3.3V to 5.2V(100 mV step), 1A, asynchronous DC/DC

Step-up Converter available for overall system requirements. The DC/DC can be

implemented through proper external components in BUCK/BOOST (SEPIC) configuration.

The output voltage can be programmed via the internal registers. BOOST1 is supplied

directly by the battery.

• DC/DC Step-down converter BUCK2: A 0.9V to 3.4V, 500 mA fully integrated synchronous

PWM DC/DC Step-down Converter. The output voltage can be programmed via the internal

registers. A Pulse Skipping mode is available in order to improve efficiency at very light load

current values. In order to guarantee very low supply voltage functionality, the controller is

supplied by the max voltages between the main battery and the output of BOOST1 (VO1).

BUCK2 can be directly supplied by the battery or by the output of BOOST1.

• LDO3: A 1.3V, 1.5V to 1.8V (100 mV of step), 2.5V to 2.8V (100 mV of step), 3.3V, 200 mA –

Low Drop out regulators. The output voltage can be programmed via the internal registers.

LDO3 can work with supply from 1.8V up to 5.5V. This LDO can be supplied by the battery, by

the output of BOOST1, or by the output of BUCK2.

• LDO4: same functionality than LDO3.

• Main Bandgap: 1.18V reference voltage.

• 900 kHz Oscillator.

• Internal LDO (VINT) at 2.8V for internal supply.

9

6266A–PMAAC–08-Sep-08

5.2

Automatic Start-up Sequences and Shut-down

5.2.1

Start-up/Wakeup

If the backup battery (only) is present, the RTC is running (1.2 µA). This mode is called “Backup

mode”. When the main battery is plugged in and voltage is higher than 2.8V, the LDO_RTC

recharges the backup battery through an internal switch (if the main battery is lower than 2.8V,

nothing happens, RTC still running). This mode is called “Standby mode”. Note that when the

battery is plugged in (and higher than 2.8V), a reset of the RTC is performed only if the backup

battery was lower than 1.8V.

Now, the system waits for wake-up information coming from the pushbutton (EN pin) or an RTC

alarm. When one of the previous conditions occurs, the automatic start-up sequence starts

(without any external commands).

Different automatic start-up sequences can be chosen from the AT73C224-x family (see Figure

5-1 on page 11 and Figure 5-2 on page 12).

When the automatic start-up sequence has been completed, the POK signal (which is an open

drain signal) goes high, thus implementing a sort of POR for the user (i.e., a microcontroller) and

enters into “Normal mode”.

Note: Power On is controlled by default by an external pushbutton, connected on EN pin (the EN

pad has an internal 100 kΩ pull up). A switch can also be used as shown bellow but should be a

request from the customer

.

EN

(Default: Pushbutton)

EN

(On request: switch)

5.2.2

Shut-down

Static and Dynamic modes are explained in detail in Section 5.3.

5.2.2.1

Static Mode

In Static mode, the Power-off condition is an OR between the following conditions: main battery

lower than 2.8V or electrical default in the DC/DC (short-circuit). When Power-off condition

occurs, POK signal is cleared, then the AT73C224-x device waits for the signal ITB/RDY to shut

down all power supplies.

5.2.2.2

Dynamic Mode

In Dynamic mode, Power-off condition is an OR between the following conditions: electrical

default in the DC/DC (short-circuit) or software shutdown. When main battery lower than 2.8V,

an interrupt is generated on signal ITB/RDY. It is the responsibility of the host microcontroller to

perform a software shut-down by properly writing the AT73C224-x device registers through the

serial interface. After that, the POK signal is cleared, and all is turned off. A check on the push-

button is then performed to assure that it has been released, thus avoiding continuous on-off-on

behavior. The “normal” shutdown is performed by software. Note that the microcontroller has to

write the proper register to enable the power off (see Section 6. ”Register Tables”).

10

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

Figure 5-1 illustrates the complete automatic start-up sequence of the AT73C224-A and

AT73C224-F, whereas Figure 5-2 illustrates the automatic start-up sequence of the other

AT73C224-x device versions.

Figure 5-1. Start up Sequence of the AT73C224-A and AT73C224-F

VBAT

POR

(internal Vth = 1.6V)

VMON

(internal Vth = 2.8V)

30 ms min

VINT

(internal supply)

PWRGDINT

(internal- Vth = 1.6V)

VBG

36 ms typ.

Automatic Start-up Sequence:

BUCK2

(Default value: 1.8V)

3ms

LDO4

(Default value: 2.8V)

3ms

LDO3

(Default value: 2.7V)

3ms

45ms typ

POK -> uP

(Start-up sequence

completed)

BOOST1

User Command:

. AT73C224-A: Through Dynamic mode (using TWI or SPI)

. AT73C224-F: Through Static mode (using D1 pin)

11

6266A–PMAAC–08-Sep-08

Figure 5-2. Automatic Start-up Sequence of all Other Versions of the AT73C224-x Device Series

POK (Automatic Start-up

sequence completed)

V

BUCK2

(Default value: 1.2V)

3ms

LDO4

(Default value: 1.8V)

3ms

LDO3

(Default value: 1.8V)

3ms

BOOST1

User Command:

. AT73C224-B: Through Dynamic mode (using TWI or SPI)

AT73C224-B, AT73C224-G

BUCK2

(Default value: 1.8V)

LDO4

(Default value: 2.8V)

LDO3

(Default value: 2.7V)

BOOST1

User command:

. AT73C224-C: Through Dynamic mode (using TWI or SPI)

. AT73C224-G: Through Static mode (using D1 pin)

AT73C224-C, AT73C224-H

BUCK2

(Default value: 1.2V)

LDO4

(Default value: 1.8V)

LDO3

(Default value: 1.8V)

BOOST1

User Command:

. AT73C224-D: Through Dynamic mode (using TWI or SPI)

AT73C224-D, AT73C224-I

BUCK2

User command:

. AT73C224-E: Through Dynamic mode (using TWI or SPI)

. AT73C224-H: Through Static mode (using D2 pin)

LDO4

(Default value: 3.3V)

LDO3

(Default value: 3V)

BOOST1

(Default value: 5.2V)

AT73C224-E, AT73C224-J

12

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

5.3

Digital Control and Protocol

The AT73C224-x family offers a choice of devices in static mode or dynamic mode (see Table 1-

1 on page 2). In dynamic mode, the user can manage the chip via SPI or TWI. The selection

between SPI or TWI is done at start-up via the D4 pin (see Section 5.3.2 on page 14).

5.3.1

Static Mode

When the AT73C224-x is established in Static Mode, the digital interface signals, D1 to D4,

directly drive the enable of the four supplies. During start-up, these enable signals are driven by

the internal state machine. To ensure a safe transition between the start-up state and the estab-

lished state, a handshake protocol must be respected. This transition period is especially

important in a microcontroller environment, as the microcontroller controlling the D1-D4 signals

may require an unknown period of time to actually drive these pins.

In Static Mode, the ITB/RDY pin is configured as an input with controllable pull-up resistor. When

the internal state machine completes the supply start-up, it latches the value of ITB/RDY and

then sets the POK signal to 1. This means that start-up is accomplished. The state machine then

checks for changes on ITB/RDY. If no changes are detected, the control of the four supply chan-

nels remains with the state machine. If a change is detected the internal pullup is disconnected

and the control is passed on to D1-D4, with the assignment shown in Table 5-2 below.

Table 5-1.

D1-D4 Signal Assignment

Digital Interface Signal

Supply Enable

Enables BOOST1

Enables BUCK2

Enables LDO3

Enables LDO4

D1

D2

D3

D4

The illustrations in Figure 5-3, Figure 5-5 and Figure 5-5 represent possible static mode

scenarios.

Figure 5-3. Fully Static Mode

0 or 1

D1

D2

D3

D4

ITB/RDY

POK

Open or 1

Power OK

Since ITB/RDY is 1 or open (weak internal pullup), the state of each supply channel is deter-

mined by the internal state machine (Automatic Start-up sequence and default values for the

three power supplies). In this configuration, the 4th power supply is off and can not be used. D1-

D4 is not considered, but must be valid. The POK signal can be used as a global system reset.

13

6266A–PMAAC–08-Sep-08

Figure 5-4. Configurable Static Mode

0

1

D1

D2

D3

D4

ITB/RDY

POK

Power OK

The state of each channel is determined by the internal state machine during the start-up

sequence. POK is looped back onto ITB/RDY. When this signal changes from 0 to 1 (i.e., the

start-up is completed), the control of each supply channel is passed on to D1-D4. This allows

changing the output values defined by the state machine. This mode can be used when the 4th

channel is needed.

Figure 5-5. GPIO (µC Controlled)

D1

D2

D3

D4

I/O

µC

ITB/RDY

POK

I/O

RST or NMI

When the system is powered, the microcontroller is not necessarily well configured and may be

unable to drive D1-D4 correctly. Since ITB/RDY is not actively controlled, its state is an unknown

logic level. If ITB/RDY is in hi-Z, the weak internal pullup pulls the level to 1. The power channels

are controlled by the internal state machine. After some initialization time, the microcontroller

configures its GPIOs to drive D1-D4 as wished. At the end of the software configuration, the

microcontroller changes the level of ITB/RDY to 0 in order to get control on the four power chan-

nels through D1-D4.

5.3.2

Dynamic Mode

For the devices of the AT73C224-x family that work in dynamic mode, supply management can

be performed by the SPI or TWI digital interface. Selection between the two digital interfaces is

done through D4 pin when the AT73C224-x is enabled. Pin D4 is a digital input pin that features

a controllable pull-up resistor with active low control signal. When the AT73C224-x starts, the

pullup is disabled until a push button event is detected. The state machine enables the pull-up

resistor on D4, waits for a time and then checks back on the value on the pad.

• If D4 is high (i.e., the level externally applied on D4 is HZ or logic 1), SPI interface is selected.

D4 will become SCS.

• If D4 is low (i.e., D4 is externally grounded), TWI interface is selected. D4 is not used.

After signal dynamic has been determined the state machine disables the pull-up resistor to

save power and the D4 pin can be normally used (if SPI has been selected).

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AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

The selection between SPI versus TWI is performed once, each time the start-up sequence is

executed. A timing diagram of the interface selection is shown in Figure 5-6. Care must be taken

to leave enough time between the activation of the pullup and the moment when D4 is sampled

back. This time is necessary to load the capacitance of the net layout where D4 is connected

through the pull-up resistor (100 kΩ typ.). This time is in the order of magnitude of 1 µs (10 pF *

100 kΩ), i.e. only a few cycles of the 900 kHz oscillator are needed.

Figure 5-6. Dynamic Mode Interface Selection

D4

Hz

SPI selected, D4 => SCS

D4 pull-up control signal

dynamic

D4

D4 pull-up control signal

dynamic

TWI selected

SCS = Serial Chip Select

Table 5-2.

Digital Interface Selection

SPI Selection

Direction

TWI Selection

Signal

Digital Signal

Interface

Pad

I

Signal

SCK

Direction

D1

D2

In

TWCK

In

BIDIR

SDO

Out

TWD

I/O

Select the 7-bit

fixed address

D3

I

SDI

In

-

D4⁽¹⁾

SCS

grounded

Note:

1. On D4, I = Input pad with controllable pull-up resistor.

5.3.2.1

SPI Operation

When SPI mode is selected, the control interface to the AT73C224-x chip is a 4-wire interface

modeled after commonly available microcontroller and serial-peripheral devices. The interface

consists of a serial clock (SCK), chip select (SCS), serial data input (SDI) and serial data output

(SDO). Data is transferred one byte at a time with each register access consisting of a pair of

byte transfers. Figure 5-7 below illustrates read and write operations in SPI mode.

15

6266A–PMAAC–08-Sep-08

Figure 5-7. SPI Read and Write Operations

SCK

SCS

SDI

0

A6 A5 A4

A3 A2 A1

A0

D7 D6 D5 D4 D3 D2 D1 D0

Hz

SDO

SPI Write

SCK

SCS

SDI

1

A6 A5 A4

A3 A2 A1

Hz

A0

SDO

D7 D6 D5 D4 D3 D2 D1

D0

SPI Read

The first byte of a pair is the command/address byte. The most significant bit of this byte indi-

cates register read when 1 and register write when 0. The remaining seven bits of the

command/address byte indicate the address of the register to be accessed.

The second byte of the pair is the data byte. During a read operation, the SDO becomes active

and the 8-bit contents of the register are driven out MSB first. The SDO will be in high imped-

ance on either the falling edge of SCK following the LSB or the rising edge of SCS, whichever

occurs first.

SDI is a don't care during the data portion of read operations. During write operations, data is

driven into the AT73C224-x via the SDI pin, MSB first. The SDO pin will remain in high imped-

ance during write operations. Data always transitions with the falling edge of the clock and is

latched on the rising edge. The clock should return to a logic high when no transfer is in

progress.

• Continuous clocking: In normal operation, the SCK should not transition out of byte transfer

periods. However, in test mode, the SCK is used as the main clock. This implies that all data

transfers must be controlled by the assertion of the SCS pin.

• 3-wire operation: SDI and SDO can be treated as two separate lines or wired together if the

master is capable of tri-stating its output during the data-byte transfer of a read operation.

• SCK vs internal clock rates: It is very likely that the bit rate commanded by SCK will be

much higher than the internal clock (900 kHz/64) used to read and write the registers. This

implies that a minimal delay between byte transfers must be imposed to allow some time to

decode the address and actually access the physical register. It is not acceptable to sample

SCK with the internal clock.

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AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

5.3.2.2

TWI Operation

The TWI interface allows a microcontroller to proceed to read or write accesses to the internal

registers of the AT73C224-x. Unlike the SPI, the TWI operation is based on a standard which

defines a data-link layer and an addressing scheme. The TWI implementation used in the

AT73C224-x conforms to this standard, with the following restrictions:

• slave only

• bit rate: 400 kbps max

• 7-bit fixed address: the default value is 1001001 (D3 is high). But the external D3 bit can

modify it. When D3 is low, the 7-bit fixed address is 1001000.

• TWCK is an input pin for the clock

• TWD is a bidirectional pin driving (open drain with external resistor connected to V_DDIO) or

receiving the serial data.

The data put on TWD line must be 8 bits long. Data is transferred MSB first. Each byte must be

followed by an acknowledgement. Each transfer begins with a Start condition and terminates

with a STOP condition.

• A high-to-low transition on TWD while TWCK is high defines a START condition.

• A low-to-high transition on TWD while TWCK is high defines a STOP condition.

Figure 5-8.

TWI Start/Stop Condition

TWD

TWCK

START

STOP

Figure 5-9.

TWI Protocol

TWD

TWCK

START

STOP

Address

R/W

Ack

Data

Ack

Data

Ack

After the host initiates a START condition, it sends the 7-bit slave address, as defined above, to

notify the slave device. A Read/Write bit follows (Read = 1, Write = 0). The device acknowledges

each received byte. The first byte sent after device address and R/W bit is the address of the

device register the host wants to read or write. For a write operation, the data follows the internal

address. For a read operation, a repeated START condition needs to be generated followed by

a read on the device.

Write and Read operations are shown in Figure 5-8 and Figure 5-9.

17

6266A–PMAAC–08-Sep-08

The TWI abbreviations are defined below.

S = Start

P = Stop

W = Write

R = Read

A = Acknowledge

N = Not Acknowledge

ADDR = Device Address

IADDR = Internal Address

Figure 5-10. Write Operation

TWD

S

ADDR

W

A

IADDR

A

DATA

A

P

Figure 5-11. Read Operation

TWD

S

ADDR

W

A

IADDR

A

S

ADDR

R

A

DATA

N

P

5.3.3

Interrupt Controller

In dynamic mode, the ITB/RDY pin is an output and operates as an interrupt to an external

microcontroller. The output logic is active low (a 0 level means interrupt).

Several sources can potentially trigger an interrupt:

• the RTC, when a real-time alarm event occurs (see Section 7.8 ”Real-time Clock (RTC)” for

more details)

• the push-button, when its state changes

• the power monitor, when it detects a failure or main battery lower than 2.7V

• the boost, when it detects a failure

• the buck, when it detects a failure

Each of these sources can be individually masked to disable the corresponding interrupt. All the

interrupt logic can also be globally disabled when the microcontroller needs to enter an uninter-

ruptible state. The interrupt enable/disable logic is controlled through two independent registers.

Refer to Section 6. ”Register Tables” for detailed register and bit assignment. IRQ_EN is used to

enable the interrupts, while IRQ_DIS is used to disable the interrupts. This strategy allows the

controlling software to handle the interrupt mask completely independently for each interrupt

source while avoiding read-modify-write operations. The register IRQ_MSK can be read to know

the current interrupt mask.

The sequence shown below in Table 5-3 shows an example of interrupt masking/unmasking.

Table 5-3.

Action

Interrupt Masking/Unmasking

What it Does

Contents of IRQ_MSK

Reset

Disables all interrupts individually and globally.

00000000

Enables the RTC interrupt and the power failure interrupt individually. The

interrupts are still globally masked, no interrupt can be triggered yet.

Write 00000101 in IRQ_EN

Write 00000000 in IRQ_EN

Write 10000000 in IRQ_EN

00000101

10000101

10000100

Nothing happens, only bits set at one have an effect.

Enables the interrupts globally. The ITB pin will toggle to 0 if either the

RTC or the power monitor requests an interrupt.

Write 00000001 in IRQ_DIS Disables the RTC interrupt. The power failure interrupt remains active.

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AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

Once the interrupt request is active on the ITB/RDY pin, the microcontroller has to handle it. To

determine the reason for being interrupted, it reads the interrupt status register IRQ_STA (this

action resets ITB/RDY). In this register, each potential interrupt source has a bit which indicates

if it is responsible for triggering the request.

Once the source is identified, the microcontroller performs the handling routine in an application-

dependant manner. It then needs to acknowledge the interrupt source to avoid being interrupted

again for the same reason.

19

6266A–PMAAC–08-Sep-08

6. Register Tables

Default values appear beneath the bit fields in the register description tables that follow.

6.1

System Registers

6.1.1

7-bit Fixed Address for TWI

Register Name:

Access Type:

Address:

TWIADDR

Read-only

0x01

7

ALT

1

6

5

4

3

ADDR

1

2

1

0

1

0

1

• ADDR:

Reads the TWI address currently in use. This field can be used to check the connectivity of the TWI, or to identify the

AT73C224-x device. When ALT bit is 0, ADDR contains the alternate address (0x48). When ALT is 1, ADDR contains the

default address (0x49).

• ALT:

Indicates if the TWI address is the default or the alternate.

0: the default address is selected.

1: the alternate address is selected.

The reset value depends on the configuration of the fuses. When the fuses are blank, the reset value is 0 (manufacturing

default).

6.1.2

Button Status Register

Register Name:

Access Type:

Address:

BT_SR

Read-only

0x02

7

6

5

4

3

2

1

HIGH

0

LOW

0

–

• Low:

0: the button input has not been seen low.

1: the button input has been seen low.

• High:

0: the button input has not been seen high.

1: the button input has been seen high.

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AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.1.3

Button Status Clear Command Register

Register Name:

Access Type:

Address:

BT_SCCR

Write-only

0x03

7

6

5

4

3

2

1

HIGH

0

LOW

0

–

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• Low:

0: no effect.

1: clears LOW in BT_SR.

• High:

0: no effect.

1: clears HIGH in BT_SR.

6.1.4

Button Interrupt Enable Register

Register Name:

Access Type:

Address:

BT_IER

Write-only

0x04

7

6

5

4

3

2

1

HIGH

0

LOW

0

–

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• Low:

0: no effect.

1: the button low interrupt is enabled.

• High:

0: no effect.

1: the button high interrupt is enabled.

21

6266A–PMAAC–08-Sep-08

6.1.5

Button Interrupt Disable Register

Register Name:

Access Type:

Address:

BT_IDR

Write-only

0x05

7

6

5

4

3

2

1

HIGH

0

LOW

0

–

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• Low:

0: no effect.

1: the button low interrupt is disabled.

• High:

0: no effect.

1: the button high interrupt is disabled.

6.1.6

Button Interrupt Mask Register

Register Name:

Access Type:

Address:

BT_IMR

Read-only

0x06

7

6

5

4

3

2

1

HIGH

0

LOW

0

–

• Low:

0: the button low interrupt is disabled.

1: the button low interrupt is enabled.

• High:

0: the button low interrupt is disabled.

1: the button low interrupt is enabled.

6.1.7

Software Shutdown Command Register

Register Name:

Access Type:

Address:

SHUTDN

Write-only

0x07

7

6

5

4

3

2

1

0

LOW

0

–

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

0: no effect.

1: shutdown the whole chip.

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AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.2

PMU Registers

6.2.1

BOOST Command Register

Register Name:

Access Type:

Address:

BST_CLR

Read/Write

0x10

7

6

5

4

3

2

1

0

–

EN(*)

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• EN:

Writing EN to 1 starts the BOOST/SEPIC converter.

Writing En to 0 stops the BOOST/SEPIC converter.

(*): Default value depends on the chosen AT73C224-x device (see Section 5.2).

23

6266A–PMAAC–08-Sep-08

6.2.2

BOOST Configuration Register

Register Name:

Access Type:

Address:

BST_CFG

Read/Write

0x11

7

6

5

4

3

2

1

0

–

ISHORT

1

0

1

• ISHORT:

Selects the overcurrent threshold. When the external sense resistor is 50 mOhms, the lookup table below applies.

ISHORT

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

1101b

Threshold (Amps)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

At the startup, it is recommended to put 1 Amp over current threshold in order not to generate a reset of the product.

24

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.2.3

BOOST Voltage Register

Register Name:

Access Type:

Address:

BST_VOLT

Read/Write

0x12

7

6

5

4

3

2

1

0

–

VOUT(*)

• VOUT:

Selects the output voltage of the regulator following the table below. VOUT should always be higher than VDD1 in BOOS T

configuration (Application schematic 1). It can be programmed lower in SEPIC configuration (Application Schematic 2).

V_OUT[5:0]

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

V_OUT[V]

V_OUT[5:0]

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

V_OUT[V]

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.0

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.0

5.1

5.2

not permitted

3.2

—

(*): Default value depends on the chosen AT73C224-x device (see Section 5.2). The chosen value should always be higher

than the supply of the cell (VDD1).

25

6266A–PMAAC–08-Sep-08

6.2.4

BUCK2 Control Register

Register Name:

Access Type:

Address:

BCK_CTROL

Read/Write

0x13

7

6

5

4

3

2

1

0

–

BYP

EN(*)

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• EN:

Writing EN to 1 starts the BUCK converter.

Writing EN to 0 stops the BUCK converter.

(*): Default value depends on the chosen AT73C224-x device (see Section 5.2).

• BYP:

Writing BYP to 1 puts the BUCK2 output voltage to VDD2.

Writing BYP to 0 configures the BUCK2 in Normal operation (default).

26

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.2.5

BUCK2 Configuration Register

Register Name:

Access Type:

Address:

BCK_CFG

Read/Write

0x14

7

OUTZ

1

6

5

4

3

2

1

0

SLIM

MODE

ISHORT

1

0

1

0

• ISHORT:

Selects the overcurrent threshold. When the external sense resistor is 50 mOhms, the lookup table below applies.

ISHORT

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

Threshold (Amps)

1.01

1.08

1.15

1.22

1.29

1.36

1.43

1.5

1.57

1.64

1.71

1.78

1.85

1.92

1.99

2.06

• MODE:

Selects the PWM pulse skipping mode.

MODE

00

Operation

Auto

01

PWM

10

Pulse skipping

Pass-through

11

• SLIM:

Selects the power-up mode.

0: current limitation.

1: slow start.

27

6266A–PMAAC–08-Sep-08

• OUTZ:

Defines the state of the voltage output when the converter is off.

0: the output is forced to ground.

1: the output is left floating (Hz).

28

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.2.6

BUCK2 Voltage Register

Register Name:

Access Type:

Address:

BCK_VOLT

Read/Write

0x15

7

6

5

4

3

2

1

0

–

VOUT(*)

• VOUT:

Selects the output voltage of the regulator following the table below.

V

_OUT[4:0]

V_OUT[V]

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

V_OUT[4:0]

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

V_OUT[V]

1.28

1.42

1.56

1.7

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

1.86

2.00

2.14

2.29

2.43

2.57

2.71

2.86

3.00

3.14

3.30

3.42

(*): Default value depends on the chosen AT73C224-x device (see Section 5.2).

29

6266A–PMAAC–08-Sep-08

6.2.7

LDO3 Control Register

Register Name:

Access Type:

Address:

LDO3_CTRL

Read/Write

0x16

7

6

5

4

3

2

1

0

–

EN(*)

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• EN:

Writing EN to 1 starts the LDO3 regulator.

Writing EN to 0 stops the LDO3 regulator.

(*): Default value depends on the chosen AT73C224-x device (see Section 5.2).

6.2.8

LDO3 Configuration Register

Register Name:

Access Type:

Address:

LDO3_CFG

Read/Write

0x17

7

6

5

4

3

2

MODE

1

OUTZ

1

0

–

• OUTZ:

Defines the state of the voltage output when the regulator is off.

0: the output is forced to ground.

1: the output is left floating (Hz).

This bit should be at 1 when LDO is on.

• MODE:

0: RF mode, I_MAX= 100 mA.

1: Smoother mode, I_MAX= 200 mA.

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AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.2.9

LDO3 Voltage Register

Register Name:

Access Type:

Address:

LDO3_VOLT

Read/Write

0x18

7

6

5

4

3

2

1

0

–

VOUT(*)

• VOUT

Selects the output voltage of the regulator following the table below.

V

_OUT[3:0]

V_OUT[V]

1.3

1.5

1.6

1.7

1.8

2.5

2.6

2.7

2.8

3.3

4.9

–

1000

0000

0001

0010

0011

0100

0101

0110

0111

1001

1010

others

(*): Default value depends on the chosen AT73C224-x device (see Section 5.2).

31

6266A–PMAAC–08-Sep-08

6.2.10

LDO4 Control Register

Register Name:

Access Type:

Address:

LDO4_CTRL

Read/Write

0x19

7

6

5

4

3

2

1

0

–

EN(*)

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• EN:

Writing EN to 1 starts the LDO4 regulator.

Writing EN to 0 stops the LDO4 regulator.

(*): Default value depends on the chosen AT73C224-x device (seeSection 5.2).

6.2.11

LDO4 Configuration Register

Register Name:

Access Type:

Address:

LDO4_CFG

Read/Write

0x1A

7

6

5

4

3

2

MODE

1

OUTZ

1

0

–

• OUTZ:

Defines the state of the voltage output when the regulator is off.

0: the output is forced to ground.

1: the output is left floating (Hz).

This bit should be at 1 when LDO is on.

• MODE:

0: RF mode, I_MAX= 100 mA.

1: Smoother mode, I_MAX= 200 mA.

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AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.2.12

LDO4 Voltage Register

Register Name:

Access Type:

Address:

LDO4_VOLT

Read/Write

0x1B

7

6

5

4

3

2

1

0

–

VOUT(*)

0

1

• VOUT

Selects the output voltage of the regulator following the table below.

V_OUT[3:0]

1000

0000

0001

0010

0011

0100

0101

0110

0111

1001

1010

others

V_OUT[V]

1.3

1.5

1.6

1.7

1.8

2.5

2.6

2.7

2.8

3.3

4.9

–

(*): Default value depends on the chosen AT73C224-x device (see Section 5.2).

33

6266A–PMAAC–08-Sep-08

6.2.13

PMU Status Register

Register Name:

Access Type:

Address:

PMU_SR

Read-only

0x1C

7

–

0

6

–

0

5

PF2

0

4

PG2

0

3

–

0

2

PF1

0

1

PG1

0

SHORT1

0

• SHORT1:

0: no overcurrent condition.

1: an overcurrent condition has been detected on the BOOST/SEPIC1 converter.

• PG1:

0: no power good condition on BOOST/SEPIC1.

1: the power good condition has been met on BOOST/SEPIC1.

• PF1:

0: no power failure condition on BOOST/SEPIC1.

1: the power failure condition has been met on BOOST/SEPIC1.

• PG2:

0: no power good condition on BUCK2.

1: the power good condition has been met on BUCK2.

• PF2:

0: no power failure condition on BUCK2.

1: the power failure condition has been met on BUCK2.

34

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.2.14

PMU Status Clear Command Register

Register Name:

Access Type:

Address:

PMU_SCCR

Write-only

0x1D

7

6

5

PF2

–

4

PG2

–

3

2

PF1

–

1

PG1

–

0

SHORT1

–

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• SHORT1:

0: no effect.

1: clears SHORT1 in the PMU_SR.

• PG1:

0: no power good condition on BOOST/SEPIC1.

1: clears PG1 in the PMU_SR.

• PF1:

0: no effect.

1: clears PF1 in the PMU_SR.

• PG2:

0: no effect.

1: clears PG2 in the PMU_SR.

• PF2:

0: no effect.

1: clears PF2 in the PMU_SR.

35

6266A–PMAAC–08-Sep-08

6.2.15

PMU Interrupt Enable Register

Register Name:

Access Type:

Address:

PMU_IER

Write-only

0x1E

7

–

6

–

5

PF2

0

4

PG2

0

3

–

2

PF1

0

1

PG1

0

SHORT1

0

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• SHORT1:

0: no effect.

1: the overcurrent detection interrupt on BOOST/SEPIC1 is enabled.

• PG1:

0: no effect.

1: the power good interrupt of BOOST/SEPIC1 is enabled.

• PF1:

0: no effect.

1: the power fail interrupt of BOOST/SEPIC1 is enabled.

• PG2:

0: no effect.

1: the power good interrupt of BUCK2 is enabled.

• PF2:

0: no effect.

1: the power fail interrupt of BUCK2 is enabled.

36

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.2.16

PMU Interrupt Disable Register

Register Name:

Access Type:

Address:

PMU_IDR

Write-only

0x1F

7

6

5

PF2

–

4

PG2

–

3

2

PF1

–

1

PG1

–

0

SHORT1

–

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• SHORT1:

0: no effect.

1: the overcurrent detection interrupt on BOOST/SEPIC1 is disabled.

• PG1:

0: no effect.

1: the power good interrupt of BOOST/SEPIC1 is disabled.

• PF1:

0: no effect.

1: the power fail interrupt of BOOST/SEPIC1 is disabled.

• PG2:

0: no effect.

1: the power good interrupt of BUCK2 is disabled.

• PF2:

0: no effect.

1: the power fail interrupt of BUCK2 is disabled.

37

6266A–PMAAC–08-Sep-08

6.2.17

PMU Interrupt Mask Register

Register Name:

Access Type:

Address:

PMU_IMR

Read-only

0x20

7

6

5

PF2

0

4

PG2

0

3

2

PF1

0

1

PG1

0

SHORT1

0

–

A minimum of 3 clock cycles of 15 kHz clock must be waited after any read operation before doing a new register access.

• SHORT1:

0: the overcurrent detection interrupt on BOOST/SEPIC1 is disabled.

1: the overcurrent detection interrupt on BOOST/SEPIC1 is enabled.

• PG1:

0: the power good interrupt of BOOST/SEPIC1 is disabled.

1: the power good interrupt of BOOST/SEPIC1 is enabled.

• PF1:

0: the power fail interrupt of BOOST/SEPIC1 is disabled.

1: the power fail interrupt of BOOST/SEPIC1 is enabled.

• PG2:

0: the power good interrupt of BUCK2 is disabled.

1: the power good interrupt of BUCK2 is enabled.

• PF2:

0: the power fail interrupt of BUCK2 is disabled.

1: the power fail interrupt of BUCK2 is enabled.

38

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.3

Interrupt Registers

6.3.1

Interrupt Enable Register

Register Name:

Access Type:

Address:

IRQ_EN

Write-only

0x30

7

ALL

–

6

5

DC2

–

4

DC1

–

3

2

PWR

–

1

PB

–

0

RTC

–

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• RTC:

Enables the RTC interrupt when written to 1.

Writing 0 has no effect.

• PB:

Enables the push-button interrupt when written to 1.

Writing 0 has no effect.

• PWR:

Enables the power failure interrupt when written to 1.

Writing 0 has no effect

• DC1:

Enables the BOOST/SEPIC1 interrupt when written to 1.

Writing 0 has no effect.

• DC2:

Enables the BUCK2 interrupt when written to 1.

Writing 0 has no effect.

• ALL:

Writing to 1 globally enables all the interrupt sources that had been previously enabled individually. The interrupt setting for

each source is restored.

Writing 0 has no effect.

39

6266A–PMAAC–08-Sep-08

6.3.2

Interrupt Disable Register

Register Name:

Access Type:

Address:

IRQ_DIS

Write-only

0x31

7

ALL

–

6

5

DC2

–

4

DC1

–

3

2

PWR

–

1

PB

–

0

RTC

–

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

• RTC:

Disables the RTC interrupt when written to 1.

Writing 0 has no effect.

• PB:

Disables the push-button interrupt when written to 1.

Writing 0 has no effect.

• PWR:

Disables the power failure interrupt when written to 1.

Writing 0 has no effect

• DC1:

Disables the BOOST/SEPIC1 interrupt when written to 1.

Writing 0 has no effect.

• DC2:

Disables the BUCK2 interrupt when written to 1.

Writing 0 has no effect.

• ALL:

Writing to 1 globally disables all the interrupt sources. The individual setting of each interrupt source is saved.

Writing 0 has no effect.

40

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.3.3

Interrupt Mask Register

Register Name:

Access Type:

Address:

IRQ_MSK

Read-only

0x32

7

ALL

0

6

–

0

5

DC2

0

4

DC1

0

3

–

0

2

PWR

0

1

PB

0

RTC

0

This register summarizes the result of the successive interrupt enable/disable commands performed by writing into

IRQ_EN/IRQ_DIS.

• RTC:

0: the RTC interrupt is masked.

1: the RTC interrupt is unmasked.

• PB:

0: the push-button interrupt is masked.

1: the push-button interrupt is unmasked.

• PWR:

0: the power failure interrupt is masked.

1: the power failure interrupt is unmasked.

• DC1:

0: the BOOST/SEPIC1 interrupt is masked.

1: the BOOST/SEPIC1 interrupt is unmasked.

• DC2:

0: the BUCK2 interrupt is masked.

1: the BUCK2 interrupt is unmasked.

• ALL:

0: the interrupt sources are globally masked.

1: the interrupt sources are globally unmasked.

41

6266A–PMAAC–08-Sep-08

6.3.4

Interrupt Status Register

Register Name:

Access Type:

Address:

IRQ_STA

Read-only

0x33

7

–

0

6

–

0

5

DC2

0

4

DC1

0

3

–

0

2

PWR

0

1

PB

0

RTC

0

A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access.

Reading IRQ de-asserts the ITB signal.

• RTC:

1: signals a pending interrupt request from the RTC.

• PB:

1: signals a pending interrupt request from the push-button.

• PWR:

1: signals a pending interrupt request from the power monitor.

• DC1:

1: signals a pending interrupt request from the BOOST/SEPIC1.

• DC2:

1: signals a pending interrupt request from the BUCK2.

42

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.4

RTC Registers

6.4.1

RTC Control Register

Register Name:

Access Type:

Address:

RT_CR

Read/Write

0x40

7

6

5

4

3

2

1

0

CALEVSEL

TIMEVSEL

–

UPDCAL

0

UPDTIM

0

• UPDTIM:

Writing 1 requests the RTC to stop the time counter so that it can be safely updated. The time counter is actually stopped

only when ACKUPD is set in RTC_SR.

Writing 0 restarts the time counter.

• UPDCAL:

Writing 1 requests the RTC to stop the calendar counter so that it can be safely updated. The calendar counter is actually

stopped only when ACKUPD is set in RTC_SR.

Writing 0 restarts the calendar counter.

• TIMEVSEL:

Selects the type of event to cause TIMEV to change in RTC_SR.

00

01

10

11

minute change

hour change

every day at midnight

every day at noon

• CALEVSEL:

Selects the type of event to cause CALEV to change in RTC_SR.

every

Monday

at time

00:00:00

00

01

week change

month change

year change

every 1st of

each month 00:00:00

at time

10

11

every 1st of

January

at time

00:00:00

43

6266A–PMAAC–08-Sep-08

6.4.2

RTC Reset Register

Register Name:

Access Type:

RT_RR

Read/Write

Address:

0x41

7

RST

0

6

5

4

3

2

1

0

–

RST:

RST = 0, Normal Operation

RST=1, Reset the RTC

6.4.3

RTC Mode Register

Register Name:

Access Type:

Address:

RT_MR

Read/Write

0x44

7

6

5

4

3

2

1

0

HRMOD

0

–

• HRMOD:

0: 24-hour mode.

1: 12-hour mode.

44

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

The three Time writing registers are only writable concomitantly and must be written in the order as shown below:

1. RT_SEC

2. RT_MIN

3. RT_HOUR

6.4.4

Real-time Second Register

Register Name:

Access Type:

Address:

RT_SEC

Read/Write

0x48

7

6

5

4

3

SEC

0

2

1

0

–

0

• SEC:

The range is 0-59 encoded in Binary Coded Decimal (BCD). The lowest four bits encode the units, the higher bits encode

the tens.

This field must not be written unless the time counter has been stopped.

6.4.5

Real-time Minute Register

Register Name:

Access Type:

Address:

RT_MIN

Read/Write

0x49

7

6

5

4

3

MIN

0

2

1

0

–

0

• MIN

The range is 0-59 encoded in BCD. The lowest four bits encode the units, the higher bits encode the tens. This field must

not be written unless the time counter has been stopped.

6.4.6

Real-time Hour Register

Register Name:

Access Type:

Address:

RT_HOUR

Read/Write

0x4A

7

6

5

4

3

2

1

0

–

AMPM

HOUR

0

• HOUR:

Depending on bit AMPM, the range can be 1-12 or 0-23, encoded in BCD. The lowest four bits encode the units, the higher

bits encode the tens. This field must not be written unless the time counter has been stopped.

• AMPM:

This bit controls/reflects the AM/PM indicator in 12-hour mode.

0: AM.

1: PM.

45

6266A–PMAAC–08-Sep-08

The four Date writing registers are only writable concomitantly and must be written in the order as shown below:

1. RT_CENT

2. RT_YEAR

3. RT_MONTH

4. RT_DATE

6.4.7

Real-time Century Register

Register Name:

Access Type:

Address:

RT_CENT

Read/Write

0x4C

7

6

5

4

3

2

1

0

–

CENT

0

1

0

1

• CENT:

The range is 19 - 20, encoded in BCD. The lowest four bits encode the units, the higher bits encode the tens.

6.4.8 Real-time Year Register

Register Name:

Access Type:

Address:

RT_YEAR

Read/Write

0x4C

7

6

5

4

3

2

1

0

YEAR

1

0

1

0

• YEAR:

The range is 1 - 12, encoded in BCD. The lowest four bits encode the units, the higher bits encode the tens.

6.4.9 Real-time Month Register

Register Name:

Access Type:

Address:

RT_Month

Read/Write

0x4E

7

6

5

4

3

2

MONTH

0

1

0

DAY

1

0

1

• MONTH:

The range is 1 - 12, encoded in BCD. The lowest four bits encode the units, the higher bits encode the tens.

• DAY:

The range is 1-7 and represents the day of the week. The relationship between the coding of this field and the actual day of

the week, is user-defined. Especially, writing to this bit has no effect on the date counter.

46

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.4.10

Real-time Date Register

Register Name:

Access Type:

Address:

RT_DATE

Read/Write

0x4F

7

6

5

4

3

2

DATE

0

1

0

DAY

1

0

1

0

• DATE:

The range is 1 - 31, encoded in BCD and represents the day of the month. The lowest four bits encode the units, the higher

bits encode the tens.

47

6266A–PMAAC–08-Sep-08

The three Time Alarm writing registers are only writable concomitantly and must be written in the order as shown below:

1. RT_SECA

2. RT_MINA

3. RT_HOURA

6.4.11

Real-time Second Alarm Register

Register Name:

Access Type:

Address:

RT_SECA

Read/Write

0x50

7

SECEN

0

6

5

4

3

SEC

0

2

1

0

• SEC:

This field is the alarm field corresponding to the BCD-encoded second counter.

• SECEN

0: the second-matching alarm is disabled.

1: the second-matching alarm is enabled.

6.4.12

Real-time Minute Alarm Register

Register Name:

Access Type:

Address:

RT_MINA

Read/Write

0x51

7

MINEN

0

6

5

4

3

MIN

0

2

1

0

• MIN:

This field is the alarm field corresponding to the BCD-encoded minute counter.

• MINEN

0: the minute-matching alarm is disabled.

1: the minute-matching alarm is enabled.

48

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.4.13

Real-time Hour Alarm Register

Register Name:

Access Type:

Address:

RT_HOURA

Read/Write

0x52

7

HOUREN

0

6

5

4

3

2

1

0

AMPM

HOUR

0

• HOUR:

This field is the alarm field corresponding to the BCD-encoded hour counter.

• AMPM:

This field is the alarm field corresponding to the BCD-encoded hour counter.

• HOUREN

0: the hour-matching alarm is disabled.

1: the hour-matching alarm is enabled.

49

6266A–PMAAC–08-Sep-08

The two Date Alarm writing registers are only writable concomitantly and must be written in the order as shown below:

1. RT_MONTHA

2. RT_DATEA

6.4.14

Real-time Month Alarm Register

Register Name:

Access Type:

Address:

RT_MONTHA

Read/Write

0x56

7

MTHEN

0

6

5

4

3

2

MONTH

0

1

0

–

0

1

• MONTH:

This field is the alarm field corresponding to the BCD-encoded month counter.

• MTHEN

0: the month-matching alarm is disabled.

1: the month-matching alarm is enabled.

6.4.15

Real-time DATE Alarm Register

Register Name:

Access Type:

Address:

RT_DATEA

Read/Write

0x56

7

DATEEN

0

6

5

4

3

2

1

0

–

DATE

0

1

• DATE:

This field is the alarm field corresponding to the BCD-encoded day of the month counter.

• DATEEN:

0: the day of the month-matching alarm is disabled.

1: the day of the month-matching alarm is enabled.

50

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.4.16

RTC Status Register

Register Name:

Access Type:

Address:

RTC_SR

Read-only

0x58

7

6

5

4

CALEV

0

3

TIMEV

0

2

SEC

0

1

ALARM

0

ACKUPD

0

–

• ACKUPD:

0: time and calendar registers should not be updated.

1: time and calendar can be updated safely (clock stopped).

• ALARM:

0: no alarm matching condition occurred.

1: an alarm matching condition occurred.

• SEC:

0: no second event has occurred since last clear.

1: at least one second event occurred since last clear.

• TIMEV:

0: no time event has occurred since last clear.

1: at least one time event occurred since last clear.

The time event is selected by the TIMEVSEL field in RTC_CR and can be any of the following events: minute change, hour

change, noon, midnight (day change).

• CALEV:

0: no calendar event occurred since last clear.

1: at least one calendar event occurred since last clear.

The calendar event is selected in the CALEVSEL field in RTC_CR and can be any of the following events: week change,

month change, or year change.

51

6266A–PMAAC–08-Sep-08

6.4.17

RTC Status Clear Command Register

Register Name:

Access Type:

Address:

RTC_SCCR

Write-only

0x5C

7

6

5

4

CALCLR

0

3

TIMCLR

0

2

SECCLR

0

1

ALRCLR

0

ACKCLR

0

–

• ACKCLR:

0: no effect.

1: clears the ACKUPD bit in RTC_SR.

• ALCLR:

0: no effect.

1: clears the ALARM bit RTC_SR.

• SECCLR:

0: no effect.

1: clears the SEC bit RTC_SR.

• TIMCLR:

0: no effect.

1: clears the TIMEV bit RTC_SR.

• CALCR:

0: no effect.

1: clears the CALEV bit RTC_SR.

52

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.4.18

RTC Interrupt Enable Register

Register Name:

Access Type:

Address:

RTC_IER

Write-only

0x60

7

6

5

4

CALEN

0

3

TIMEN

0

2

SECEN

0

1

ALREN

0

ACKEN

0

–

• ACKEN:

0: no effect.

1: the acknowledge for update interrupt is enabled.

• ALREN:

0: no effect.

1: the alarm interrupt is enabled.

• SECEN:

0: no effect.

1: the second periodic interrupt is enabled.

• TIMEN:

0: no effect.

1: the selected time event interrupt is enabled.

• CALEN:

0: no effect.

1: the selected calendar event interrupt is enabled.

53

6266A–PMAAC–08-Sep-08

6.4.19

RTC Interrupt Disable Register

Register Name:

Access Type:

Address:

RTC_IDR

Write-only

0x64

7

6

5

4

CALDIS

0

3

TIMDIS

0

2

SECDIS

0

1

ALRDIS

0

ACKDIS

0

–

• ACKDIS:

0: no effect.

1: the acknowledge for update interrupt is disabled.

• ALRDIS:

0: no effect.

1: the alarm interrupt is disabled.

• SECDIS:

0: no effect.

1: the second periodic interrupt is disabled.

• TIMDIS:

0: no effect.

1: the selected time event interrupt is disabled.

• CALDIS:

0: no effect.

1: the selected calendar event interrupt is disabled.

54

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

6.4.20

RTC Interrupt Mask Register

Register Name:

Access Type:

Address:

RTC_IMR

Read-only

0x68

7

6

5

4

CAL

0

3

TIM

0

2

SEC

0

1

ALR

0

ACK

0

–

• ACK:

0: the acknowledge for update interrupt is disabled.

1: the acknowledge for update interrupt is enabled.

• ALR:

0: the alarm interrupt is disabled.

1: the alarm interrupt is enabled.

• SEC:

0: the second periodic interrupt is disabled.

1: the second periodic interrupt is enabled.

• TIM:

0: the selected time event interrupt is disabled.

1: the selected time event interrupt is enabled.

• CAL:

0: the selected calendar event interrupt is disabled.

1: the selected calendar event interrupt is enabled.

55

6266A–PMAAC–08-Sep-08

6.4.21

RTC Valid Entry Register

Register Name:

Access Type:

Address:

RTC_VER

Read-only

0x6C

7

6

5

4

3

2

1

0

–

NVCALA

NVTIMA

NVCAL

NVTIM

• NVTIM:

0: no invalid data has been detected in the time registers.

1: invalid data has been detected.

• NVCAL:

0: no invalid data has been detected in the calendar registers.

1: invalid data has been detected.

• NVTIMA:

0: no invalid data has been detected in the time alarm registers.

1: invalid data has been detected.

• NVCALA:

0: no invalid data has been detected in the calendar alarm registers.

1: invalid data has been detected.

56

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

7. Electrical Characteristics

With external components as listed in Table 4-1, Ta = -40°C to 85°C typical values are at Ta =

25°C (unless otherwise specified).

7.1

Absolute Maximum Ratings

Table 7-1.

Absolute Maximum Ratings

*NOTICE:

Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at these or other conditions beyond those indi-

cated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

Operating Temperature (Industrial).............-40°C to + 85°C

Storage Temperature..................................-55°C to + 150°C

Power Supply Input........................................-0.3V to + 5.5V

I/O Input.......................................................... -0.3V to + 5.5V

ESD (all pins)-..................................................................2 KV

7.2

Recommended Operating Conditions

Table 7-2.

Parameter

Recommended Operating Conditions

Condition

Min

-40

2.8

Max

85

Unit

°C

Operating Temperature

Power Supply Input

5.25

V

57

6266A–PMAAC–08-Sep-08

7.3

Digital I/Os

Digital I/Os are supplied by VDDIO. VDDIO is an input and must be externally connected.

.

Table 7-3.

Symbol

VDDIO

VDDIO Referred Digital I/Os

Parameter

Conditions

Min

Typ

Max

Unit

Operating Supply Voltage

1.75

3.6

5.25

V

0.3x

V_IL

Input Low Level Voltage

Input High Level Voltage

Output Low Level Voltage

-0.3

V

VDDIO

0.7x

VDDIO

+ 0.3

V_IH

V_OL

VDDIO

0.75x

VDDIO

0.25x

V_OH

Io

Output high Level Voltage

Output Current

V

VDDIO

8

mA

kΩ

Pull-Up or Pull Down

resistance

Rp

when applicable

90

120

150

VDDIO referred pins EN, D1, D3, D4: CMOS inputs. Only VIH and VIL parameters are

applicable.

VDDIO referred pins POK: CMOS output. Only VOL, VOH parameters are applicable.

VDDIO referred pin ITB, D2: CMOS BiDir. All parameters applicable.

7.4

Current Consumption Versus Modes

Table 7-4.

Status

Quiescent Current in Different Operating Modes

Conditions

Battery Current

Typ

Max

Off

No battery is present

N/A

No Main Battery is present

Backup battery present (and charged):

. Running:

Backup mode

RTC (dig + oscillator 32 kHz) - supply: vbackup pin

1 µA

2 µA

Main Battery plugged in and higher than 2.8V

Backup battery present (and charged)

. Power supplies off (BOOST1, BUCK2, LDO3, LDO4)

. Running:

Stand by

RTC, LDO_RTC - supply: vbat_ldortc

POR, LPBG, VMON - supply: vdd0 pin

4µA

9µA

7µA

17µA

58

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

7.5

BOOST1: Step-up Converter

Table 7-5.

Symbol

VDD1

Fs

BOOST1 Electrical Characteristics

Parameter

Conditions

Min

2.8

Typ

3.6

Max

5.25

1400

1

Unit

V

Operating Supply Voltage

Converter Frequency

Load Current

400

900

kHz

A

I_O

BST_VOLT register (@12) - Step 100 mV

VDD1 < VO1

VO1

Output Voltage

3.2

-10

5.2

V

Error

Output voltage precision

Shutdown Current

Iload > 100 mA

-10

1

%

µA

A

I_sc

BST_CLR register (@10); EN = 0

BST_CFG register (@11)

I_O= 1 A, VDD1 = 2.8V, VO1 = 3.3V

I_O= 1 A, VDD1 = 3.3V, VO1 = 5.2V

No load

I_LIM

Current Limitation

0.5

7⁽¹⁾

η2.8_3.3_1A

h3.6_5.2_1A

t_START

Efficiency at VDD1 = 2.8 V

Efficiency at VDD1 = 3.6 V

Start-up Time

90

85

%

µs

200

peak-to-peak, I_O= 1 A, VO1 = 5.2V

Bandwidth = 20 MHz

∆V_{O1_5.2V}

Ripple Voltage

200

50

mV

Static Line Regulation

Static Load Regulation

VDD1: 2.8 to 4.2V - I_O= 1 A - VO1 = 5.2V

VDD1: 3.6V - I_O: 100 mA to 900 mA -

VO1 = 5.2V

Note:

1. Before the BOOST is turned on, it is recommended to establish low current limitation (typic: 1 Amp) to avoid current peak on

main supply.

59

6266A–PMAAC–08-Sep-08

7.5.1

BOOST1: Typical Characteristics

Figure 7-1. Efficiency BOOST1 - VO1 = 5V -

100

95

90

85

80

75

70

65

VDD1 = 4.2V

VDD1 = 3.6V

VDD1 = 3V

VDD1 = 2.8V

60

0.01

0.1

1

Iload (A)

60

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

Figure 7-2. Load Regulation BOOST1 - VO1 = 5V -

5.32

5.3

5.28

5.26

5.24

5.22

5.2

5.18

5.16

5.14

5.12

5.1

VDD1 = 4.2V

VDD1 = 3.6V

VDD1 = 3V

5.08

5.06

5.04

5.02

VDD1 = 2.8V

1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Iload (A)

The BOOST1 cell can be implemented using proper external components. (See Figure 4-3

“Application Schematic 3: BOOST in SEPIC Configuration (BUCK/BOOST)”.)

61

6266A–PMAAC–08-Sep-08

7.6

BUCK2: Step-down Converter

Table 7-6.

BUCK2 Electrical Characteristics

Symbol Parameter

Conditions

Min

2.8

Typ

3.6

Max

5.25

1400

0.5

Unit

V

VDD2

Fs

Operating Supply Voltage

Converter Frequency

Load Current

PWM mode

400

900

kHz

A

I_LOAD

BCK_VOLT register (@15) - Step 100mV

VDD2 > (VO2 + 0.2V)

VO2

Output Voltage

0.9⁽¹⁾

-10

3.4

V

Error

I_SC

Output Voltage Precision

Shutdown Current

10

6

%

µA

A

BCK_CTROL register (@13), EN = 0

BCK_CTROL register (@13), EN = 1, clock not present

BCK_CFG register (@14)

1

I_STB

I_MAX

Stand-by Current

20

50

2

Short Circuit Current

1

PWM – Pulse SKipping

Current Threshold

I_PWM-PSK

Automatic mode- VDD2 = 3.6V- VO2 = 1.8V

70

mA

∆v

Ripple Voltage

Rise Time

PWM mode

10

1

mV

ms

T_R

Bandgap already started, slow-start power up selected

I_LOAD= 500 mA, VDD2 from 2.8V to 5V

PWM mode

∆V_DC

Static Line Regulation

Static Load Regulation

80

40

mV

1 mA <iload<500 mA,

PWM mode

∆V_DC

Note:

1. for device commanded in Dynamic Mode only. For devices commanded in Static Mode, the minimum voltage is 1.8V.

The BUCK2 is a Pulse Width Modulator (PWM) / Pulse-Skipping (PSK) synchronous regulator

that can be used to provide an accurate 0.9V to 3.4V programmable output voltage at 500 mA of

maximum load current.

Integrated current sensing is used to sense the DC/DC converter load current used for the over-

current circuit protection and for the PWM / PSK mode selector.

By default, the BUCK2 is in Automatic Mode: according to the load current value, the regulator is

either in Pulse-Skipping mode (light load) or in PWM mode (high load). In dynamic mode, the

user can select PWM or PSK mode, using the bits 4 and 5 of the BCK_CFG register (see Sec-

tion 6 Register Tables).

Note that the Automatic mode should not be used for output voltages below 1.8V.

62

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

7.6.1

BUCK2: Typical Characteristics

Figure 7-3. Efficiency Manual/Automatic Modes

Efficiency VO2 = 1.2V - Manual Mode: PSK/PWM

Efficiency VO2 = 0.9V - Manual Mode: PSK/PWM

100

95

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

90

VDD2 = 2.8V

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

VDD2 = 2.8V

VDD2 = 3.6V

VDD2 = 4.2V

VDD2 = 3.6V

VDD2 = 4.2V

VDD2 = 5V

VDD2 = 2.8V

VDD2 = 3.6V

VDD2 = 4.2V

VDD2 = 5V

VDD2 = 2.8V

VDD2 = 3.6V

PWM

PSK

PWM

PSK

VDD2 = 4.2V

VDD2 = 5V

0

0.001

0.01

0.1

1

0.001

0.01

0.1

1

Iload (A)

Efficiency VO2 = 1.8V - Manual Mode: PSK/PWM

Efficiency VO2 = 3.3V - Manual Mode: PSK/PWM

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

VDD2 = 4.2V

VDD2 = 2.8V

VDD2 = 3.6V

VDD2 = 4.2V

VDD2 = 5V

VDD2 = 2.8V

PWM

PSK

PWM

PSK

VDD2 = 3.6V

VDD2 = 4.2V

VDD2 = 5V

VDD2 = 4.2V

VDD2 = 5V

0

0.001

0.01

0.1

1

0.001

0.01

0.1

1

Iload (A)

Efficiency VO2 = 3.3V - Automatic Mode

Efficiency VO2 = 1.8V - Automatic Mode

100

95

90

85

80

75

70

65

60

55

50

45

100

95

90

85

80

75

70

65

60

VDD2 = 4.2V

VDD2 = 5V

VDD2 = 2.8V

VDD2 = 3.6V

VDD2 = 4.2V

VDD2 = 5V

0.001

0.01

0.1

1

0.001

0.01

0.1

1

Iload (A)

63

6266A–PMAAC–08-Sep-08

7.6.2

BUCK2: Load Regulation of VO2

Figure 7-4. Load Regulation

Load Regulation: VO2 = 0.9V (PWM mode)

Load Regulation: VO2 = 1.2V (PWM mode)

VDD2 = 2.8V

1.23

1.22

1.21

1.2

0.93

0.92

0.91

0.9

VDD2 = 2.8V

VDD2 = 3.6V

VDD2 = 4.2V

VDD2 = 3.6V

VDD2 = 4.2V

1.19

1.18

1.17

1.16

1.15

0.89

0.88

0.87

0.86

0.85

VDD2 = 5V

VDD2 = 5.5V

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

I load (A)

Load Regulation: VO2 = 3.3V (PWM mode)

Load Regulation: VO2 = 1.8V (PWM Mode)

VDD2 = 2.8V

3.3

1.84

3.29

3.28

3.27

3.26

3.25

3.24

3.23

3.22

1.82

1.8

VDD2 = 4.2V

VDD2 = 3.6V

VDD2 = 4.2V

1.78

1.76

1.74

1.72

VDD2 = 5.5V

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

I load (A)

64

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

7.7

LDO3 & LDO4

LDO3 and LDO4 are low-drop-out voltage regulators that can provide a 1.3V, 1.5V to 1.8V (step

100 mV), 2.5V to 2.8V (100 mV step) or 3.3V output voltage.

Two kinds of applications are defined: “RF” mode (high PSRR and low noise) with 100 mA max-

imum load and “Smoother” mode with 200 mA maximum load.

By default, the LDOs are configured in RF mode. If the load is higher than 100 mA, the user

should pass into Smoother mode (see the register tables in Section 6.2.8 ”LDO3 Configuration

Register” and Section 6.2.11 ”LDO4 Configuration Register”).

An external 2.2 µF ceramic capacitor is needed for the stability of each LDO.

Table 7-7.

Symbol

VDD3&4

I_{LOAD_S}

LDO3 and LDO4 Electrical Characteristics

Parameter

Conditions

Min

2.8

0

Typ

Max

5.25

200

100

Unit

V

Operating Supply Voltage

Smoother Load current

RF Load current

3.6

In Smoother mode

In RF mode

mA

I_{LOAD_RF}

0

Selection in LDO3_VOLT @ 18 and

LDO4_VOLT @ 1B

VO3,

VO4

Output Voltage

1.3

-8

3.3

V

VDD3 > VO3 + 200mV

VDD4 > VO4 + 200mV

∆V_o

Accuracy

I_LOAD=10mA

8

1

%

GND output

I_SC

Shutdown Current

µA

(LDO3_CFG@17 and LDO4_CFG@1A)

I_QQ

Quiescent Current

Rise Time

No load

20

100

10

µA

µs

t_R

∆V_DC

Line Regulation Static

Load Regulation Static

2.8V < VDD3 < 5.25V, full load

10 mA <I_LOAD<100 mA

mV

10

5

In RF mode

n

Output Noise

1.5

µVrms

Bandwidth: [22 - 80kHz]

In RF mode:

I

_LOAD=100mA, 100 Hz

70

65

55

45

dB

PSRR

Power Supply Rejection Ratio

I_LOAD=100mA, 1kHz

I_LOAD=100mA, 10kHz

I_LOAD=100mA, 100kHz

65

6266A–PMAAC–08-Sep-08

7.7.1

LDO3 and LDO4: Typical Characteristics

Figure 7-5. LDO Load Regulation

Load regulation VO3 = 1.8V

Load regulation VO3 = 3.3V

1.771

1.77

3.276

3.275

3.274

3.273

3.272

3.271

3.27

1.769

1.768

1.767

1.766

1.765

1.764

1.763

1.762

1.761

VDD3 = 5V

VDD3 = 4.2V

VDD3 = 3.6V

VDD3 = 3V

VDD3 = 2.8V

VDD3 = 3.6V

VDD3 = 4.2V

VDD3 = 5V

3.269

3.268

3.267

3.266

3.265

3.264

0

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27

0.3

0

0.03

0.06

0.09

0.12

0.15

0.18

Iload (A)

0.21

0.24

0.27

0.3

Iload (A)

Shown below is VO3 Ripple (same as VO4) in response to a load current pulse from 10 mA to

200 mA.

Channel 2: VO3 = 1.8V and VO3 = 3.3V (50mV/div)

Channel 1: Iload = 10 mA - 200 mA (100 mA/div)

66

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

7.8

Real-time Clock (RTC)

The Real-time Clock architecture is shown in Figure 7-6 and is comprised of the following

blocks: 2.6V LDO_RTC voltage regulator with backup switch, RTC oscillator and RTC block.

7.8.1

Block Diagram

Figure 7-6.

RTC Block Diagram

AT73C224-x

VDD0

VMON

VBAT_LDORTC

VDD0 < 2.8V

switch open

LDO_RTC off

R2

LDO

RTC

2.6V

VBACKUP

Recharchable

Backup

Battery 2.5V

(NBL type)

C11

XIN

RTC

Clock

X1

RTC

OSC

32.768 kHz

crystal

RTC

XOUT

D0 to D4

Serial

Interface

The LDO_RTC is used to charge the backup battery at 2.6V. When the main battery is plugged

in, the LDO is enabled and the backup switch is closed, thus charging the battery. If the

VBACKUP initial value is lower than the minimum backup voltage admissible (1.8V typical), an

active low reset is generated on reset signal.

The C11 capacitor is used for LDO compensation while the R2 resistor limits the charge current

for the backup battery.

The RTC oscillator is suited to work with a 32.768 kHz crystal oscillator and generates the

32.768 kHz clock for the RTC. The RTC block provides seconds, minutes, hours, days, date,

month, and year information. RTC time data is stored into a register that can be accessed via

the AT73C224-x device serial interface.

67

6266A–PMAAC–08-Sep-08

7.8.2

LDO RTC

Table 7-8.

Symbol

V_{BAT_LDORTC}

V_BACKUP

I_OUT

LDO RTC Electrical Characteristics

Parameter

Conditions

Min

2.8

Typ

Max

5.25

2.65

2

Unit

V

Operating Supply Voltage

Output Voltage

Vbat_ldortc present

Dc load current

en = 1

2.55

2.6

V

Load Current

mA

µA

I_QQ

Battery Quiescent Current

3

5

Backup Battery Quiescent

Current

I_BKQQ

en = 0

200

300

nA

I_SC

T_S

Shutdown Current

Start-up Time

1

µA

ms

V

V_TH

Reset Threshold

reset is active low

1.8

The LDO_Backup is a low drop out voltage regulator that is used to charge a 2.5V RTC

rechargeable backup battery (type NBL621). The max load current is 2 mA. An external 1 µF

ceramic capacitor (C11) is needed for compensation.

7.8.3

RTC Oscillator

Table 7-9.

Symbol

V_BACKUP

F_CK

RTC Oscillator Electrical Characteristics

Parameter

Conditions

Min

Typ

Max

Unit

Supply voltage

Operating frequency

Duty cycle

1.75

2.65

32.768

50

kHz

%

Duty

40

60

900

360

0.1

5

Ton

Startup time

ms

V_SIN

Level sinus wave on xin

Drive level

R_S= 50 KΩ

160

260

0.8

mVpp

µW

D_RV

R_S= 50 KΩ

OFF

nA

I

Current dissipation

ON

2

µA

A_CC

Accuracy

T = 25 °C

3

mn/month

kΩ

R_S

Equivalent series resistance

Motional capacitance

Shunt capacitance

Load capacitance

Crystal @ 32.768kHz

50

3

C_MT

1

0.6

6

fF

C_SHUNT

C_LOAD

2

pF

12.5

pF

The RTC Oscillator is a low-frequency, 2-Pad, Pierce-type Xtal oscillator, optimized for 32.768

kHz crystal. For operation with 6 pF load capacitance crystals, no external components are

needed on “xin” and “xout”. It may be necessary to add external capacitors on “xin” and “xout” to

ground in special cases, for example, to exactly set the frequency or for crystals with a load

capacitance superior to 6 pF. The “clock” output is low during standby. “xin” and “xout” must not

be used to drive other circuitry.

68

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

7.9

VINT

One external capacitor (47 0nF) is necessary on VINT pin for functionality of the internal LDO

supply. This voltage should not be used by the user.

69

6266A–PMAAC–08-Sep-08

8. Package Drawing

Figure 8-1. QFN 32-lead Package Drawing (all dimensions in millimeters)

R-QFN032_H

70

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

9. Revision History

Change

Request

Ref.

Doc. Rev.

Comments

6266A

First issue.

71

6266A–PMAAC–08-Sep-08

72

AT73C224

6266A–PMAAC–08-Sep-08

AT73C224

Table of Contents

Features..................................................................................................... 1

Description ............................................................................................... 1

Block Diagram .......................................................................................... 3

Pinout ........................................................................................................ 4

Application examples .............................................................................. 5

Detailed Description ................................................................................ 9

1

2

3

4

5

5.1

5.2

5.3

Core ...................................................................................................................9

Automatic Start-up Sequences and Shut-down ...............................................10

Digital Control and Protocol .............................................................................13

6

7

Register Tables ...................................................................................... 20

6.1

6.2

6.3

6.4

System Registers ............................................................................................20

PMU Registers ................................................................................................23

Interrupt Registers ...........................................................................................39

RTC Registers .................................................................................................43

Electrical Characteristics ...................................................................... 57

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Absolute Maximum Ratings .............................................................................57

Recommended Operating Conditions .............................................................57

Digital I/Os .......................................................................................................58

Current Consumption Versus Modes ..............................................................58

BOOST1: Step-up Converter ...........................................................................59

BUCK2: Step-down Converter .........................................................................62

LDO3 & LDO4 .................................................................................................65

Real-time Clock (RTC) ....................................................................................67

VINT ................................................................................................................69

8

9

Package Drawing ................................................................................... 70

Revision History ..................................................................................... 71

Table of Contents....................................................................................... i

i

6266A–PMAAC–08-Sep-08

ii

AT73C224

6266A–PMAAC–08-Sep-08

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

Atmel Europe

Le Krebs

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

Technical Support

Sales Contacts

www.atmel.com

pmaac@atmel.com

www.atmel.com/contacts/

www.atmel.com/PowerManagement Atmel techincal support

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

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6266A–PMAAC–08-Sep-08


型号：	AT73C224-B_14
厂家：	ATMEL
描述：	Ultra-low Power Real-time Clock (RTC) and Backup Battery Management 电池
文件：	总75页 (文件大小：1254K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT73C224-B_14 [ATMEL]

相关型号：

AT73C224-C

AT73C224-C_14

AT73C224-D

AT73C224-D_14

AT73C224-E

AT73C224-E_14

AT73C224-F

AT73C224-F_14

AT73C224-G

AT73C224-G_14

AT73C224-H

AT73C224-H_14