AT68166HT-YM25MQ [ATMEL]
Rad Hard 16 MegaBit 3.3V 5V Tolerant SRAM Multi-Chip Module; 抗辐射16兆3.3V 5V容错SRAM的多芯片模块
| 型号： | AT68166HT-YM25MQ |
| 厂家： | 
ATMEL |
| 描述： | Rad Hard 16 MegaBit 3.3V 5V Tolerant SRAM Multi-Chip Module |
| 文件： | 总15页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 16 Mbit SRAM Multi Chip Module
• Allows 32-, 16- or 8-bit access configuration
• Operating Voltage: 3.3V + 0.3V, 5V Tolerant
• Access Time:
– 25 ns
– 20 ns
– 18 ns (preliminary information)
• Very Low Power Consumption
– Active: 595 mW per byte (Max) @ 20 ns(1), 415mW per byte (Max) @ 50ns(2)
– Standby: 15 mW (Typ)
• Military Temperature Range: -55 to +125°C
• TTL-Compatible Inputs and Outputs
• Asynchronous
• Die manufactured on Atmel 0.25 µm Radiation Hardened Process
• No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm2@125°C
• Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019
• ESD better than 2000V
Rad Hard
16 MegaBit 3.3V
5V Tolerant
SRAM Multi-
Chip Module
• Quality Grades:
– QML-Q or V
– ESCC
• 950 Mils Wide MQFPT68 Package
• Mass : 8.5 grams
AT68166HT
Notes: 1. For AT68166HT-20 only. 540mW for AT68166HT-25.
2. For AT68166HT-20 only. 450mW for AT68166HT-25.
Description
The AT68166HT is a 16Mbit SRAM packaged in a hermetic Multi Chip Module (MCM)
for space applications.
The AT68166HT MCM incorporates four 4Mbit AT60142HT SRAM dice. It can be
organized as either one bank of 512Kx8, two banks of 512Kx16 or four banks of
512Kx8. It combines rad-hard capabilities, a latch-up threshold of 80MeV.cm²/mg, a
Multiple Bit Upset immunity and a total dose tolerance of 300Krads, with a fast access
time.
The MCM packaging technology allows a reduction of the PCB area by 50% with a
weight savings of 75% compared to four 4Mbit packages.
Thanks to the small size of the 4Mbit SRAM die, Atmel has been able to accommo-
date the assembly of the four dice on one side of the package which facilitates the
power dissipation.
The compatibility with other products allows designers to easily migrate to the Atmel
AT68166HT memory.
The AT68166HT is powered at 3.3V and is 5V tolerant.
The AT68166HT is processed according to the test methods of the latest revision of
the MIL-PRF-38535 or the ESCC 9000.
7843A–AERO–10/09
Block Diagram
AT68166HT Block Diagram
CS1
WE1
CS0
WE0
CS3
WE3
CS2
WE2
A[18:0]
OE
BANK1
BANK0
BANK3
BANK2
512k x 8
512k x 8
512k x 8
512k x 8
I/O[15:8]
or
I/O[7:0]
or
I/O[31:24]
or
I/O[23:16]
or
I/O1[31:16]
or
I/O1[15:0]
or
I/O2[31:16]
or
I/O2[15:0]
or
I/O1[7:0]
I/O[7:0]
I/O3[7:0]
I/O2[7:0]
512K x 8 Banks Block Diagram (AT60142HT)
I/Ox0
I/Ox7
CSx
OE
WEx
2
AT68166HT
7843A–AERO–10/09
AT68166HT
Pin Configuration
AT68166HT is packaged in a MQFPT68. The pin assignment depends on the access time.
There are 2 versions as described in the table below :
Access Time
25 ns
20 ns
18 ns
Package Version
YM
YS
YS
Table 1. Pin assignment for YS & YM versions
Lead
1
Signal
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
Lead
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Signal
VCC
A11
Lead
Signal
I/O3[7]
I/O3[6]
I/O3[5]
I/O3[4]
I/O3[3]
I/O3[2]
I/O3[1]
I/O3[0]
GND
Lead
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Signal
VCC
A10
A9
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
2
3
A12
A13
A14
A15
A16
CS0
OE
4
A8
5
A7
6
A6
7
WE0
CS3
GND
CS2
A5
8
9
10
11
12
13
14
15
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
CS1
A17
WE1
WE2
WE3
A18
GND
NC
I/O2[7]
I/O2[6]
I/O2[5]
I/O2[4]
I/O2[3]
I/O2[2]
A4
A3
A2
A1
YS
16
17
I/O1[6]
I/O1[7]
33
34
50
51
I/O2[1]
I/O2[0]
67
A0
YM
YS
YM
VCC
NC
YS
YM
VCC
NC
68
3
7843A–AERO–10/09
Figure 1. YM package pin assignment
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
1
I/O2[0]
I/O2[1]
I/O2[2]
I/O2[3]
I/O2[4]
I/O2[5]
I/O2[6]
I/O2[7]
GND
I/O3[0]
I/O3[1]
I/O3[2]
I/O3[3]
I/O3[4]
I/O3[5]
I/O3[6]
I/O3[7]
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
2
3
4
5
6
AT68166H
(top view)
7
8
9
10
11
12
13
14
15
16
17
Note:
NC pins are not bonded internally. So, they can be connected to GND or Vcc.
Figure 2. AT68166HT pin assignment in YS package
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
1
I/O2[0]
I/O2[1]
I/O2[2]
I/O2[3]
I/O2[4]
I/O2[5]
I/O2[6]
I/O2[7]
GND
I/O3[0]
I/O3[1]
I/O3[2]
I/O3[3]
I/O3[4]
I/O3[5]
I/O3[6]
I/O3[7]
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
2
3
4
5
6
AT68166H
(top view)
7
8
9
10
11
12
13
14
15
16
17
4
AT68166HT
7843A–AERO–10/09
AT68166HT
Pin Description
Table 2. Pin Names
Name
Description
Address Inputs
Data Input/Output
Chip Select
A0 - A18
I/O0 - I/O31
CS0 - CS3
WE0 - WE3
OE
Write Enable
Output Enable
Power Supply
Ground
VCC
GND(1)
Note:
1. The package lid is connected to GND
Table 3. Truth Table(1)
CSx
H
WEx
OE
X
Inputs/Outputs
Mode
Standby
Read
X
H
L
Z
Data Out
Data In
Z
L
L
L
X
Write
L
H
H
Output Disable
Note:
1. L=low, H=high, X= H or L, Z=high impedance.
5
7843A–AERO–10/09
Electrical Characteristics
Absolute Maximum Ratings*
*NOTE:
Stresses beyond those listed under "Abso-
lute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure between recommended DC
operating and absolute maximum rating
conditions for extended periods may
affect device reliability.
Supply Voltage to GND Potential: ...................... -0.5V to 4.6V
Voltage range on any input: ......................... GND -0.5V to 7V
Voltage range on any ouput: ........................ GND -0.5V to 7V
Storage Temperature: .................................... -65⋅C to +150⋅C
Output Current from Outputs Pins: .............................. 20 mA
Electrostatic Discharge Voltage: ............................... > 2000V
(MIL STD 883D Method 3015)
Military Operating Range
Operating Voltage
Operating Temperature
3.3 + 0.3V
-55⋅C to + 125⋅C
Recommended DC Operating Conditions
Parameter
Vcc
Description
Min
Typ
3.3
0.0
0.0
–
Max
3.6
Unit
V
Supply voltage
Ground
3.0
0.0
GND
VIL
0.0
V
Input low voltage
Input high voltage
GND - 0.3
2.2
0.8
V
VIH
5.5V(1)
V
Note:
1. 5.8V in transient conditions.
Capacitance
Parameter
Cin(1) (OE and Ax)
Description
Min
–
Typ
–
Max
Unit
pF
Input capacitance
Input capacitance
I/O capacitance
48
12
12
Cin(1) (CSx and WEx)
–
–
pF
(1)
Cio
–
–
pF
Note:
1. Guaranteed but not tested.
6
AT68166HT
7843A–AERO–10/09
AT68166HT
DC Parameters
DC Test Conditions
TA = -55°C to + 125°C; Vss = 0V; VCC = 3.0V to 3.6V
Maximum
AT68166HT-25 AT68166HT-20 AT68166HT-18
Description
Minimum Typical
Unit
Parameter
IIX(1)
Input leakage current
-1
-1
–
–
–
–
–
–
–
–
1
1
1
1
1
1
μA
μA
μA
µA
μA
V
IOZ(1)
Output leakage current
Input Leakage Current (OE & Axx)
Input Leakage Current (WE & CS)
10
5
6
6
IIH(2) at 5.5V
–
2
2
IOZH(2) at 5.5V Output Leakage Current
–
5
1.5
0.4
–
1.5
0.4
–
VOL(3)
VOH(4)
Output low voltage
Output high voltage
–
0.4
–
2.4
V
Notes: 1. GND < VIN < VCC, GND < VOUT < VCC Output Disabled.
2. VIN = 5.5V, VOUT = 5.5V, Output Disabled.
3. VCC min, - IOL = 6 mA
4. VCC min, IOH = -4 mA
Consumption
Symbol
Description
AT68166HT-25 AT68166HT-20 AT68166HT-18
(preliminary)
Unit Value
TAVAV/TAVAW
Test Condition
(1)
ICCSB
Standby Supply Current
Standby Supply Current
–
–
10
8
7
6
7.5
7
mA
mA
max
max
(2)
ICCSB1
18 ns
20 ns
25 ns
50 ns
1 µs
–
–
–
170
165
145
80
165
145
80
ICCOP(3) Read
per byte
Dynamic Operating
Current
150
85
15
mA
mA
max
max
12
12
18 ns
20 ns
25 ns
50 ns
1 µs
–
–
145
140
135
115
105
–
140
135
115
105
ICCOP(4) Write
per byte
Dynamic Operating
Current
150
125
110
Notes: 1. All CSx >VIH
2. All CSx > VCC - 0.3V
3. F = 1/TAVAV, Iout = 0 mA, WEx = OE = VIH, VIN = GND/VCC, VCC max.
4. F = 1/TAVAW, Iout = 0 mA, WEx = VIL, OE = VIH , VIN = GND/VCC, VCC max.
7
7843A–AERO–10/09
Data Retention Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and sup-
ply current are guaranteed over temperature. The following rules insure data retention:
1. During data retention chip select CSx must be held high within VCC to VCC -0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, mini-
mizing power dissipation.
3. During power-up and power-down transitions CSx and OE must be kept between VCC
0.3V and 70% of VCC.
+
4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages
(3V).
Figure 3. Data Retention Timing
vcc
CSx
Data Retention Characteristics
Parameter
Description
Min
2.0
0.0
Typ TA = 25⋅C
Max
Unit
V
VCCDR
tCDR
tR
VCC for data retention
Chip deselect to data retention time
Operation recovery time
–
–
–
–
–
–
ns
(1)
tAVAV
ns
6
(AT68166HT-25)
4.5
(2)
ICCDR
Data retention current
–
3
mA
(AT68166HT-20)
5
(AT68166HT-18)
1.
2.
TAVAV = Read cycle time.
All CSx = VCC, VIN = GND/VCC
.
8
AT68166HT
7843A–AERO–10/09
AT68166HT
AC Characteristics
Temperature Range:................................................................................................. -55 +125°C
Supply Voltage: ........................................................................................................... 3.3 +0.3V
Input Pulse Levels:................................................................................................. GND to 3.0V
Input Rise and Fall Times:................................................................................... 3ns (10 - 90%)
Input and Output Timing Reference Levels:........................................................................ 1.5V
Output Loading IOL/IOH:........................................................................................... See Figure 4
Figure 4. AC Test Loads Waveforms
General
Specific (TWLQZ, TWHQX, TELQX, TEHQZ
TGLQX, TGHQZ)
Write Cycle
Table 4. Write cycle timings(1)
AT68166HT-25
AT68166HT-20
AT68166HT-18
(preliminary)
Symbol
TAVAW
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ
TWLWH
Parameter
min
20
2
max
min
20
2
max
min
18
2
max
Unit
ns
Write cycle time
-
-
-
-
-
-
Address set-up time
Address valid to end of write
Data set-up time
ns
14
9
-
11
8
-
10
7
-
ns
-
-
-
ns
CS low to write end
Write low to high Z(2)
Write pulse width
12
-
-
12
-
-
11
-
-
ns
10
-
10
-
9
-
ns
12
9
9
ns
Address hold from end of
write
TWHAX
0
-
0
-
0
-
ns
TWHDX
TWHQX
Data hold time
2
5
-
-
1
5
-
-
1
5
-
-
ns
ns
Write high to low Z(2)
Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Wave-
forms” on page 9.)
9
7843A–AERO–10/09
Write Cycle 1.
WE Controlled, OE High During Write
ADDRESS
CSx
WEx
OE
I/Os
Write Cycle 2.
WE Controlled, OE Low
ADDRESS
CSx
WEx
I/Os
Write Cycle 3.
CS Controlled
ADDRESS
CSx
WEx
I/Os
The internal write time of the memory is defined by the overlap of CS Low and WE LOW. Both signals must
be activated to initiate a write and either signal can terminate a write by going in active mode. The data
input setup and hold timing should be referenced to the active edge of the signal that terminates the write.
Data out is high impedance if OE= VIH.
10
AT68166HT
7843A–AERO–10/09
AT68166HT
Read Cycle
Table 5. Read cycle timings(1)
Symbol
Parameter
AT68166HT-25 AT68166HT-20 AT68166HT-18
(preliminary)
min
max
-
min
max
min
max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TAVAV
Read cycle time
25
-
20
-
-
20
-
18
-
-
18
-
TAVQV
TAVQX
TELQV
TELQX
TEHQZ
TGLQV
TGLQX
TGHQZ
Address access time
Address valid to low Z
Chip-select access time
CS low to low Z(2)
25
-
5
-
5
-
5
-
25
-
20
-
18
-
5
-
5
-
5
-
CS high to high Z(2)
Output Enable access time
OE low to low Z(2)
10
12
-
9
9
-
-
10
-
-
9
2
-
2
-
2
-
-
OE high to high Z (2)
10
9
9
Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Wave-
forms” on page 9.)
Read Cycle 1.
Address Controlled (CS = OE = VIL, WE = VIH)
ADDRESS
DOUT
Read Cycle 2.
Chip Select Controlled (WE = VIH)
CSx
OE
DOUT
11
7843A–AERO–10/09
Typical Applications
This section shows standard implementations of the AT68166HT in applications.
32-bit mode
application
When used on a 32-bit (word) application, the module shall be connected as follow :
•
•
•
The 32 lines of data are connected to distinct data lines
The four CSx are connected together and linked to a single host CS output
Each one of the four WEx is connected to a dedicated WE line on the host to allow byte, half
word and word format write.
Figure 5. 32-bit typical application ( 1 SRAM bank)
A
D
AT68166HT
A[19:2]
D[31:0]
CS[3:0]
OE
A[17:0]
RAMS0*
RAMOE0*
RWE[3:0]*
I/O[31:0]
WE[3:0]
TSC695F
A[19:2]
D[31:0]
A[27:0]
D[31:0]
16-bit mode
application
When used on a 16-bit (half word) application, the module can be connected as presented in the
following figure. This allows use of a single AT68166HT part for two SRAM memory banks.
All input controls of the AT68166HT not used in the application shall be pulled-up.
Figure 6. 16-bit typical application (two SRAM banks)
AT68166HT
A
OE
RAMOE[1:0]*
A[18:1]
A[17:0]
D
CS[3:2]
WE[3:2]
RAMS1*
RWE0*
D[31:16]
D[31:16]
I/O[31:16]
I/O[15:0]
CS[1:0]
WE[1:0]
RAMS0*
RWE0*
TSC695F
A[18:1]
D[31:0]
A[27:0]
D[31:0]
8-bit mode
application
When used on a 8-bit (byte) application, the module can be connected as presented in the fol-
lowing figure. This allows use of a single AT68166HT part for up to four SRAM memory banks.
All input controls of the AT68166HT not used in the application shall be pulled-up.
Figure 7. 8-bit typical application (two SRAM banks)
OE
RAMOE[1:0]*
A
AT68166HT
CS[3]
WE[3]
RAMS2*
RWE0*
A[17:0]
A[17:0]
D
CS[2]
WE[2]
RAMS2*
RWE0*
D[31:24]
D[31:24]
D[31:24]
D[31:24]
I/O[31:24]
I/O[23:16]
I/O[15:8]
I/O[7:0]
CS[1]
WE[1]
RAMS1*
RWE0*
TSC695F
CS[0]
WE[0]
RAMS0*
RWE0*
A[17:0]
D[31:0]
A[27:0]
D[31:0]
12
AT68166HT
7843A–AERO–10/09
AT68166HT
Ordering Information
Part Number
Temperature Range
25⋅C
Speed
25 ns
25 ns
25 ns
25 ns
25 ns
Package
MQFPT68
MQFPT68
MQFPT68
MQFPT68
MQFPT68
Flow
Engineering Samples
Mil Level B
AT68166HT-YM25-E
AT68166HT-YM25MQ(2)
AT68166HT-YM25SV(2)
AT68166HT-YM25SR(2)
AT68166HT-YM25-SCC(3)
-55⋅ to +125⋅C
-55⋅ to +125⋅C
-55⋅ to +125⋅C
-55⋅ to +125⋅C
Space Level B
Space Level B RHA
ESCC
AT68166HT-YS20-E
25°C
20 ns
20 ns
20 ns
20 ns
20 ns
MQFPT68
MQFPT68
MQFPT68
MQFPT68
MQFPT68
Engineering Samples
Mil Level B
AT68166HT-YS20MQ(2)
AT68166HT-YS20SV(2)
AT68166HT-YS20SR(2)
AT68166HT-YS20-SCC(3)
-55° to +125°C
-55° to +125°C
-55° to +125°C
-55° to +125°C
Space Level B
Space Level B RHA
ESCC
AT68166HT-YS18-E(1)
25°C
18 ns
18 ns
18 ns
18 ns
18 ns
MQFPT68
MQFPT68
MQFPT68
MQFPT68
MQFPT68
Engineering Samples
Mil Level B
AT68166HT-YS18-MQ(1)(2)
AT68166HT-YS18-SV(1)(2)
AT68166HT-YS18-SR(1)(2)
AT68166HT-YS18-SCC(1)(3)
-55° to +125°C
-55° to +125°C
-55° to +125°C
-55° to +125°C
Space Level B
Space Level B RHA
ESCC
Note:
1. Please contact your local sales office.
2. Will be replaced by SMD part number when available.
3. Will be replaced by ESCC part number when available.
13
7843A–AERO–10/09
Package Drawing
68-lead Quad Flat Pack (950 Mils) with non conductive tie bar
Note:
1. Lid is connected to Ground.
2. YM and YS package drawings are identical.
Document Revision History
Creation from AT66168FT without any change.
14
AT68166HT
7843A–AERO–10/09
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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