AT68166G [ATMEL]
Rad Hard 16 MegaBit 3.3V SRAM MultiChip Module; 抗辐射16兆3.3V SRAM多芯片模块
| 型号： | AT68166G |
| 厂家： | 
ATMEL |
| 描述： | Rad Hard 16 MegaBit 3.3V SRAM MultiChip Module |
| 文件： | 总17页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
•
•
•
16 Mbit SRAM Multi Chip Module
Allows 32-, 16- or 8-bit access configuration
Operating Voltage: 3.3V + 0.3V
Access Time
– 20 ns, 18 ns for AT68166F
– <18 ns for AT68166G (in development prototypes in Q4 2007)
Power Consumption
– Active: 620 mW per byte (Max) @ 18ns - 415 mW per byte (Max) @ 50ns (1)
– Standby: 13 mW (Typ)
•
•
•
•
•
•
•
•
•
Military Temperature Range: -55 to +125°C
TTL-Compatible Inputs and Outputs
Asynchronous
Rad Hard
16 MegaBit
3.3V
Die manufactured on Atmel 0.25 µm Radiation Hardened Process
No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm2
Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019
ESD Better than 4000V
SRAM Multi-
Chip Module
Quality Grades:
– QML-Q or V with SMD 5962-06229
– ESCC
950 Mils Wide MQFP 68 Package
•
•
Mass : 8.5 grams
AT68166F
AT68166G
Note:
1. Only for AT68166F-18. 450mW for AT68166F-20.
Description
The AT68166F/G is a 16Mbit SRAM packaged in a hermetic Multi Chip Module
(MCM) for space applications.
The AT68166F/G MCM incorporates four 4Mbit AT60142FT SRAM dice. It can be
organized as either one bank of 512Kx8, two banks of 512Kx16 or four banks of
512Kx8. It combines rad-hard capabilities, a latch-up threshold of 80MeV.cm²/mg, a
Multiple Bit Upset immunity and a total dose tolerance of 300Krads, with a fast access
time.
The MCM packaging technology allows a reduction of the PCB area by 50% with a
weight savings of 75% compared to four 4Mbit packages.
Thanks to the small size of the 4Mbit SRAM die, Atmel has been able to accommo-
date the assembly of the four dice on one side of the package which facilitates the
power dissipation.
The compatibility with other products allows designers to easily migrate to the Atmel
AT68166F/G memory.
The AT68166F/G is powered at 3.3V.
The AT68166F/G is processed according to the test methods of the latest revision of
the MIL-PRF-38535 or the ESCC 9000.
7747A–AERO–07/07
Block Diagram
Figure 1. AT68166F/G Block Diagram
CS1
WE1
CS0
WE0
CS3
CS2
WE2
WE3
A[18:0]
OE
BANK1
BANK0
BANK3
BANK2
512k x 8
512k x 8
512k x 8
512k x 8
I/O[15:8]
or
I/O[7:0]
or
I/O[31:24]
or
I/O[23:16]
or
I/O1[31:16]
or
I/O1[7:0]
I/O1[15:0]
or
I/O[7:0]
I/O2[31:16]
or
I/O3[7:0]
I/O2[15:0]
or
I/O2[7:0]
Figure 2. 512K x 8 Banks Block Diagram (AT60142F/G)
A0
-
-
-
A10
I/Ox0
I/Ox7
CSx
WEx
OE
Packages
AT68166F and AT68166G are packed in MQFP68.
Access Time
18 ns
YS
20 ns
<18 ns
AT68166F
AT68166G
YM
YS
The pin assignment depends on the access time. There are 2 versions:
–
–
YM package where 3 pins are not connected.
YS package where the 3 above pins are connected to GND or VCC
.
2
AT68166F/G
7747A–AERO–07/07
AT68166F/G
Pin
Configuration
Table 1. AT68166F/G pin assignment in YS package
Lead
1
Signal
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
Lead
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal
VCC
A11
Lead
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Signal
I/O3[7]
I/O3[6]
I/O3[5]
I/O3[4]
I/O3[3]
I/O3[2]
I/O3[1]
I/O3[0]
GND
Lead
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal
VCC
A10
A9
2
3
A12
4
A13
A8
5
A14
A7
6
A15
A6
7
A16
WE0
CS3
GND
CS2
A5
8
CS0
OE
9
10
11
12
13
14
15
16
17
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
CS1
A17
I/O2[7]
I/O2[6]
I/O2[5]
I/O2[4]
I/O2[3]
I/O2[2]
I/O2[1]
I/O2[0]
WE1
WE2
WE3
A18
A4
A3
A2
A1
GND
VCC
A0
VCC
Notes: 1. In YM package leads 33, 34 and 68 are not connected.
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7747A–AERO–07/07
Figure 3. AT68166F pin assignment in YM package
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
1
2
3
4
5
6
7
8
I/O2[0]
I/O2[1]
I/O2[2]
I/O2[3]
I/O2[4]
I/O2[5]
I/O2[6]
I/O2[7]
GND
I/O3[0]
I/O3[1]
I/O3[2]
I/O3[3]
I/O3[4]
I/O3[5]
I/O3[6]
I/O3[7]
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
AT68166F
(top view)
9
10
11
12
13
14
15
16
17
Figure 4. AT68166F/G pin assignment in YS package
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
1
2
3
4
5
6
7
8
I/O2[0]
51
I/O2[1]
I/O2[2]
I/O2[3]
I/O2[4]
I/O2[5]
I/O2[6]
I/O2[7]
GND
I/O3[0]
I/O3[1]
I/O3[2]
I/O3[3]
I/O3[4]
I/O3[5]
I/O3[6]
I/O3[7]
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
AT68166F/G
(top view)
9
10
11
12
13
14
15
16
17
4
AT68166F/G
7747A–AERO–07/07
AT68166F/G
Pin Description
Table 2. Pin Names
Name
Description
Address Inputs
Data Input/Output
Chip Select
A0 - A18
I/O0 - I/O31
CS0 - CS3
WE0 - WE3
OE
Write Enable
Output Enable
Power Supply
Ground
VCC
GND(1)
Note:
1. The package lid is connected to GND
Table 3. Truth Table(1)
CSx
H
WEx
OE
X
Inputs/Outputs
Mode
Standby
Read
X
H
L
Z
Data Out
Data In
Z
L
L
L
X
Write
L
H
H
Output Disable
Note:
1. L=low, H=high, X= H or L, L=high impedance.
5
7747A–AERO–07/07
Electrical Characteristics
Absolute Maximum Ratings*
*NOTE:
Stresses beyond those listed under "Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Supply Voltage to GND Potential:.........................-0.5V + 4.6V
DC Input Voltage:........................................GND -0.5V to 4.6V
DC Output Voltage High Z State:................GND -0.5V to 4.6V
Storage Temperature:................................... -65°C to + 150°C
Output Current Into Outputs (Low): ............................... 20 mA
Electro Statics Discharge Voltage:..............> 4000V (MIL STD
883D Method 3015.3)
Military Operating Range
Operating Voltage
Operating Temperature
3.3 + 0.3V
-55°C to + 125°C
Recommended DC Operating Conditions
Parameter
Vcc
Description
Min
Typ
Max
3.6
Unit
V
Supply voltage
Ground
3
0.0
3.3
0.0
0.0
–
GND
VIL
0.0
V
Input low voltage
Input high voltage
GND - 0.3
2.2
0.8
V
VIH
VCC + 0.3
V
Capacitance
Parameter
Description
Min
Typ
Max
Unit
Cin(1) (OE and Ax)
Input capacitance
–
–
48
pF
Cin(1) (CSx and
WEx)
Input capacitance
I/O capacitance
–
–
–
–
12
12
pF
pF
(1)
Cio
Note:
1. Guaranteed but not tested.
6
AT68166F/G
7747A–AERO–07/07
AT68166F/G
DC Parameters
Parameter
Description
Minimum
Typical
Maximum
Unit
IIX(1)
Input leakage current
-1
–
1
µA
Output leakage
current
IOZ(1)
-1
–
1
µA
VOL(2)
VOH(3)
Output low voltage
Output high voltage
–
–
–
0.4
–
V
V
2.4
Notes: 1. GND < VIN < VCC, GND < VOUT < VCC Output Disabled.
2. VCC min. IOL = 8 mA
3.
VCC min. IOH = -4 mA
Consumption
AT68166F-20
AT68166F-18
TAVAV/TAVAW Test
Condition
Symbol
Description
Unit
Value
Standby
Supply Current
(1)
ICCSB
–
–
10
8
7
6
mA
max
Standby
Supply Current
(2)
ICCSB1
mA
mA
max
max
18 ns
20 ns
50 ns
1 µs
–
170
165
80
Dynamic
Operating
Current
ICCOP(3) Read
per byte
170
85
15
12
18 ns
20 ns
50 ns
1 µs
–
145
140
115
105
Dynamic
Operating
Current
ICCOP(4) Write
per byte
150
125
110
mA
max
Notes: 1. All CSx >VIH
2. All CSx > VCC - 0.3V
3. F = 1/TAVAV, Iout = 0 mA, WEx = OE = VIH, VIN = GND/VCC, VCC max.
4. F = 1/TAVAW, Iout = 0 mA, WEx = VIL, OE = VIH , VIN = GND/VCC, VCC max.
7
7747A–AERO–07/07
Data Retention
Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and sup-
ply current are guaranteed over temperature. The following rules insure data retention:
1. During data retention chip select CSx must be held high within VCC to VCC -0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, mini-
mizing power dissipation.
3. During power-up and power-down transitions CSx and OE must be kept between VCC
0.3V and 70% of VCC
+
.
4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages
(3V).
Figure 5. Data Retention Timing
vcc
CSx
Data Retention Characteristics
Parameter
Description
Min
Typ TA = 25°C
Max
Unit
VCCDR
VCC for data retention
2.0
–
–
V
Chip deselect to data
retention time
tCDR
0.0
–
–
–
–
ns
ns
Operation recovery
time
(1)
tR
tAVAV
6 (AT68166F-20)
(2)
ICCDR
Data retention current
–
3
mA
4.5 (AT68166F-18)
1.
TAVAV = Read cycle time.
All CSx = VCC, VIN = GND/VCC.
2.
8
AT68166F/G
7747A–AERO–07/07
AT68166F/G
AC Characteristics
Temperature Range:................................................ -55 +125°C
Supply Voltage: ....................................................... 3.3 +0.3V
Input Pulse Levels:.................................................. GND to 3.0V
Input Rise and Fall Times:....................................... 3ns (10 - 90%)
Input and Output Timing Reference Levels:............ 1.5V
Output Loading IOL/IOH:............................................ See Figure 3
Figure 6. AC Test Loads Waveforms
General
Specific (TWLQZ, TWHQX, TELQX, TEHQZ
TGLQX, TGHQZ)
Write Cycle
Table 4. Write cycle timings(1)
AT68166F-20
AT68166F-18
Symbol
TAVAW
TAVWL
TAVWH
TDVWH
TELWH
TWLQZ
TWLWH
TWHAX
TWHDX
TWHQX
Parameter
min
20
2
max
min
18
2
max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
-
-
-
-
-
-
-
8
-
-
-
-
Address set-up time
Address valid to end of write
Data set-up time
14
9
-
11
8
-
CS low to write end
Write low to high Z(2)
Write pulse width
12
-
-
12
-
10
-
12
0
9
Address hold from end of write
Data hold time
-
0
2
-
1
Write high to low Z(2)
5
-
3
Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 9.)
9
7747A–AERO–07/07
Figure 7. Write Cycle 1. WE Controlled, OE High During Write
ADDRESS
CSx
WEx
OE
I/Os
Figure 8. Write Cycle 2. WE Controlled, OE Low
ADDRESS
CSx
WEx
I/Os
Figure 9. Write Cycle 3. CS Controlled
ADDRESS
CSx
WEx
I/Os
The internal write time of the memory is defined by the overlap of CS Low and WE LOW. Both signals must
be activated to initiate a write and either signal can terminate a write by going in active mode. The data
input setup and hold timing should be referenced to the active edge of the signal that terminates the write.
Data out is high impedance if OE= VIH.
10
AT68166F/G
7747A–AERO–07/07
AT68166F/G
Read Cycle
Table 5. Read cycle timings(1)
AT68166F-18
AT68166F-20
Symbol
TAVAV
Parameter
min
max
min
max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
20
-
-
20
-
18
-
-
18
-
TAVQV
TAVQX
TELQV
TELQX
TEHQZ
TGLQV
TGLQX
TGHQZ
Address access time
Address valid to low Z
Chip-select access time
CS low to low Z(2)
5
-
5
-
20
-
18
-
5
-
5
-
CS high to high Z(2)
Output Enable access time
OE low to low Z(2)
9
8
-
11
-
-
8
2
-
2
-
-
OE high to high Z (2)
9
8
Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 9.)
Figure 10. Read Cycle nb 1: Address Controlled (CS = OE = VIL, WE = VIH)
ADDRESS
DOUT
11
7747A–AERO–07/07
Figure 11. Read Cycle nb 2: Chip Select Controlled (WE = VIH)
CSx
OE
DOUT
12
AT68166F/G
7747A–AERO–07/07
AT68166F/G
Typical
Applications
This section presents some standard implementations of the AT68166F/G in application.
32-bit mode
application
When used on a 32-bit (word) application, the module shall be connected as follow :
•
•
•
The 32 lines of data are connected to distinct data lines
The four CSx are connected together and linked to a single host CS output
Each one of the four WEx is connected to a dedicated WE line on the host to allow byte, half
word and word format write.
Figure 12. 32-bit typical application ( 1 SRAM bank)
A
D
AT68166F/G
A[19:2]
D[31:0]
CS[3:0]
OE
WE[3:0]
A[17:0]
RAMS0*
RAMOE0*
RWE[3:0]*
I/O[31:0]
AT697E
A[19:2]
D[31:0]
A[27:0]
D[31:0]
16-bit mode
application
When used on a 16-bit (half word) application, the module can be connected as presented in the
following figure. This allows use of a single AT68166F/G part for two SRAM memory banks.
All input controls of the AT68166F/G not used in the application shall be pulled-up.
Figure 13. 16-bit typical application (two SRAM banks)
AT68166F/G
A
OE
RAMOE[1:0]*
A[18:1]
A[17:0]
D
CS[3:2]
WE[3:2]
RAMS1*
RWE0*
D[31:16]
D[31:16]
I/O[31:16]
I/O[15:0]
CS[1:0]
WE[1:0]
RAMS0*
RWE0*
AT697E
A[18:1]
D[31:0]
A[27:0]
D[31:0]
8-bit mode
application
When used on a 8-bit (byte) application, the module can be connected as presented in the fol-
lowing figure. This allows use of a single AT68166F/G part for up to four SRAM memory banks.
All input controls of the AT68166F/G not used in the application shall be pulled-up.
13
7747A–AERO–07/07
Figure 14. 8-bit typical application (two SRAM banks)
OE
RAMOE[1:0]*
A
AT68166F/G
CS[3]
WE[3]
RAMS2*
RWE0*
A[17:0]
A[17:0]
D
CS[2]
WE[2]
RAMS2*
RWE0*
D[31:24]
D[31:24]
D[31:24]
D[31:24]
I/O[31:24]
I/O[23:16]
I/O[15:8]
I/O[7:0]
CS[1]
WE[1]
RAMS1*
RWE0*
AT697E
CS[0]
WE[0]
RAMS0*
RWE0*
A[17:0]
D[31:0]
A[27:0]
D[31:0]
14
AT68166F/G
7747A–AERO–07/07
AT68166F/G
Ordering Information
Part Number
AT68166F
Temperature Range
Speed
Package
Flow
AT68166F-YM20-E
5962-0622902QXC
5962-0622902VXC
5962R0622902VXC
AT68166F-YM20-SCC
25°C
20 ns
20 ns
20 ns
20 ns
20 ns
MQFP68
MQFP68
MQFP68
MQFP68
MQFP68
Engineering Samples
QML Q
-55° to +125°C
-55° to +125°C
-55° to +125°C
-55° to +125°C
QML V
QML V RHA
ESCC
AT68166F-YS18-E
25°C
18 ns
18 ns
18 ns
18 ns
18 ns
MQFP68
MQFP68
MQFP68
MQFP68
MQFP68
Engineering Samples
QML Q
AT68166F-YS18-MQ(1)
AT68166F-YS18-SV(1)
AT68166F-YS18-SR(1)
AT68166F-YS18-SCC(1)
-55° to +125°C
-55° to +125°C
-55° to +125°C
-55° to +125°C
QML V
QML V RHA
ESCC
Note:
1. Will be replaced by SMD part number when available.
15
7747A–AERO–07/07
Package
Drawings
68-lead Quad Flat Pack (950 Mils) with non conductive tie bar
Note:
Note:
Lid is connected to Ground.
YM and YS package drawings are identical.
16
AT68166F/G
7747A–AERO–07/07
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
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Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Regional Headquarters
Microcontrollers
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Tel: 1(408) 441-0311
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Europe
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Japan
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Japan
Fax: 1(719) 540-1759
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Maxwell Building
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