AT5FC512-20 [ATMEL]
512K byte Flash Memory PCMCIA Card; 512K字节的闪存PCMCIA卡
| 型号： | AT5FC512-20 |
| 厂家： | 
ATMEL |
| 描述： | 512K byte Flash Memory PCMCIA Card |
| 文件： | 总15页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
Single Power Supply
•
Read and Write Voltage, 5V ± 5%
High Performance
•
•
•
200 ns Maximum Access Time
6 ms Typical Sector Write
CMOS Low Power Consumption
20 mA Typical Active Current (Byte Mode)
400 µA Typical Standby Current
Fully MS-DOS Compatible Flash Driver and Formatter
Virtual-Disk Flash Driver with 256 Bytes/Sector
Random Read/Write to any Sector
No Erase Operation Required Prior to any Write
Zero Data Retention Power
Batteries not Required for Data Storage
PCMCIA/JEIDA 68-Pin Standard
Selectable Byte- or Word-Wide Configuration
High Re-programmable Endurance
Built-in Redundancy for Sector Replacement
Minimum 100,000 Write Cycles
512K byte
Flash Memory
PCMCIA Card
•
•
•
AT5FC512
Five Levels of Write Protection
•
Prevent Accidental Data Loss
Block Diagram
Pin Configuration
Pin Name
A0-A18
Function
Addresses
Data
D0-D15
CE1, CE2,
Control Signals
Card Status
,
,
WE OE REG
CD, WP
BVD1, BVD2
Description
Atmel’s Flash Memory Card provides the highest system
level performance for data and file storage solutions to the
portable PC market segment. Data files and applications
programs can be stored on the AT5FC512. This allows
OEM manufacturers of portable system to eliminate the
weight, power consumption and reliability issues associ-
ated with electro-mechanical disk-based systems. The
AT5FC512 requires a single voltage power supply for total
system operation. No batteries are needed for data reten-
tion due to its Flash-based technology. Since no high volt-
age (12-volt) is required to perform any write operation,
the AT5FC512 is suitable for the emerging "mobile" per-
sonal systems.
The Card Information Structure (CIS) can be written by the
OEM or by Atmel at the attribute memory address space
using a format utility. The CIS appears at the beginning of
the card’s attribute memory space and defines the low-
level organization of data on the PC card. The AT5FC512
contains a separate 2K byte EEPROM memory for the
card’s attribute memory space.
The third party software solutions such as AWARD Soft-
ware’s CardWare system and the SCM’s Flash File Sys-
tem (FFS), enables Atmel’s Flash Memory Card to emu-
late the function of essentially all the major brand personal
computers that are DOS/Windows compatible.
For some unique portable computers, such as the
HP200/100/95LX series, the software Driver and Format-
ter are also available. The Atmel Driver and Formatter util-
izes a self-contained spare sector replacement algorithm,
enabled by Atmel’s small 256-byte sectors, to achieve
long term card reliability and endurance.
The AT5FC512 is compatible with the 68-pin
PCMCIA/JEIDA international standard. Atmel’s Flash
Memory Cards can be read in either a byte-wide or word-
wide mode which allows for flexible integration into various
system platforms. It can be read like any typical PCMCIA
SRAM or ROM card.
Block Diagram
2
AT5FC512
AT5FC512
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the card.
This is a stress rating only and functional operation of the
card at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied.Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Storage Temperature........................ -30°C to +70°C
Ambient Temperature with
Power Applied................................... -10°C to +70°C
Voltage with
(1)
Respect to Ground, All pins ........... -2.0V to +7.0V
(1)
Notes:
V
................................................ -2.0V to +7.0V
CC
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transients, inputs may overshoot VSS to -2.0V for
periods of up to 20 ns. Maximum DC voltage on output and
I/O pins is VCC + 0.5V. During voltage transitions, outputs
may overshoot to VCC + 2.0V for periods up to 20 ns.
2. No more than one output shorted at a time. Duration of the
short circuit should not be greater than one second. Condi-
tions equal VOUT = 0.5V or 5.0V, VCC = Max.
(2)
Output Short Circuit Current ....................-200 mA
DC and AC Operating Range
AT5FC512-20
o
o
Operating Temperature (Case)
Power Supply
Com.
0 C - 70 C
V
5V ± 5%
CC
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Symbol
Parameter
Conditions
Typ
Max
Units
pF
C
C
C
C
Address Capacitance
Output Capacitance
Control Capacitance
I/O Capacitance
V
V
V
V
= 0V
20
20
45
20
IN1
OUT
IN2
I/O
IN
= 0V
= 0V
pF
OUT
pF
IN
= 0V
pF
I/O
Note: 1. This parameter is characterized and is not 100% tested.
3
PC Card Pin Assignments
I = Input, O = Output, I/O = Bi-directional, NC = No Connect
Pin
1
Signal I/O
Function
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal I/O
Function
GND
Ground
GND
Ground
(1)
2
D3
D4
D5
D6
D7
CE
I/O
Data Bit 3
CD
O
I/O
I/O
I/O
I/O
I/O
I
Card Detect 1
Data Bit 11
Data Bit 12
Data Bit 13
Data Bit 14
Data Bit 15
Card Enable 2
No Connect
Reserved
1
3
I/O
Data Bit 4
D11
D12
D13
D14
D15
4
I/O
Data Bit 5
5
I/O
Data Bit 6
6
I/O
Data Bit 7
(1)
7
I
I
I
I
I
I
I
I
I
Card Enable 1
Address Bit 10
Output Enable
Address Bit 11
Address Bit 9
Address Bit 8
Address Bit 13
Address Bit 14
Write Enable
No Connect
Power Supply
No Connect
Address Bit 16
Address Bit 15
Address Bit 12
Address Bit 7
Address Bit 6
Address Bit 5
Address Bit 4
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
Data Bit 0
1
(1)
8
A10
OE
A11
A9
CE
2
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
RFU
RFU
A17
A18
NC
Reserved
A8
I
I
Address Bit 17
Address Bit 18
No Connect
A13
A14
WE
NC
NC
No Connect
NC
No Connect
V
V
CC
Power Supply
No Connect
CC
NC
A16
A15
A12
A7
NC
NC
NC
NC
NC
NC
NC
NC
NC
REG
I
No Connect
I
No Connect
I
No Connect
I
No Connect
A6
I
No Connect
A5
I
No Connect
A4
I
I
No Connect
A3
No Connect
A2
I
I
Register Select
Battery Voltage Detect 2
Battery Voltage Detect 1
Data Bit 8
(2)
(2)
A1
I
BVD
BVD
D8
O
2
A0
I
O
1
D0
I/O
I/O
I/O
O
I/O
I/O
I/O
O
D1
Data Bit 1
D9
Data Bit 9
D2
Data Bit 2
D10
Data Bit 10
(1)
(1)
WP
GND
Write Protect
Ground
CD
Card Detect 2
2
GND
Ground
2. BVD = Internally pulled up.
Notes: 1. Signal must not be connected between cards.
4
AT5FC512
AT5FC512
Pin Description
Symbol
Name
Type
Function
A0-A18
Address Inputs
Input
Address Inputs are internally latched during write cycles.
Data Input/Outputs are internally latched on write cycles.
Input/Output Data outputs are latched during read cycles. Data pins
are active high. When the memory card is de-selected or
the outputs are disabled the outputs float to tri-state.
D0-D15
Data Input/Output
Card Enable
Card Enable is active low. The memory card is
de-selected and power consumption is reduced to
standby levels when CE is high. CE activates the internal
memory card circuitry that controls the high and low byte
CE , CE
Input
1
2
control logic of the card, input buffers, segment decoders,
and associated memory devices.
Output Enable is active low and enables the data buffers
through the card outputs during read cycles.
OE
Output Enable
Write Enable
Input
Write Enable is active low and controls the write function
to the memory array. The target address is latched on the
falling edge of the WE pulse and the appropriate data is
WE
Input
latched on the rising edge of the pulse.
PC Card Power
Supply
PC Card Power Supply for device operation
(5.0V ± 5%)
V
CC
GND
Ground
Ground
When Card Detect 1 and 2 = Ground the system detects
the card.
CD , CD
Card Detect
Output
1
2
Write Protect is active high and indicates that all card
Output
WP
NC
Write Protect
write operations are disabled by the write protect switch.
No Connect
Corresponding pin is not connected internally.
BVD , BVD
Battery Voltage Detect
Output
Input
Internally pulled up. (There is no battery in the card.)
1
2
Provide access to Card Information Structure in the
Attribute Memory Device
REG
Register Select
Byte-Wide Operations
Memory Card Operations
The AT5FC512 provides the flexibility to operate on data
in byte-wide or word-wide operations. Byte-wide data is
The AT5FC512 Flash Memory Card is organized as an
array of 4 individual AT29C010A devices. They are logi-
cally defined as contiguous sectors of 256 bytes. Each
sector can be read and written randomly as designated by
the host. There is NO need to erase any sector prior to any
write operation. Also, there is NO high voltage (12V) re-
quired to perform any write operations.
available on D0-D7 for read and write operations (CE =
1
low, CE = high). Even and odd bytes are stored in a pair
2
of memory chip segments (i.e., S0 and S1) and are ac-
cessed when A0 is low and high respectively.
Word-Wide Operations
The common memory space data contents are altered in
a similar manner as writing to individual Flash memory de-
vices. On-card address and data buffers activate the ap-
propriate Flash device in the memory array. Each device
internally latches address and data during write cycles.
Refer to the Common Memory Operations table.
The 16 bit words are accessed when both CE and CE
1
2
are forced low, A0 = don’t care. D0-D15 are used for word-
wide operations.
(continued)
5
Memory Card Operations (Continued)
Read Enable/Output Disable
A mechanical write protection switch provides a second
type of write protection. When this switch is activated, WE
is internally forced high. The Flash memory arrays are
therefore write-disabled.
Data outputs from the card are disabled when OE is at a
logic-high level. Under this condition, outputs are in the
high-impedance state. The A18 selects the paired mem-
ory chip segments, while A0 decides the upper or lower
The third type of write protection is achieved with the built-
bank. The CE /CE pins determine either byte or word
1
2
in low V sensing circuit within each Flash device. If the
CC
mode operation. The Output Enable (OE) is forced low to
activate all outputs of the memory chip segments. The on-
card I/O transceiver is set in the output mode. The
AT5FC512 sends data to the host. Refer to AC Read
Waveforms drawing.
external V
inhibited.
is below 3.8V (typical), the write function is
CC
The fourth type of write protection is a noise filter circuit
within each Flash device. Any pulse of less than 15 ns
(typical) on the WE, CE or CE inputs will not initiate a
1
2
program cycle.
Standby Operations
The last type of write protection is based on the Software
Data Protection (SDP) scheme of the AT29C010A de-
vices. Each of the sixteen devices needs to enable and
disable the SDP individually. Refer to the Software Data
Protected Programming/Disable Algorithm tables for
descriptions of enable and disable SDP operations.
When both CE an d CE are at logic-high level, the
1
2
AT5FC512 is in Standby mode; i.e., all memory chip seg-
ments as well as the decoder/transceiver are completely
de-selected at minimum power consumption. Even in the
byte-mode read operation, only one memory chip seg-
ment (even or odd) is active at any time. The other seven
memory chip segments remain in standby. In the word-
mode there are two memory chip segments in active and
six in standby.
Card Detection
Each CD (output) pin should be read by the host system
to determine if the memory card is properly seated in the
socket. CD and CD are internally tied to the ground. If
both bits are not detected, the system should indicate that
the card must be re-inserted.
1
2
Write Operations
The AT5FC512 is written on a sector basis. Each sector of
256 bytes can be selected randomly and written inde-
pendently without any prior erase cycle. A8 to A17 specify
the sector address, while A18 specifies the Flash chip
segment pair. Within each sector, the individual byte ad-
dress is latched on the falling edge of CE or WE, which-
ever occurs last. The data is latched by the first rising edge
of CE or WE. Each byte pair to be programmed must have
its high-to-low transition on WE (or CE) within 150 µs of
the low-to- high transition of WE (or CE) of the preceding
byte pair. If a high-to-low transition is not detected within
150 µs of the last low-to-high transition, the data load pe-
riod will end and the internal programming period will start.
All the bytes of a sector are simultaneously programmed
during the internal programming period. A maximum write
time of 10 ms per sector is self-controlled by the Flash
devices. Refer to AC Write Waveforms drawings.
CIS Data
The Card Information Structure (CIS) describes the capa-
bilities and specifications of a card. The CIS of the
AT5FC512 can be written either by the OEM or by Atmel
at the attribute memory space beginning at address
00000H by using a format utility. The AT5FC512 contains
a separate 2K byte EEPROM memory for the card’s attrib-
ute memory space. The attribute is active when the REG
pin is driven low. D0-D7 are active during attribute mem-
ory access. D8-D15 should be ignored. Odd order bytes
present invalid data. Refer to the Attribute Memory
Operations table.
Write Protection
The AT5FC512 has five types of write protection. The
PCMCIA/JEIDA socket itself provides the first type of write
protection. Power supply and control pins have specific
pin lengths in order to protect the card with proper power
supply sequencing in the case of hot insertion and re-
moval.
6
AT5FC512
AT5FC512
Common Memory Operations
X = Don’t Care, where Don’t Care is either V or V levels.
IL
IH
Pins
REG
CE
CE
OE
WE
A0
D8-D15
D0-D7
2
1
Read-Only
(1)
Read (x8)
Read (x8)
Read (x8)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
High Z
Data Out-Even
IH
IH
IH
IH
IH
IH
IH
IL
IL
IL
IL
IL
IH
IH
IH
IH
IH
IH
IL
(2)
(3)
V
High Z
Data Out-Odd
High Z
IL
IH
V
V
V
X
Data Out-Odd
Data Out-Odd
High Z
IL
IL
IH
(4)
Read (x16)
V
IL
X
X
X
Data Out-Even
High Z
Output Disable
Standby
X
X
V
X
V
V
X
X
High Z
High Z
IH
IH
Write-Only
(1)
Write (x8)
V
IH
V
IH
V
IH
V
IH
V
IH
V
V
V
V
V
V
V
V
V
V
IL
V
IL
V
IL
V
IL
V
IL
V
High Z
Data In-Even
Data In-Odd
High Z
IH
IH
IL
IL
IH
IH
IH
IH
IH
IH
IL
(2)
Write (x8)
V
High Z
IH
(3)
Write (x8)
V
V
V
X
Data In-Odd
Data In-Odd
High Z
IL
IL
(4)
Write (x16)
V
IL
X
X
Data In-Even
High Z
Output Disable
X
X
Notes:
1. Byte access - Even. In this x8 mode, D0-D7 contain the
"even" byte (low byte) of the x16 word. D8-D15 are inactive.
2. Byte access - Odd. In this x8 mode, D0-D7 contain the "odd"
byte (high byte) of the x16 word. This is accomplished inter-
nal to the card by transposing D8-D15 to D0-D7. D8-D15
are inactive.
3. Odd byte only access. In this x8 mode, D8-D15 contain the
"odd" byte (high byte) of the x16 word. D0-D7 are inactive.
A0 = X.
4. Word access. In this mode D0-D7 contain the "even" byte
while D8-D15 contain the "odd" byte. A0 = X
Memory Card Program Routine
Memory Card Program Routine
Byte Mode
Word Mode
7
Attribute Memory Operations
X = Don’t Care, where Don’t Care is either V or V levels.
IL
IH
Pins
REG
CE
CE
OE
WE
A0
D8-D15
D0-D7
2
1
Read-Only
(1)
Read (x8)
Read (x8)
Read (x8)
Read (x16)
Output Disable
Standby
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
High Z
Data Out-Even
Not Valid
High Z
IL
IL
IL
IL
IL
IH
IH
IL
IL
IL
IL
IL
IH
IH
IH
IH
IH
IH
IL
V
High Z
IL
IH
V
V
V
X
Not Valid
Not Valid
High Z
IL
IL
IH
V
IL
X
X
X
Data Out-Even
High Z
X
X
V
X
V
V
X
X
High Z
High Z
IH
IH
Write-Only
(1)
Write (x8)
V
IL
V
IL
V
IL
V
IL
V
IL
V
V
V
V
V
V
V
V
V
V
IL
V
IL
V
IL
V
IL
V
IL
V
High Z
Data In-Even
Not Valid
High Z
IH
IH
IL
IL
IH
IH
IH
IH
IH
IH
IL
Write (x8)
V
High Z
IH
Write (x8)
V
V
V
X
Not Valid
Not Valid
High Z
IL
IL
Write (x16)
Output Disable
V
IL
X
X
Data In-Even
High Z
X
X
Note: 1. Byte access - Even. In this x8 mode, D0-D7 contain the "even" byte (low byte) of the x16 word. D8-D15 are inactive.
8
AT5FC512
AT5FC512
DC Characteristics, Byte-Wide Operation
Symbol Parameter
Condition
Min
Typ
Max
Units
V
V
= V Max,
CC
CC
I
I
I
Input Leakage Current
Output Leakage Current
1.0
±20
µA
LI
= V or V
IN
CC
SS
V
V
= V Max,
CC
CC
1.0
0.4
20
µA
LO
SB
= V or V
OUT
CC
SS
V
= V Max,
CC
CC
V
V
V
Standby Current
0.8
mA
CC
CC
CC
CE = V ± 0.2V
CC
V
= V Max, CE = V ,
CC IL
CC
(1)
I
I
Active Read Current
Active Write Current
OE = V , I
at 5 MHz
= 0 mA,
20
20
40
mA
mA
CC1
IH OUT
CE = V ,WE = V ,
Programming in Progress
IL
IL
40
CC2
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
0.8
V
V
V
V
IL
2.4
3.8
IH
I
= 3.2 mA
= -2.0 mA
0.40
OL
OH
OL
I
OH
Note: 1. One Flash device active, 15 in standby.
DC Characteristics, Word-Wide Operation
Symbol Parameter
Condition
Min
Typ
Max
Units
V
V
= V Max,
CC
CC
IN
I
I
I
Input Leakage Current
Output Leakage Current
1.0
±20
µA
LI
= V or V
CC
SS
V
V
= V Max,
CC
CC
1.0
0.4
20
µA
LO
SB
= V or V
OUT
CC
SS
V
= V Max,
CC
CC
V
V
V
Standby Current
0.8
mA
CC
CC
CC
CE = V ± 0.2V
CC
V
= V Max, CE = V ,
CC IL
CC
(1)
I
I
Active Read Current
Active Write Current
OE = V , I
at 5 MHz
= 0 mA,
40
40
80
mA
mA
CC1
CC2
IH OUT
CE = V , WE = V ,
Programming in Progress
IL
IL
80
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
0.8
V
V
V
V
IL
2.4
3.8
IH
I
= 3.2 mA
= -2.0 mA
0.40
OL
OH
OL
I
OH
Note: 1. Two Flash devices active, 2 in standby.
9
AC Read Characteristics
Symbol Parameter
Min
Max
Units
ns
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
200
RC
CE
ACC
OE
Lz
Chip Enable Access Time
200
200
100
ns
Address Access Time
ns
Output Enable Access Time
ns
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
Output Hold Time from First of Address, CE, or OE Change
Write Recovery Time Before Read
5
5
5
ns
60
ns
DF
ns
OLZ
DF
60
ns
ns
OH
WC
10
ms
Input test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
AC Read Waveforms(1)
Note:
1. CE refers to CE1, and/or CE2
10
AT5FC512
AT5FC512
Write Cycle Characteristics
Symbol
Parameter
Min
Max
Units
t
t
t
t
t
t
t
t
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
ms
ns
ns
ns
ns
ns
µs
ns
WC
10
60
AS
AH
60
DS
10
DH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
WP
BLC
WPH
150
100
AC Write Waveforms (Byte Mode)
Notes:
1. A18 specify the pair of AT29C010A devices to be written,
while A0 controls the selection of even and odd bytes. A0,
A18 must be valid throughout the entire WE low pulse.
3. OE must be high when WE and CE are both low.
4. All bytes that are not loaded within the sector being pro-
grammed will be indeterminate.
2. A8 through A17 must specify the sector address during each
high to low transition of WE (or CE).
11
AC Write Waveforms (Word Mode)
Notes:
1. A18 specifies the pair of AT29C010A devices to be written;
they must be valid throughout the entire WE low pulse. A0
is don’t care.
3. OE must be high when WE and CE are both low.
4. All bytes that are not loaded within the sector being pro-
grammed will be indeterminate.
2. A8 through A18 must specify the sector address during each
high to low transition of WE (or CE).
12
AT5FC512
AT5FC512
Software Data Protected Programming Algorithm (1)
Device
0
1
2
3
Data
Address
AA
0AAAA
AA
0AAAB
AA
4AAAA
AA
4AAAB
Data
Address
55
05554
55
05555
55
45554
55
45555
Data
Address
A0
0AAAA
A0
0AAAB
A0
4AAAA
A0
4AAAB
Writes
Enabled
Write
Bytes
Write
Bytes
Write
Bytes
Write
Bytes
Note: 1. Load 3 bytes to corresponding Flash chip segment individually to enable software data protection.
13
Software Data Protected Disable Algorithm (1)
Device
0
1
2
3
Data
Address
AA
0AAAA
AA
0AAAB
AA
4AAAA
AA
4AAAB
Data
Address
55
05554
55
05555
55
45554
55
45555
Data
Address
80
0AAAA
80
0AAAB
80
4AAAA
80
4AAAB
Data
Address
AA
0AAAA
AA
0AAAB
AA
4AAAA
AA
4AAAB
Data
Address
55
05554
55
05555
55
45554
55
45555
Data
Address
20
0AAAA
20
0AAAB
20
4AAAA
20
4AAAB
Writes
Enabled
Write
Bytes
Write
Bytes
Write
Bytes
Write
Bytes
Note: 1. Load 6 bytes to corresponding Flash chip segment individually to disable software data protection.
14
AT5FC512
AT5FC512
Ordering Information
t
ACC
Ordering Code
AT5FC512-20
Package
Operation Range
(ns)
200
PCMCIA Type 1
Commercial
(0°C to 70°C)
Packaging Information
PCMCIA, Type 1 PC Memory Card
Dimensions in millimeters
85.6 0.2 mm
10.0 MIN. (mm)
54.0 0.1 mm
10.0 MIN. (mm)
3.3 0.1 mm
FRONT SIDE
34
68
1
35
BACK SIDE
15
相关型号：
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