AT5FC002 [ATMEL]
2-Megabyte Flash Memory PCMCIA Card; 2兆字节的闪存PCMCIA卡
| 型号： | AT5FC002 |
| 厂家： | 
ATMEL |
| 描述： | 2-Megabyte Flash Memory PCMCIA Card |
| 文件： | 总15页 (文件大小：718K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
Single Power Supply
•
Read and Write Voltage, 5 V ± 5%
High Performance
•
•
•
200 ns Maximum Access Time
6 ms Typical Sector Write
CMOS Low Power Consumption
20 mA Typical Active Current (Byte Mode)
400 µA Typical Standby Current
Fully MS-DOS Compatible Flash Driver and Formatter
Virtual-Disk Flash Driver with 512 Bytes/Sector
Random Read/Write to any Sector
No Erase Operation Required Prior to any Write
Zero Data Retention Power
Batteries not Required for Data Storage
PCMCIA/JEIDA 68-Pin Standard
Selectable Byte- or Word-Wide Configuration
High Re-programmable Endurance
Built-in Redundancy for Sector Replacement
Minimum 100,000 Write Cycles
2-Megabyte
Flash Memory
PCMCIA Card
•
•
•
AT5FC002
Five Levels of Write Protection
•
Prevent Accidental Data Loss
Block Diagram
Pin Configuration
Pin Name
Function
Addresses
Data
A0-A20
D0-D15
CE1, CE2,
Control Signals
Card Status
,
,
WE OE REG
CD, WP
BVD1, BVD2
Description
Atmel’s Flash Memory Card provides the highest system level
performance for data and file storage solutions to the portable
PC market segment. Data files and applications programs can be
stored on the AT5FC002. This allows OEM manufacturers of
portable system to eliminate the weight, power consumption and
reliability issues associated with electro-mechanical disk-based
systems. The AT5FC002 requires a single voltage power supply
for total system operation. No batteries are needed for data re-
tention due to its Flash-based technology. Since no high voltage
(12-volt) is required to perform any write operation, the
AT5FC002 is suitable for the emerging "mobile" personal sys-
tems.
The Card Information Structure (CIS) can be written by the
OEM or by Atmel at the attribute memory address space using a
format utility. The CIS appears at the beginning of the card’s
attribute memory space and defines the low-level organization
of data on the PC card. The AT5FC002 contains a separate
2 Kbyte EEPROM memory for the card’s attribute memory
space.
The third party software solutions such as AWARD Software’s
CardWare system and the SCM’s Flash File System (FFS),
enables Atmel’s Flash Memory Card to emulate the function of
essentially all the major brand personal computers that are
DOS/Windows compatible.
The AT5FC002 is compatible with the 68-pin PCMCIA/JEIDA
international standard. Atmel’s Flash Memory Cards can be
read in either a byte-wide or word-wide mode which allows for
flexible integration into various system platforms. It can be read
like any typical PCMCIA SRAM or ROM card.
For some unique portable computers, such as the
HP200/100/95LX series, the software Driver and Formatter are
also available. The Atmel Driver and Formatter utilizes a self-
contained spare sector replacement algorithm, enabled by At-
mel’s small 512-byte sectors, to achieve long term card
reliability and endurance.
Block Diagram
2
AT5FC002
AT5FC002
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum
Ratings" may cause permanent damage to the card. This is a stress
rating only and functional operation of the card at these or any
other conditions beyond those indicated in the
Storage Temperature........................ -30°C to +70°C
Ambient Temperature with
Power Applied................................... -10°C to +70°C
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended pe-
riods may affect device reliability.
Voltage with
(1)
Respect to Ground, All pins .......... -2.0 V to +7.0 V
(1)
Notes:
V
CC
............................................... -2.0 V to +7.0 V
1. Minimum DC voltage on input or I/O pins is -0.5 V. During volt-
(2)
age transients, inputs may overshoot V to -2.0 V for periods of
SS
up to 20 ns. Maximum DC voltage on output and I/O pins is
Output Short Circuit Current ....................-200 mA
V
V
+0.5 V. During voltage transitions, outputs may overshoot to
+2.0 V for periods up to 20 ns.
CC
CC
2. No more than one output shorted at a time. Duration of the short cir-
cuit should not be greater than one second. Conditions equal
V
OUT
= 0.5 V or 5.0 V, V = Max.
CC
D.C. and A.C. Operating Range
AT5FC002-20
o
o
Operating Temperature (Case)
Power Supply
Com.
0 C - 70 C
V
5 V ± 5%
CC
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Symbol
Parameter
Conditions
Typ
Max
Units
pF
C
IN1
C
OUT
C
IN2
C
I/O
Address Capacitance
Output Capacitance
Control Capacitance
I/O Capacitance
V
V
V
V
= 0 V
20
20
45
20
IN
= 0 V
pF
OUT
= 0 (CE)
= 0 V
pF
IN
pF
I/O
Note: 1. This parameter is characterized and is not 100% tested.
3
PC Card Pin Assignments
I = Input, O = Output, I/O = Bi-directional, NC = No Connect
Pin
1
Signal I/O
Function
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal I/O
Function
Ground
GND
Ground
GND
(1)
2
D3
D4
D5
D6
D7
CE
I/O Data Bit 3
I/O Data Bit 4
I/O Data Bit 5
I/O Data Bit 6
I/O Data Bit 7
CD
O
Card Detect 1
1
3
D11
D12
D13
D14
D15
I/O Data Bit 11
I/O Data Bit 12
I/O Data Bit 13
I/O Data Bit 14
I/O Data Bit 15
4
5
6
(1)
7
I
I
I
I
I
I
I
I
I
Card Enable 1
1
(1)
8
A10
OE
A11
A9
Address Bit 10
Output Enable
Address Bit 11
Address Bit 9
Address Bit 8
Address Bit 13
Address Bit 14
Write Enable
No Connect
CE
I
Card Enable 2
No Connect
Reserved
2
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
RFU
RFU
A17
A18
A19
A20
NC
Reserved
A8
I
I
I
I
Address Bit 17
Address Bit 18
Address Bit 19
Address Bit 20
No Connect
A13
A14
WE
NC
V
CC
Power Supply
No Connect
V
CC
Power Supply
No Connect
NC
A16
A15
A12
A7
NC
NC
NC
NC
NC
NC
NC
NC
NC
REG
I
I
I
I
I
I
I
I
I
I
I
Address Bit 16
Address Bit 15
Address Bit 12
Address Bit 7
Address Bit 6
Address Bit 5
Address Bit 4
Address Bit 3
Address Bit 2
Address Bit 1
Address Bit 0
No Connect
No Connect
No Connect
No Connect
A6
No Connect
A5
No Connect
A4
No Connect
A3
No Connect
A2
I
Register Select
Battery Voltage Detect 2
Battery Voltage Detect 1
(2)
(2)
A1
BVD
BVD
D8
O
O
2
A0
1
D0
I/O Data Bit 0
I/O Data Bit 1
I/O Data Bit 2
I/O Data Bit 8
I/O Data Bit 9
I/O Data Bit 10
D1
D9
D2
D10
(1)
(1)
WP
GND
O
Write Protect
Ground
CD
O
Card Detect 2
Ground
2
GND
Notes: 1. Signal must not be connected between cards.
2. BVD = Internally pulled up.
4
AT5FC002
AT5FC002
Pin Description
Symbol
Name
Type
Function
A0-A20
Address Inputs
Input
Address Inputs are internally latched during write cycles.
Data Input/Outputs are internally latched on write cycles. Data
outputs are latched during read cycles. Data pins are active high.
When the memory card is de-selected or the outputs are disabled
the outputs float to tri-state.
Input/Output
Input
D0-D15
Data Input/Output
Card Enable
Card Enable is active low. The memory card is de-selected and
power consumption is reduced to standby levels whenCE is high.
CE activates the internal memory card circuitry that controls the
high and low byte control logic of the card, input buffers, segment
decoders, and associated memory devices.
CE , CE
1
2
Output Enable is active low and enables the data buffers through
the card outputs during read cycles.
OE
Output Enable
Write Enable
Input
Input
Write Enable is active low and controls the write function to the
memory array. The target address is latched on the falling edge of
the WE pulse and the appropriate data is latched on the rising
edge of the pulse.
WE
PC Card Power Supply for device operation
(5.0 V ± 5%)
PC Card Power
Supply
V
CC
GND
Ground
Ground
CD , CD
Card Detect
Output
Output
When Card Detect 1 and 2 = Ground the system detects the card.
1
2
Write Protect is active high and indicates that all card write
operations are disabled by the write protect switch.
WP
NC
Write Protect
No Connect
Corresponding pin is not connected internally.
BVD , BVD
Battery Voltage Detect
Output
Input
Internally pulled up. (There is no battery in the card.)
1
2
Provide access to Card Information Structure in the Attribute
Memory Device
REG
Register Select
5
Memory Card Operations
The AT5FC002 Flash Memory Card is organized as an array of
4 individual AT29C040A devices. They are logically defined as
contiguous sectors of 512 bytes. Each sector can be read and
written randomly as designated by the host. There is NO need to
erase any sector prior to any write operation. Also, there is NO
high voltage (12 V) required to perform any write operations.
first rising edge of CE or WE. Each byte pair to be programmed
must have its high-to-low transition on WE (or CE) within 150
µs of the low-to- high transition of WE (or CE) of the preceding
byte pair. If a high-to-low transition is not detected within 150
µs of the last low-to-high transition, the data load period will
end and the internal programming period will start. All the bytes
of a sector are simultaneously programmed during the internal
programming period. A maximum write time of 10 ms per sec-
tor is self-controlled by the Flash devices. Refer to A.C. Write
Waveforms drawings.
The common memory space data contents are altered in a simi-
lar manner as writing to individual Flash memory devices. On-
card address and data buffers activate the appropriate Flash de-
vice in the memory array. Each device internally latches address
and data during write cycles. Refer to the Common Memory
Operations table.
Write Protection
The AT5FC002 has five types of write protection. The
PCMCIA/JEIDA socket itself provides the first type of write
protection. Power supply and control pins have specific pin
lengths in order to protect the card with proper power supply
sequencing in the case of hot insertion and removal.
Byte-Wide Operations
The AT5FC002 provides the flexibility to operate on data in
byte-wide or word-wide operations. Byte-wide data is available
on D0-D7 for read and write operations (CE = low, CE =
1
2
high). Even and odd bytes are stored in a pair of memory chip
segments (i.e., S0 and S1) and are accessed when A0 is low and
high respectively.
A mechanical write protection switch provides a second type of
write protection. When this switch is activated, WE is internally
forced high. The Flash memory arrays are therefore write-dis-
abled.
Word-Wide Operations
The third type of write protection is achieved with the built-in
low VCC sensing circuit within each Flash device. If the exter-
nal VCC is below 3.8 V (typical), the write function is inhibited.
The 16-bit words are accessed when both CE and CE are
1
2
forced low, A0 = don’t care. D0-D15 are used for word-wide
operations
The fourth type of write protection is a noise filter circuit within
each Flash device. Any pulse of less than 15 ns (typical) on the
Read Enable/Output Disable
WE, CE or CE inputs will not initiate a program cycle.
1
2
Data outputs from the card are disabled when OE is at a logic-
high level. Under this condition, outputs are in the high-imped-
ance state. The A20 selects the paired memory chip segments,
The last type of write protection is based on the Software Data
Protection (SDP) scheme of the AT29C040A devices. Each of
the sixteen devices needs to enable and disable the SDP indi-
vidually. Refer to the Software Data Protected Program-
ming/Disable Algorithm tables for descriptions of enable and
disable SDP operations.
while A0 decides the upper or lower bank. The CE /CE pins
1
2
determine either byte or word mode operation. The Output En-
able (OE) is forced low to activate all outputs of the memory
chip segments. The on-card I/O transceiver is set in the output
mode. The AT5FC002 sends data to the host. Refer to A.C.
Read Waveforms drawing.
Card Detection
Each CD (output) pin should be read by the host system to de-
termine if the memory card is properly seated in the socket.CD
1
Standby Operations
and CD are internally tied to the ground. If both bits are not
2
When both CE and CE are at logic-high level, the AT5FC002
1
2
detected, the system should indicate that the card must be
re-inserted.
is in Standby mode; i.e., all memory chip segments as well as the
decoder/transceiver are completely de-selected at minimum
power consumption. Even in the byte-mode read operation, only
one memory chip segment (even or odd) is active at any time.
The other seven memory chip segments remain in standby. In
the word-mode there are two memory chip segments in active
and six in standby.
CIS Data
The Card Information Structure (CIS) describes the capabilities
and specifications of a card. The CIS of the AT5FC002 can be
written either by the OEM or by Atmel at the attribute memory
space beginning at address 00000H by using a format utility.
The AT5FC002 contains a separate 2 Kbyte EEPROM memory
for the card’s attribute memory space. The attribute is active
when the REG pin is driven low. D0-D7 are active during at-
tribute memory access. D8-D15 should be ignored. Odd order
bytes present invalid data. Refer to the Attribute Memory
Operations table.
Write Operations
The AT5FC002 is written on a sector basis. Each sector of 512
bytes can be selected randomly and written independently with-
out any prior erase cycle. A9 to A19 specify the sector address,
while A20 specifies the Flash chip segment pair. Within each
sector, the individual byte address is latched on the falling edge
of CE or WE, whichever occurs last. The data is latched by the
6
AT5FC002
AT5FC002
Common Memory Operations
X = Don’t Care, where Don’t Care is either V or V levels.
IL
IH
Pins
REG
CE
CE
OE
WE
A0
D8-D15
D0-D7
2
1
Read-Only
(1)
Read (x8)
Read (x8)
Read (x8)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
High Z
Data Out-Even
IH
IH
IH
IH
IH
IH
IL
IL
IL
IL
IL
IH
IH
IH
IH
IH
IH
IL
(2)
(3)
V
IH
High Z
Data Out-Odd
High Z
IH
IL
V
V
V
IH
X
Data Out-Odd
Data Out-Odd
High Z
IL
(4)
Read (x16)
V
IL
X
X
X
Data Out-Even
High Z
IL
Output Disable
Standby
X
X
V
X
V
IH
V
IH
X
X
High Z
High Z
Write-Only
(1)
Write (x8)
V
IH
V
IH
V
IH
V
IH
V
IH
V
V
V
V
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
V
IL
V
High Z
Data In-Even
Data In-Odd
High Z
IH
IL
IL
IH
IL
(2)
Write (x8)
V
IH
High Z
IH
(3)
Write (x8)
V
V
V
X
Data In-Odd
Data In-Odd
High Z
IL
(4)
Write (x16)
V
IL
X
X
Data In-Even
High Z
IL
Output Disable
X
X
Notes:
1. Byte access - Even. In this x8 mode, D0-D7 contain the "even"
byte (low byte) of the x16 word. D8-D15 are inactive.
2. Byte access - Odd. In this x8 mode, D0-D7 contain the "odd" byte
(high byte) of the x16 word. This is accomplished internal to the
card by transposing D8-D15 to D0-D7. D8-D15 are inactive.
3. Odd byte only access. In this x8 mode, D8-D15 contain the "odd"
byte (high byte) of the x16 word. D0-D7 are inactive. A0 = X.
4. Word access. In this mode D0-D7 contain the "even" byte while
D8-D15 contain the "odd" byte. A0 = X
Memory Card Program Routine
Memory Card Program Routine
Byte Mode
Word Mode
BEGIN
BEGIN
SELECT
SECTOR
SELECT
SECTOR
INTERLEAVING LOW
LOAD ADDRESS/DATA
LOW AND HIGH BYTES
SIMULTANEOUSLY
LOAD ADDRESS/DATA
OF 256 WORDS
256 BYTES AND
OF 512 BYTES
HIGH 256 BYTES
WAIT FOR A
WAIT FOR A
MAXIMUM OF 10 ms
MAXIMUM OF 10 ms
SECTOR
SECTOR
PROGRAM COMPLETE
PROGRAM COMPLETE
7
Attribute Memory Operations
X = Don’t Care, where Don’t Care is either V or V levels.
IL
IH
Pins
REG
CE
CE
OE
WE
A0
D8-D15
D0-D7
2
1
Read-Only
(1)
Read (x8)
Read (x8)
Read (x8)
Read (x16)
Output Disable
Standby
V
V
V
V
V
VIH
VIH
VIL
VIL
X
V
V
V
V
V
V
V
V
V
V
V
V
High Z
Data Out-Even
Not Valid
High Z
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IH
IH
IH
IH
IH
IL
V
IH
High Z
IL
V
IH
X
Not Valid
Not Valid
High Z
V
IL
X
X
X
Data Out-Even
High Z
X
VIH
X
X
V
IH
V
IH
X
High Z
High Z
Write-Only
(1)
Write (x8)
V
IL
V
IL
V
IL
V
IL
V
IL
V
V
V
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
V
IL
V
High Z
Data In-Even
Not Valid
High Z
IH
IL
IL
IH
IL
Write (x8)
VIH
VIL
VIL
X
V
IH
High Z
Write (x8)
V
X
Not Valid
Not Valid
High Z
Write (x16)
Output Disable
V
IL
X
X
Data In-Even
High Z
X
Note: 1. Byte access - Even. In this x8 mode, D0-D7 contain the "even" byte (low byte) of the x16 word. D8-D15 are inactive.
8
AT5FC002
AT5FC002
D.C. Characteristics, Byte-Wide Operation
Symbol Parameter
Condition
Min
Typ
Max
Units
V
V
= V Max,
CC
CC
IN
I
I
I
Input LeakageCurrent
1.0
±20
µA
LI
= V or V
SS
CC
V
V
= V Max,
CC
CC
OUT
Output Leakage Current
1.0
0.4
20
µA
LO
SB
= V or V
CC
SS
V
CC
= V Max,
CC
V
CC
V
CC
V
CC
Standby Current
0.8
mA
CE = V ± 0.2 V
CC
V
CC
= V Max, CE = V ,
CC IL
(1)
I
I
Active Read Current OE = V , I
= 0 mA,
20
20
40
mA
mA
CC1
CC2
IH OUT
at 5 MHz
CE = V ,WE = V ,
Programming in Progress
IL
IL
Active Write Current
40
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
0.8
V
V
V
V
IL
2.4
3.8
IH
I
= 3.2 mA
= -2.0 mA
0.40
OL
OH
OL
I
OH
Notes: 1. One Flash device active, 3 in standby.
D.C. Characteristics, Word-Wide Operation
Symbol Parameter
Condition
Min
Typ
Max
Units
V
V
= V Max,
CC
CC
IN
I
I
I
Input LeakageCurrent
1.0
±20
µA
LI
= V or V
CC
SS
V
V
= V Max,
CC
CC
OUT
Output Leakage Current
1.0
0.4
20
µA
LO
SB
= V or V
CC
SS
V
CC
= V Max,
CC
V
CC
V
CC
V
CC
Standby Current
0.8
mA
CE = V ± 0.2 V
CC
V
CC
= V Max, CE = V ,
CC IL
(1)
I
I
Active Read Current OE = V , I
= 0 mA,
40
40
80
mA
mA
CC1
CC2
IH OUT
at 5 MHz
CE = V , WE = V ,
Programming in Progress
IL
IL
Active Write Current
80
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
0.8
V
V
V
V
IL
2.4
3.8
IH
I
= 3.2 mA
= -2.0 mA
0.40
OL
OH
OL
I
OH
Notes: 1. Two Flash devices active, 2 in standby.
9
A.C. Read Characteristics
Symbol Parameter
Min
Max
Units
ns
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
200
RC
CE
ACC
OE
Lz
Chip Enable Access Time
200
200
100
ns
Address Access Time
ns
Output Enable Access Time
ns
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
Output Hold Time from First of Address, CE, or OE Change
Write Recovery Time Before Read
5
5
5
ns
60
60
10
ns
DF
ns
OLZ
DF
ns
ns
OH
WC
ms
Input test Waveforms and
Measurement Level
Output Test Load
5.0V
3.0V
1.8K
AC
AC
OUTPUT
PIN
DRIVING
1.5V
LEVELS
0.0V
MEASUREMENT
LEVEL
100pF
1.3K
t , t < 5 ns
R
F
A.C. Read Waveforms(1)
DEVICE AND
ADDRESS
SELECTION
DATA
OUTPUT
ENABLED VALID
POWER-UP,
STANDBY
STANDBY,
POWER-DOWN
ADDRESS
ADDRESSES STABLE
tRC
CE
OE
tDF
tDF
tWC
WE
tOE
tCE
tOH
OUTPUT VALID
tOLZ
tLZ
HIGH Z
DATA
VCC
tACC
5.0 V
0 V
Note:
1. CE refers to CE1, and/or CE2
10
AT5FC002
AT5FC002
Write Cycle Characteristics
Symbol
Parameter
Min
Max
Units
t
t
t
t
t
t
t
t
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
ms
ns
ns
ns
ns
ns
µs
ns
WC
10
60
AS
AH
60
DS
10
DH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
WP
BLC
WPH
150
100
A.C. Write Waveforms (Byte Mode)
OE
CE2
CE1
WE
tWP
tWPH
tBLC
tWC
tAS
tAH
A0
tDH
BYTE
A1-A8
ADDRESS
SECTOR
A9-A19
ADDRESS
tDS
DATA
BYTE 0
BYTE 1
BYTE 2
BYTE 510
BYTE 511
Notes:
1. A20 specifies the pair of AT29C040A devices to be written, while
A0 controls the selection of even and odd bytes. A0 and A20
must be valid throughout the entire WE low pulse.
3. OE must be high when WE and CE are both low.
4. All bytes that are not loaded within the sector being pro-
grammed will be indeterminate.
2. A9 through A19 must specify the sector address during each high
to low transition of WE (or CE).
11
A.C. Write Waveforms (Word Mode)
OE
CE1,2
WE
tWP
tWPH
tBLC
tAS
tWC
tAH
tDH
BYTE
A1-A8
ADDRESS
SECTOR
A9-A19
ADDRESS
tDS
DATA
WORD 0
WORD 1
WORD 2
WORD 254
WORD 255
1. A20 specifies the pair of AT29C040A devices to be written; they
must be valid throughout the entire WE low pulse. A0 is don’t
care.
3. OE must be high when WE and CE are both low.
4. All bytes that are not loaded within the sector being pro-
grammed will be indeterminate.
2. A9 through A19 must specify the sector address during each high
to low transition of WE (or CE).
12
AT5FC002
AT5FC002
Software Data Protected Programming Algorithm (1)
Device
0
1
2
3
Data
Address
AA
00AAAA
AA
00AAAB
AA
10AAAA
AA
10AAAB
Data
Address
55
005554
55
005555
55
105554
55
105555
Data
Address
A0
00AAAA
A0
00AAAB
A0
10AAAA
A0
10AAAB
Writes
Enabled
Write
Bytes
Write
Bytes
Write
Bytes
Write
Bytes
Note: 1. Load 3 bytes to corresponding Flash chip segment individually to enable software data protection.
13
Software Data Protected Disable Algorithm (1)
Device
0
1
2
3
Data
Address
AA
00AAAA
AA
00AAAB
AA
10AAAA
AA
10AAAB
Data
Address
55
005554
55
005555
55
105554
55
105555
Data
Address
80
00AAAA
80
00AAAB
80
10AAAA
80
10AAAB
Data
Address
AA
00AAAA
AA
00AAAB
AA
10AAAA
AA
10AAAB
Data
Address
55
005554
55
005555
55
105554
55
105555
Data
Address
20
00AAAA
20
00AAAB
20
10AAAA
20
10AAAB
Writes
Enabled
Write
Bytes
Write
Bytes
Write
Bytes
Write
Bytes
Note: 1. Load 6 bytes to corresponding Flash chip segment individually to disable software data protection.
14
AT5FC002
AT5FC002
Ordering Information
t
ACC
Ordering Code
AT5FC002-20
Package
Operation Range
(ns)
200
PCMCIA Type 1
Commercial
(0°C to 70°C)
Packaging Information
PCMCIA, Type 1 PC Memory Card
Dimensions in millimeters
85.6 0.2 mm
10.0 MIN. (mm)
54.0 0.1 mm
10.0 MIN. (mm)
3.3 0.1 mm
FRONT SIDE
34
68
1
35
BACK SIDE
CardWare may be trademarks of others.
15
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