AT49LD3200B-10 [ATMEL]
32-megabit (1M x 32 or 2M x 16) High-speed Synchronous Flash Memory; 32兆位（ 1M ×32或2M ×16 ）高速同步闪存
| 型号： | AT49LD3200B-10 |
| 厂家： | 
ATMEL |
| 描述： | 32-megabit (1M x 32 or 2M x 16) High-speed Synchronous Flash Memory |
| 文件： | 总39页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 3.0V to 3.6V Read/Write
• Burst Read Performance
– <100 MHz (RAS Latency = 2, CAS Latency = 6), 10 ns Cycle Time
tSAC = 7 ns
– <75 MHz (RAS Latency = 2, CAS Latency = 5), 13 ns Cycle Time
tSAC = 8 ns
– <50 MHz (RAS Latency = 1, CAS Latency = 4), 20 ns Cycle Time
t
SAC = 9 ns
• MRS Cycle with Address Key Programs
– RAS Latency (1 and 2)
– CAS Latency (2 ~ 8)
– Burst Length: 4, 8
– Burst Type: Sequential and Interleaved
• Word Selectable Organization
32-megabit
(1M x 32 or
2M x 16)
– 16 (Word Mode)/x 32 (Double Word Mode)
• Sector Erase Architecture
High-speed
Synchronous
Flash Memory
– Eight 256K Word or 128K Double Word (4-Mbit) Sectors
• Independent Asynchronous Boot Block
– 8K x 16 Bits with Hardware Lockout
• Fast Program Time
– 3-volt, 100 µs per Word/Double Word Typical
– 12-volt, 30 µs per Word/Double Word Typical
• Fast Sector Erase Time
– 2.5 Seconds at 3 Volts
– 1.6 Seconds at 12 Volts
• Low-power Operation
– ICC Read = 75 mA Typical
• Input and Output Pin Continuity Test Mode Optimizes Off-board Programming
• Package:
– 86-pin TSOP Type II with Off-center Parting Line (OCPL) for Improved Reliability
• LVTTL-compatible Inputs and Outputs
AT49LD3200
AT49LD3200B
SFlash™
Description
The AT49LD3200 or AT49LD3200B SFlash™ is a synchronous, high-bandwidth Flash
memory fabricated with Atmel’s high-performance CMOS process technology and is
organized either as 2,097,152 x 16 bits (word mode) or as 1,048,576 x 32 bits (double
word mode), depending on the polarity of the WORD pin (see Pin Function Descrip-
tion Table). Synchronous design allows precise cycle control. I/O transactions are
possible on every clock cycle. All operations are synchronized to the rising edge of the
system clock. The range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high-band-
width, high-performance memory system applications.
The AT49LD3200B will automatically activate the Asynchronous Boot Block after
power-up, whereas with the AT49LD3200, the Asynchronous Boot Block can be acti-
vated through Mode Register Set.
The synchronous DRAM interface allows designers to maximize system performance
while eliminating the need to shadow slow asynchronous Flash memory into high-
speed RAM.
The 32-megabit SFlash device is designed to sit on the synchronous memory bus and
operate alongside SDRAM.
Rev. 1940B–FLASH–11/01
To maximize system manufacturing throughput the AT49LD3200(B) features high-
speed 12-volt program and erase options. Additionally, stand-alone programming cycle
time of individual devices or modules is optimized with Atmel’s unique input and output
pin continuity test mode.
Pin Configuration
TSOP (Type II)
Top View
VCC
DQ0
VCCQ
DQ16
DQ1
VSSQ
DQ17
DQ2
VCCQ
DQ18
DQ3
VSSQ
DQ19
MR
1
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ31
VSSQ
DQ15
DQ30
VCCQ
DQ14
DQ29
VSSQ
DQ13
DQ28
VCCQ
DQ12
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VCC
DQM
NC
VSS
NC
VPP
WE
CAS
RAS
CS
CLK
CKE
A9
WORD
A12
A8
A11
A7
A10
A6
A0
A5
A1
A4
A2
A3
NC
NC
VCC
NC
VSS
NC
DQ4
VSSQ
DQ20
DQ5
VCCQ
DQ21
DQ6
VSSQ
DQ22
DQ7
VCCQ
DQ23
VCC
DQ27
VCCQ
DQ11
DQ26
VSSQ
DQ10
DQ25
VCCQ
DQ9
DQ24
VSSQ
DQ8
VSS
2
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Pin Function Description
Pin
CLK
CS
Name
Input Function
System Clock
Chip Select
Active on the rising edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK and CKE.
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle. CKE should be
enabled at least one cycle prior to new command. Disables input buffers for power-
down in standby mode.
A0 - A12
RAS
Address
Row/column addresses are multiplexed on the same pins.
Row address: RA0 ~ RA12, Column address: CA0 ~ CA6 (x32), CA0 ~ CA7 (x16)
Row Address Strobe
Column Address Strobe
Latches row addresses on the rising edge of the CLK with RAS low.
Enables row access.
CAS
Latches column addresses on the rising edge of the CLK with CAS low.
Enables column access.
MR
Mode Register Set
Data Input/Output
Power Supply/Ground
Enables mode register set with MR low. (Simultaneously CS, RAS and CAS are low).
Data input for program/erase. Data output for read.
DQ0 - DQ31
VCC/VSS
Power and ground for the input buffers and the core logic.
VCCQ/VSSQ Data Output Power/Ground Power and ground for the output buffers.
WORD
x32/x16 Mode Selection
Double word mode/word mode, depending on polarity of WORD pin (WORD = high,
double word mode; WORD = low, word mode).
Should be set to the desired state during power-up and prior to any device operation.
DQM
NC
Data-out Masking
No Connection
Masks output operation when a complete burst is not required.
Not connected
WE
Write Enable
Enables the chip to be written.
VPP
Program/Erase Pin Supply
Program/Erase power supply.
3
1940B–FLASH–11/01
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature under Bias ................................ -55LC to +125LC
Storage Temperature..................................... -65LC to +150LC
All Input Voltages
(including NC Pins)
with Respect to Ground.....................................-0.6V to +4.6V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on VPP
with Respect to Ground...................................-0.6V to +13.5V
Power Dissipation .............................................................. 1 W
Functional Block Diagram
DQ0
DQ16
DQ15
DQ31
IO Buffer
Program/
Erase
WE
VPP
Logic
ADD
8K x 16 Boot Block
CLK
1M x 32
Cell Array
ADD
LRAS
Column Decoder
Latency & Burst Length
Programming Register
LCKE
LRAS
LMR
LCAS
Timing Register
CLK
CKE
MR
RAS
CAS
CS
DQM
4
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
DC and AC Operating Range
AT49LD3200(B)-10
0LC - 70LC
AT49LD3200(B)-13
AT49LD3200(B)-20
0LC - 70LC
Commercial
0LC - 70LC
-40LC - 85LC
3.0V to 3.6V
Operating Temperature
(Case)
Industrial
-40LC - 85LC
3.0V to 3.6V
-40LC - 85LC
3.0V to 3.6V
VCC, VCCQ Power Supply
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
mA
ISB1
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Standby Current
VCC Active Current
CKE = 0, tCC = Min
20
20
ISB2
CKE ?ꢁVIL (Max), tCC = Min
CS O VIH (Min), tCC = Min
tCC = Min, All Outputs Open
mA
ISB3
50
mA
ICC
150
mA
0V ? VIN ? VDD + 0.3V
Pins not under test = 0V
IIL
Input Leakage Current
-10
-10
10
10
µA
µA
Output Leakage Current (IOOUT
Disabled)
(0V ? VOUT ? VDD Max)
All Outputs in High-Z
IOL
VIH
VIL
Input High Voltage, All Inputs
Note(1)
2.0
-0.3
2.4
VDD + 0.3
0.8
V
V
V
V
Input Low Voltage, All Inputs
Note(2)
VOH
VOL
Output High Voltage Level (Logic 1)
Output Low Voltage Level (Logic 0)
IOH = -2 mA
IOL = 2 mA
0.4
Notes: 1. VIH (max) = 4.6V for pulse width ꢀ10 ns acceptable, pulse width measured at 50% of pulse amplitude.
2. VIL (min) = -1.5V for pulse width ꢀ10 ns acceptable, pulse width measured at 50% of pulse amplitude.
AC Operating Test Conditions
TA = 0 to 70LC, VCC = 3.3V ± 0.3V, unless otherwise noted.
Parameter(1)
Value
1.4V
Timing Reference Levels of Input/Output Signals
Input Signal Levels
VIH/VIL = 2.4V/0.4V
tr/tf = 1 ns/1 ns
LVTTL
Transition Time (Rise & Fall) of Input Signals
Output Load
Note:
1. If CLK transition time is longer than 1 ns, timing parameters should be compensated. Add [(tr + tf)/2-1] ns for transition time
longer than 1 ns. Transition time is measured between VIL (max) and VIH (min).
5
1940B–FLASH–11/01
Figure 1. DC Output Load Circuit
3.3V
1200Ω
VOH (DC) = 2.4V, IOH= -2 mA
Output
V
OL (DC) = 0.4V, IOL= 2 mA
50 pF
870Ω
Figure 2. AC Output Load Circuit
Vtt = 1.4V
50Ω
Output
Z0 = 50Ω
50pF
Pin Capacitance(1)
f = 1 MHz, T = 25°C
Symbol
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
CIN
(2)
COUT
8
12
pF
VOUT = 0V
Notes: 1. This parameter is characterized and is not 100% tested.
2. VPP behaves as an output pin.
6
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
AC Read Characteristics
AC operating conditions unless otherwise noted.
<100 MHz
<75 MHz
<50 MHz
Symbol
tCC
Parameter
Min
Max
Min
Max
Min
Max
Units
ns
CLK Cycle Time
10
13
20
tSAC
tOH
CLK to Valid Output Delay
Data Output Hold Time
CLK High Pulse Width
CLK Low Pulse Width
Row-active to Row-active(1)
Input Setup Time
7
8
9
ns
3
3
4
4
4
6.5
6.5
9
ns
tCH
ns
tCL
3
4
ns
tRC
11
2
10
4
clks
ns
tSS
4
tSH
Input Hold Time
1
2
2
ns
tSLZ
tSHZ
tT
CLK to Output in Low-Z
CLK to Output in High-Z
Transition Time
0
0
0
ns
7
10
10
15
10
ns
0.1
9
10
0.1
8
0.1
7
ns
tVCVC
Valid CAS Enable to Valid CAS Enable(2)
clks
Notes: 1. These tRC values are for BL = 8. For BL = 4, tRC = 7 CLKs for up to 100 MHz, tRC = 6 CLKs for up to 75 MHz, tRC = 5 CLKs for
up to 50 MHz. RAS latency increase means a simultaneous tRC increase in the same number of cycles. (If RAS latency is
3 CLKs, tRC is 12 CLKs for BL = 8.) Refer to page 27 for gapless operation.
2. These tVCVC values are for BL = 8. For BL = 4, tVCVC = 5 CLKs for up to 100 MHz, tVCVC = 4 CLKs for up to 75 MHz,
t
VCVC = 3 CLKs for up to 50 MHz. Refer to page 27 for gapless operation.
7
1940B–FLASH–11/01
Function Truth Table
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Abbreviations (RA: Row Address, CA: Column Address, NOP: No Operation Command, DWM: Double Word Mode, WM:
Word Mode)
Command
CKEn-1 CKEn CS RAS CAS MR(9) DQM
Add.
WORD VPP WE
Register(1)
Mode Register Set
H
H
X
X
L
L
L
L
L
L
X
X
Code
X
X
X
X
X
X
Row Access
& Latch
Row Active
Read
H
H
RA
Column Access
& Latch
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
H
L
L
X
X
X
CA
X
X
X
X
X
X
X
H
X
X
Burst Stop
(Precharge on
Synch. DRAM)
X
Power-down
and Clock
Two
Standby
Mode
Entry
Exit
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Suspend(2)
H
DQM(3)
H
H
H
X
X
X
X
H
L
X
X
H
X
X
H
X
X
H
V
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
No Operation Command(4)
Organization Control(5)
H
X
L
H
L
H
X
CA
X
H
Program/Erase(6)
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
H
L
L
L
X
H
H
X
L
L
L
X
L
L
L
X
X
X
X
L
X
X
X
X
X
X
X
CA
CA
X
X
X
X
X
X
X
X
12V
X
L
L
Fast Program/Erase(6)
Program/Erase Inhibit
X
X
X
H
L
Mode Register Set
Read
A7 = H
L
X
Product
Identification(7)
H
H
X
H
X
X
X
Entry
CA
X
Continuity Test Mode
Exit
Code(8)
X
X
Notes: 1. A0 ~ A6: Program keys (@MRS). After power-up, mode register set can be set before issuing other input command. After the
Mode Register Set command is completed, no new commands can be issued for 3 CLK Cycles, and CS or MR state must
be defined “H” within 3 CLK cycles. Refer to the Mode Register Control Table.
2. In the case CKE is low, two standby modes are possible. Those are standby mode in power-down, and active standby mode
in clock suspend (non-power-down).
Power-down: CKE = “L” (after no command is issued for 60 µs)
Clock Suspend: CKE = “L” (at the range of Row Active, Read and Data Out)
3. DQM sampled at rising edge of a CLK makes a high-Z state the data-out state, delayed by 2 CLK cycles.
4. Precharge command on Synch. DRAM can be used for Burst Stop operation during burst read operation only.
5. Mode selection is controlled by the polarity of WORD pin, “H” state is DWM, “L” state is WM. WORD should be set to the
desired state during power-up and prior to any device operation.
6. Data is provided through DQ0 ~ DQ31. Refer to AC programming and erasing waveforms.
7. DQ0 ~ DQ31 will output Manufacturer Code/Device Code.
8. A0 = A2 = A11 = “H”, A1 = A10 = A12 = “L”
9. The user can tie MR and WE together to simplify the interface of the AT49LD3200(B) onto the standard SDRAM bus.
8
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Asynchronous Boot Block Function Truth Table
Command
CLK(2)
CKE(2)
CS
RAS
CAS
MR
DQM
Add.
Add
X
WORD
VPP
X
WE
X
Read
X
X
X
X
H
H
H
L
X
X
X
L
H
X
X
X
X
X
X
X
X
Output Disable
Program/Erase(1)
Fast Program/Erase(1)
Program/Erase Inhibit
L
X
X
X
X
X
L
H
L
X
Add
Add
X
X
L
L
H
L
X
12V
X
L
H
X
X
X
X
Notes: 1. Program/Erase is performed through the synchronous bus cycle operation after the boot block is activated through either
power-up or Mode Register Set.
2. It is recommended to hold CKE Low if CLK is running during asynchronous boot block mode except for synchronous com-
mand cycle and MRS operations.
Mode Register Control Table(1)
Register Programmed with MRS
Address
Function
A7
A6
A5
A4
A3
A2
A1
A0
Product ID
RAS Latency
CAS Latency
Burst Type
Burst Length
Product ID
RAS Latency
Type
CAS Latency
A5 A4 A3 Length
Burst Type
Type
Burst Length
A7
“Read”
Array
ID
A6
0
A2
0
A1
0
A0
0
Length
0
1
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Sequential
Interleave
Reserved
1
2
3
4
5
6
7
8
1
0
1
4
8
1
0
1
1
Boot Block
Note:
1. After power-up, when the user wants to change Mode Register Set, the user must exit from power-down mode and start
Mode Register Set before entering normal operation mode. Reserved modes are not to be used; device function in these
modes is not guaranteed.
9
1940B–FLASH–11/01
Addressing Map
WORD = “H”: x32 Organization(1)
Function
A0
A1
A2
A3
A4
A5
A6
A7
RA7
X
A8
RA8
X
A9
RA9
X
A10
RA10
X
A11
RA11
X
A12
RA12
X
Row Address
Column Address
RA0
CA0
RA1
CA1
RA2
CA2
RA3
CA3
RA4
CA4
RA5
CA5
RA6
(1)
CA6
Note:
1. Column Address MSB (at x32 organization) (X = Don’t Care)
WORD = “L”: x16 Organization(1)
Function
A0
A1
A2
A3
A4
A5
A6
A7
A8
RA8
X
A9
RA9
X
A10
RA10
X
A11
RA11
X
A12
RA12
X
Row Address
Column Address
RA0
CA0
RA1
CA1
RA2
CA2
RA3
CA3
RA4
CA4
RA5
CA5
RA6
CA6
RA7
(1)
CA7
Note:
1. Column Address MSB (at x16 organization) (X = Don’t Care)
Each Address is Arranged as Follows(1)(2)
For X32 operation,
MSB
LSB
AR0
CA0
Address Register
Address
AR19
RA12
AR18
RA11
AR17
RA10
...
...
AR8
RA1
AR7
RA0
AR6
CA6
...
...
AR3
CA3
AR2
CA2
AR1
CA1
BL = 4
* Initial Address BL = 8
Notes: 1. For X16 operation, when CA0 is set to Low, data belonging to 0 ~ 15th registers are output to DQ0 ~ DQ15 pins, and when
CA0 is set to High, data belonging to 16 ~ 31th registers are output to DQ0 ~ DQ15 pins.
2. Asynchronous Boot Block uses x16 operation and A0 ~ A12 as address inputs.
10
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Burst Sequence (Burst Length = 4)
Initial Address
A1
0
A0
0
Sequential
Interleave
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
Burst Sequence (Burst Length = 8)
Initial Address
A2
0
A1
0
A0
0
Sequential
Interleave
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
0
0
1
7
0
1
2
3
4
5
3
0
1
6
7
4
5
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Device Operations
Clock (CLK)
A square wave signal (CLK) must be applied externally at cycle time tCC. All operations
are synchronized to the rising edge of the clock. The clock transitions must be mono-
tonic between VIL and VIH. During operation with CKE high, all inputs are assumed to be
in valid state (low or high) for the duration of setup and hold time around the positive
edge of the clock for proper functionality and ICC specifications.
Clock Enable (CKE)
The clock enable (CKE) gates the clock into the AT49LD3200(B) and is asserted high
during all cycles, except for power-down, standby and clock suspend mode. If CKE goes
low synchronously with clock (setup and hold time same as other inputs), the internal
clock is suspended from the next clock cycle and the state of output and burst address
is frozen for as long as the CKE remains low. All other inputs are ignored from the next
clock cycle after CKE goes low. The AT49LD3200(B) remains in the power-down mode,
ignoring other inputs for as long as CKE remains low. The power-down exit is synchro-
nous as the internal clock is suspended. When CKE goes high at least “1 CLK + tSS
”
before the rising edge of the clock, then the AT49LD3200 becomes active from the
same clock edge accepting all the input commands.
NOP and Device
Deselect
When RAS, CAS and MR are high, the AT49LD3200(B) performs no operation (NOP).
NOP does not initiate any new operation. Device deselect is also a NOP and is entered
by asserting CS high. CS high disables the command decoder so that RAS, CAS, MR
11
1940B–FLASH–11/01
and all the address inputs are ignored. In addition, entering a Mode Register Set com-
mand in the middle of a normal operation results in an illegal state in the
AT49LD3200(B).
Power-up
The following power-up sequence is recommended.
1. Apply power and start clock. Hold the MR, CKE and DQM inputs high; all other
pins are a NOP condition at the inputs before or along with VCC (and VCCQ
)
supply.
2. Set WORD to the desired state (prior to any device operation).
3. To change the default Mode Register Set values, perform a Mode Register Set
cycle to program the RAS latency, CAS latency, burst length and burst type.
4. At the end of three clock cycles after the mode register set cycle, the device is
ready for operation.
When the above sequence is used for power-up, all outputs will be in high impedance
state. The high impedance of outputs is not guaranteed in any other power-up
sequence.
For AT49LD3200B, Asynchronous Boot Block will be selected after power-up.
Mode Selection Control
Address Decoding
Mode selection is controlled by the polarity of WORD pin. WORD should be set to the
desired state during power-up and prior to any device operation. The AT49LD3200(B)
can be organized as either double word wide (x32) or word wide (x16). The organization
is selected via the WORD pin. When WORD is asserted high (VIH), the double word-
wide organization is selected. When WORD is asserted low (VIL), the word-wide organi-
zation is selected.
The address bits required to decode one of the available cell locations out of the total
depth are multiplexed onto the address select pins and latched by externally applying
two commands. The first command, RAS asserted low, latches the row address into the
device. A second command, CAS asserted low, subsequently latches the column
address.
Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of
AT49LD3200(B). It programs the RAS latency, CAS latency, burst length, burst type,
selects product ID Read or activates the Asynchronous Boot Block. For
AT49LD3200(B), the default value of the mode register is defined as array read with
RAS latency = 2, CAS latency = 5, burst length = 4, sequential burst type. When and if
the user wants to change its values, the user must exit from power-down mode and start
Mode Register Set before entering normal operation mode. The mode register is repro-
grammed by asserting low on CS, RAS, CAS and MR (the AT49LD3200(B) should be in
active mode with CKE already high prior to writing the mode register). The state of
address pins A0 ~ A7 in the same cycle as CS, RAS, CAS and MR going low is the data
written in the mode register. Three clock cycles are required to complete the program in
the mode register, therefore after a Mode Register Set command is completed, no new
commands can be issued for 3 clock cycles and CS or MR must be high within 3 clock
cycles. The mode register is divided into various fields, depending on functionality. The
burst length field uses A0 ~ A1, burst type uses A2, CAS latency (read latency from col-
umn address) uses A3 ~ A5, RAS latency uses A6 (RAS to CAS delay), array read or
product ID read uses A7. Refer to Mode Register Control Table for specific codes for
various burst lengths, burst types, CAS latencies, RAS latencies, and read modes.
12
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Latency
There are latencies between the issuance of a Row Active command and when data is
available on the I/O buffers. The RAS to CAS delay is defined as the RAS latency. The
CAS to data out delay is the CAS latency. The CAS and RAS latencies are programma-
ble through the mode register. RAS latencies of 1 and 2, and CAS latencies of 2 through
6 are supported. It is understood that some RAS and CAS latency values are reserved
for future use, and are not available in this generation of synchronous Flash. The follow-
ing are the supported minimum values: RAS latency = 2, and CAS latency = 6 for 100
MHz operation, and RAS latency = 2, and CAS latency = 5 for 66 MHz operation, and
RAS latency = 1, and CAS latency = 4 for 50 MHz operation, and RAS latency = 1, and
CAS latency = 3 for 33 MHz operation.
DQM Operation
Burst Read
The DQM is used to mask output operations when a complete burst read is not required.
It works similar to OE during a read operation. The read latency is two cycles from DQM,
which means DQM masking occurs two cycles later in the read cycle. DQM operation is
synchronous with the clock. The masking occurs for a complete cycle. (Also refer to the
DQM timing diagram.)
The Burst Read command is used to access a burst of data on consecutive clock cycles
from an active row state. The Burst Read command is issued by asserting low CS and
CAS with MR being high on the rising edge of the clock. The first output appears in CAS
latency number of clock cycles after the issuance of the Burst Read command. The
burst length, burst sequence and latency from the Burst Read command are determined
by the mode register, which is already programmed. Burst read can be initiated on any
column address of the active row. The output goes into high-impedance at the end of
the burst, unless a new burst read is initiated to keep the data output gapless. The burst
read can be terminated by issuing another burst read.
Sector Erase
Before a word/double word can be reprogrammed, it must be erased. The erased state
of the memory bits is a logical “1”. The AT49LD3200(B) is organized into eight uniform
four megabit sectors (SA0 - SA7) that can be individually erased. The Sector Erase
command is a synchronous six-bus cycle operation (refer to the Command Definition
table and Program Cycle and Erase Cycle waveforms). The erase code consists of 6-
byte (DQ8 - DQ31 are Don’t Care inputs for the command) load commands to specific
address locations with a specific data pattern. The sector address and 30H data input
are latched in the sixth cycle. The sector erase starts at the following rising edge of CLK
after the sixth cycle. The erase operation is internally controlled; it will automatically time
to completion.
Any commands written to the device during the erase cycle will be ignored. The maxi-
mum time needed to erase one sector is tEC
.
Word/Double Word
Programming
Once a sector is erased, it is programmed (to a logical “0”) on a word-by-word/double-
word-by-double-word basis. Programming is accomplished via the internal device com-
mand register and is synchronous four-bus cycle operation (refer to the Command
Definition table and Program Cycle and Erase Cycle waveforms). The programming
operation starts at the following rising edge of CLK after the fourth cycle. The device will
automatically generate the required internal program pulses.
Any commands written to the device during the embedded programming cycle will be
ignored. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tPGM
cycle time. The DATA polling feature may also be used to indicate the end of a program
cycle.
13
1940B–FLASH–11/01
Product Identification
DATA Polling
The product identification mode identifies the device and manufacturer as Atmel. This
mode can be used by an on-board controller or external programmer to identify the cor-
rect programming algorithm for the Atmel product.
The AT49LD3200(B) features DATA polling to indicate the end of a program or sector
erase cycle. DATA polling may begin at any time during the program or sector erase
cycle.
During a program cycle, an attempted read of the last word/double word loaded will
result in the complement of the loaded data in DQ7. Once the program cycle has com-
pleted, true valid data can be read on all outputs and the next cycle may begin.
During a sector erase operation, an attempt to read the device will give a “0” on DQ7.
Once the sector erase cycle has completed, logical “1” data can be read on all outputs
from the device.
Hardware Data
Protection
Hardware features protect against inadvertent programming or erasure to the
AT49LD3200(B) in the following way: VCC sense: if VCC is below 2.3V (typical), the pro-
gram or erase function is inhibited; but if VCC dips below 2.3V during program or erase
cycle, the respective function will be interrupted and the data at the location being pro-
grammed may be corrupted.
Continuity Test Mode
The AT49LD3200(B) has built-in circuitries to make input and output pin continuity
check simple and easy. This mode can be activated via the internal device command
register and is a synchronous five-bus cycle operation (refer to the Command Definition
Table and Continuity Test Mode Entry Waveforms). After the bus cycle operation, keep
DQM high (VIH) and allow 5 µsec for circuit setup time or until data is no longer asserted
at DQ0 - DQ7, whichever takes longer. This will keep DQ0 - DQ7 from contention since
data is asserted at DQ0 - DQ7 during the mode entry sequence. Then DQM can be
asserted low (VIL) to enable DQ0 - DQ7 for test. Once in this asynchronous mode, input
pins are virtually tied to output pins internally forming input - output pin pairs. The output
pin of the pair will follow the logic state of the input pin of the pair (refer to the Input -
Output Pin Pairs table). To exit the mode, A0, A2 and AII are asserted high (VIH) and A1,
A10 and A12 are asserted low (VIL), allow 5 µsec for circuit recovery time before returning
the device for normal operation.
14
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Input - Output Pin Pairs
Input
MR
RAS
CAS
DQM
CS
Output
DQ0, DQ16
DQ1, DQ17
DQ2
DQ18
DQ3
WORD
A12
A11
A10
A0
DQ19
DQ4
DQ20
DQ5
DQ21
A1
DQ6, DQ22
DQ7, DQ23
DQ8, DQ24
DQ9, DQ25
DQ10
A2
A3
A4
A5
A6
DQ26
A7
DQ11
A8
DQ27
A9
DQ12
CKE
CLK
WE
VPP
DQ28
DQ13, DQ29
DQ14, DQ30
DQ15, DQ31
Asynchronous Boot
Block
The AT49LD3200B will automatically activate the Asynchronous Boot Block after
power-up and the AT49LD3200 can activate the Asynchronous Boot Block through the
Mode Register Set. The size of the boot block is 8K x 16 bits with addresses A0 ~ A12
and outputs DQ0 ~ DQ15. The contents of the boot block are accessed asynchronously,
meaning the data at outputs will change according to the address inputs after tACC, with-
out any external clocking signals.
Programs and erases are performed using the synchronous bus cycle operation (refer
to Command Definitions table and Program Cycle and Erase Cycle waveforms) after the
boot block is activated either through power-up or Mode Register Set. Programming of
the boot block is set up for x16 mode.
This Asynchronous Boot Block has a lockout feature that prevents programming or
erasing of data in this boot block once the feature has been enabled. This feature does
not have to be activated; the boot block’s usage as a protected region is optional to the
user. Once this feature is enabled, the data in the boot block can no longer be erased or
programmed when input levels of 3.6V or less are used. To activate the lockout feature,
15
1940B–FLASH–11/01
Boot Block Lockout command, which is a synchronous five-bus cycle operation, must be
performed (refer to Command Definitions table and Program Cycle Waveforms).
A software method is available to determine if programming or erasing of the boot block
is locked out. Issue Boot Block Lockout Verify command and observe DQ0 ~ DQ7. If the
data show 00H/02H, the boot block can be programmed or erased; if the data show
01H/03H, the lockout feature has been enabled and the boot block cannot be pro-
grammed or erased. The Boot Block Lockout Verify Exit command should be used to
return to standard operation (refer to Command Definition table and Boot Block Lockout
Verify Waveforms).
The user can override the boot block lockout by taking the MR pin to 12 volts after the
boot block is activated. When the MR pin is brought back to TTL levels, the boot block
lockout feature is again active.
16
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Command Definition in Hex(1)
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
6th Bus Cycle
CA Data
Command
Bus
Sequence Cycles RA
CA Data RA CA Data RA
CA Data RA
CA Data RA
CA Data RA
Word/
Double
Word
4
AA
55
AA
55
2A
55
AA
55
A0
RA
CA
DIN
Program
Sector
Erase
6
5
5
5
AA
AA
AA
AA
55
55
55
55
AA
AA
AA
AA
55
55
55
55
2A
2A
2A
2A
55
55
55
55
AA
AA
AA
AA
55
55
55
55
80
80
80
80
AA
AA
AA
AA
55
55
55
55
AA
AA
AA
AA
55
2A
55
55
55
55
SA(2)
X
30
Continuity
Test Mode
Entry
AA
AA
AA
70
40
90
Boot Block
Lockout
Boot Block
Lockout
Verify
Boot Block
Lockout
5
AA
55
AA
55
2A
55
AA
55
80
AA
55
AA
AA
55
F0
Verify Exit
Notes: 1. The DATA FORMAT in each bus cycle is as follows: DQ31 - DQ8 (Don’t Care); DQ7 - DQ0 (Hex).
2. SA = Sector Addresses: Any word/double word address within a sector can be used to designate the sector address.
See Sector Address Mapping table below.
3. Allow minimum 200 ns after Boot Block Lockout Verify command and before Read.
4. Allow minimum 10 µs after Boot Block Lockout Verify Exit command for the device to return to standard operation.
Sector Address Mapping
x16
x32
Address Range
Address Range
Sector
Size (Word/Double Word)
CA7-0
RA12-0
CA6-0
RA12-0
00XX
03XX
00XX
03XX
SA0
256K/128K
X
X
04XX
07XX
04XX
07XX
SA1
SA2
SA3
SA4
SA5
SA6
SA7
256K/128K
256K/128K
256K/128K
256K/128K
256K/128K
256K/128K
256K/128K
X
X
X
X
X
X
X
X
X
X
X
X
X
X
08XX
0BXX
08XX
0BXX
0CXX
0FXX
0CXX
0FXX
10XX
13XX
10XX
13XX
14XX
17XX
14XX
17XX
18XX
1BXX
18XX
1BXX
1CXX
1FXX
1CXX
1FXX
17
1940B–FLASH–11/01
Basic Feature and Function Descriptions
MRS
Mode Register Set
CLK
CMD
MRS
ACT
(1)
3CLK
Clock Suspend
Clock Suspended During Burst Read (BL=4)
CLK
CMD
CKE
RD
Masked by CKE
Internal
CLK
DQ0 DQ1
Data
DQ2
DQ3
: This command cannot be activated.
Suspended Dout
Clock Suspend Exit and Power-down Exit
1) Clock Suspend Exit
2) Power Down
CLK
CLK
CKE
tSS
tSS
CKE
Internal
CLK
Internal
CLK
NOP ACT
CMD
CMD
RD
Note:
After Mode Register Set command is completed, no new commands can be issued for 3 clock cycles, and MR or CS should be
fixed “H” within a minimum of 3 clock cycles.
18
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
DQM Operation
1) Read Mask (BL=4)
CLK
CMD
DQM
RD
Masked by DQM
High-Z
Data(CL2)
Data(CL3)
Data(CL4)
DQ3
DQ2
DQ0
DQ1
DQ0
High-Z
High-Z
DQ3
DQ3
DQ1 DQ2
DQM to Data-out Mask = 2CLKs
2) DQM with Clock Suspended (BL=8)
CLK
RD
CMD
CKE
DQM
(1)
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ0
DQ1
DQ0
DQ5
DQ7
DQ6
DQ
DQ3
DQ2
DQ1
Data(CL2)
Data(CL3)
Data(CL4)
High-Z
High-Z
DQ4
DQ3
7
DQ
DQ6 DQ7
5
Note:
DQM makes data out high-Z after 2 CLKs, which should be masked by CKE “L”.
19
1940B–FLASH–11/01
Read Cycle I: Normal @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
tCH
4
0
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
tCL
tCC
HIGH
tRC
tSH
tSS
CS
RAS
Latency
tSH
tSS
RAS
CAS
tSH
RAa
tSS
ADDR
CAa
RAb
CAb
(1)
tRC=6 clocks at BL=4
tOH
DQa0 DQa1 DQa2 DQa3
tSAC
DQb0 DQb1 DQb2 DQb3
Data
MR
tSHZ
: Don't Care
Row Active
Read
Row Active
Read
Note:
When the burst length is 4 at 66 MHz, tRC is equal to 6 clock cycles.
20
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Read Cycle II: Consecutive Column Access @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
tCL
tCC
HIGH
tSH
CS
t
SS
RAS
Latency
t
SH
SS
RAS
t
CAS
t
SH
RAa
SS
CAa
CAb
ADDR
t
t
VCVC=4 clocks at BL=4
tOH
Burst Length=4
DQa0 DQa1 DQa2 DQa3 DQb0 DQb1 DQb2 DQb3
Data
MR
tSAC
tSHZ
Row Active
Read
Read
: Don't Care
Note:
When column access is initiated beyond tVCVC, at BL = 4, CAa access read is completed, CAb access read begins.
21
1940B–FLASH–11/01
Read Cycle III: Clock Suspend @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
t
CH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
tCL
t
CC
(1)
Internal
CLK
CS
RAS
Latency
t
SH
SS
RAS
t
CAS
t
SH
RAa
SS
CAa
ADDR
t
tVCVC= 4 clocks at BL=4
(2)
DQa2
Burst Length=4
DQa0
DQa3
DQa1
Data
MR
Row Active
Read
Clock Suspend Resume
: Don't Care
Notes: 1. From next clock after CKE goes low, clock suspension begins.
2. For clock suspension, data output state is held and maintained.
22
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Read Interrupted by Precharge Command and Burst Read Stop Cycle @Burst Length = 8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
HIGH
CS
RAS
CAS
RAa
CAa
CAb
ADDR
CL=2
(1)
DQb0 DQb1 DQb2 DQb3 DQb4 DQb5
(1)
DQa0 DQa1 DQa2 DQa3 DQa4
Data
(2)
DQb0 DQb1 DQb2 DQb3 DQb4 DQb5
(2)
DQa0 DQa1 DQa2 DQa3 DQa4
CL=3
MR
DQM
(1)(2)
Burst Stop
Row Active
Read
Read
Precharge
: Don't Care
Notes: 1. The Burst Stop command is valid at every page burst length. The data bus goes to high-Z after the CAS latency from the
Burst Stop command is issued.
2. The interval between Read command (column address presented) and Burst Stop command is 1 cycle (min).
23
1940B–FLASH–11/01
Power-down and Clock Suspend Cycle: @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tSS
(1)
(1)
CKE
Power Down
Clock Suspend
(3)
CLK
(internal)
CS
RAS
CAS
t
SH
(2)
ADDR
NOP RAa
SS
CAa
t
Data High-Z State
DQa0 DQa1
DQa2
DQa3
Data
(High)
MR
Row Active
Read
Power-down
Entry
Power-down
Exit
Clock Suspend
Exit
Clock Suspend
Entry
: Don't Care
Notes: 1. From next clock after CKE goes low, clock suspend and power-down begins.
2. After power-down exit, NOP should be issued and new command can be issued after 1 clock.
3. Clock suspend is in active standby mode.
24
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Mode Register Set: @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
t
CH
4
0
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
tCL
tCC
HIGH
tSH
CS
t
SS
RAS
CAS
ADDR
Data
Code
RAa
CAa
Data High-Z State
DQa0 DQa1 DQa2 DQa3
MR
MRS
Row Active
: Don't Care
Notes: 1. After the Mode Register Set is completed, no new commands can be issued for 3 CLK cycles.
2. After power-up, necessarily Mode Register Set should be completed at least one time and CS or MR must be fixed “H” within
3 clock cycles, and when user wants to change Mode Register Set, user must exit from power-down mode and start Mode
Register Set before chip enters normal operation mode.
25
1940B–FLASH–11/01
Detailed Functional Truth Table
Input Signal
Current
State
CKE
L
CS
X
RAS
CAS
X
MR
X
Add.
X
Next State Operation
Power-down
X
L
L
After
H
L
H
H
RA
Row Active; latch RA
Mode Register Set
Power-up(1)
H
L
L
L
Code
If consecutive row access is issued within tRC (min.)
without CAS enabling, only the final RA is valid.
H
L
L
H
H
RA
H
H
L
L
L
X
H
L
L
L
X
H
L
CA
Code
X
Begin READ; latch CA
Illegal(1)
Row Active
X
X
Clock Suspend
Row Access in Read State, within the tRC, previous
read is ignored and new row is activated. Beyond the
tRC, previous read is completed and new read
begins.
H
H
L
L
L
H
L
H
H
RA
CA
Consecutive Column Access, within the tVCVC, only
the final CA is valid and the previous burst read is
ignored. Beyond the tVCVC, the previous read is
completed and new read begins.
H
READ
H
H
H
L
L
L
L
X
L
L
L
L
L
H
L
H
H
L
L
L
X
X
NOP (after Burst Read)/Read Interrupt
NOP (after Burst Read)/Read Interrupt
L
Code
X
Illegal(1)
X
L
X
L
X
H
H
H
L
Clock Suspend/Power-down
Any State
Any State
L
X
Low Power Consumption Mode
H
H
H
H
L
H
L
X
NOP
X
Illegal
Illegal
Any State
H
L
CA
Note:
1. After the power-up, when user wants to change MR Set, user must exit from power-down mode and start MR Set before chip
enters normal operation mode.
26
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Technical Notes
Frequency vs. AC Parameter Relationship Table(1)
<100 MHz
Burst Length
RAS Latency
CAS Latency
tRC (min)
tVCVC (min)
6
7
6
7
7
8
5(2)
4
2
6
11
12
9(2)
10
8
2
<75 MHz
Burst Length
RAS Latency
CAS Latency
tRC (min)
tVCVC (min)
5
6
5
6
6
7
4(2)
4
2
5
10
11
8(2)
9
8
2
<50 MHz
Burst Length
RAS Latency
CAS Latency
tRC (min)
tVCVC (min)
4
5
6
4
5
6
4(2)
3/4(2)
4(2)
5
4
1
5
6
8(2)
7/8(2)
8(2)
9
8
1
9
10
Notes: 1. Above tables are not specifications values, but rather the actual number of clock cycles. There are no gapless operations for
CAS latency 7 and 8.
2. Minimum clocks for gapless operation.
3. tRC (max) = tVCVC (max) = 50 µs. If tRC (max) or tVCVC (max) has been reached, a new “ACTIVE” command is necessary for
new access.
27
1940B–FLASH–11/01
CAS Interrupt
Read interrupted by Read (BL=4) (1)
CLK
RD RD
CMD
A
B
ADD
Data(CL2)
DQB0 DQB1
DQB0
2
DQB
DQB3
Data(CL3)
Data(CL4)
DQB1 DQB2 DQB3
DQB0 DQB1 DQB2
DQB3
(2)
Notes: 1. By “Interrupt”, it is meant to stop Burst Read by external command before the end of burst. By “CAS Interrupt”, to stop Burst
Read by CAS access.
2. CAS to CAS delay (=1 CLK).
Read Interrupt Operation by Issuing the Precharge of Burst Stop Command
CASE I ) Issued read Interrupt command during burst read operation period.
CLK
CMD
CLK
STOP
RD
PRE
DQ0
RD
CMD
(1)
(1)
Data(CL2)
DQ1
DQ0 DQ1
DQ0 DQ1
DQ0 DQ1
Data(CL2)
Data(CL3)
Data(CL4)
DQ0 DQ1
Data(CL3)
Data(CL4)
DQ0 DQ1
CASE II ) Issued read Interrupt command between read command and data out.
CLK
CLK
STOP
RD PRE
RD
CMD
CMD
(2)
(2)
Data(CL2)
DQ0
DQ0
Data(CL2)
Data(CL3)
Data(CL4)
DQ0
DQ0
Data(CL3)
Data(CL4)
DQ0
DQ0
Notes: 1. The data bus goes to high-Z after CAS latency from the Burst Stop (or precharge) command.
2. Valid output data will last up to CL-1 clock cycle from PRE command.
28
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Read Cycle Depending on tRC
@RL = 2, CL = 6, BL = 4; 100 MHz
CLK
tRC(min)=7
tCC=10ns
CASE I )
CMD
ACT
RDa
ACT
RDb
ACT
CASE II )
ACT
RDb
CASE III )
RDb
High-Z
CASE I )
DQb
0
DQb
1
DQb
DQb
DQb
2
DQb
DQb
DQb
3
DQa
0
DQa
1
DQa
DQa
2
DQa
DQa
3
DQb
0
1
2
DQb
3
CASE II )
CASE III )
DQa
0
DQa
1
2
3
0
1
DQb
2 DQb3
@RL = 2, CL = 5, BL = 4; 75 MHz
CLK
tRC(min)=6
tCC=15ns
CASE I )
CMD
ACT
RDa
ACT
RDb
ACT
CASE II )
ACT
RDb
CASE III )
RDb
High-Z
CASE I )
DQb0 DQb1 DQb2 DQb3
DQb0 DQb1 DQb2 DQb3
DQb0 DQb1 DQb2 DQb3
DQa0 DQa1 DQa2 DQa3
DQa0 DQa1 DQa2 DQa3
CASE II )
CASE III )
@RL = 1, CL = 4, BL = 4; 50 MHz
CLK
tRC(min)=4
tCC=20ns
CASE I )
CMD
ACT RDa
ACT RDb
ACT
CASE II)
RDb
CASE III)
ACT RDb
DQb
DQa
DQa
0
DQb
1
DQb
2
DQb
DQb
DQb
3
CASE I )
(Gapless Operation)
3
DQa
0
DQa
1
DQa
DQa
2
2
3
DQb
0
DQb
1
0
2
DQb
DQb
CASE II )
CASE III )
DQa
0
DQa
1
3
DQb
1
2 DQb3
29
1940B–FLASH–11/01
Read Cycle Depending on tVCVC
@RL = 2, CL = 6, BL = 4; 100 MHz
CLK
tVCVC=5
tCC=10ns
CASE I)
CMD
RDa
RDb
ACT
CASE II)
RDb
CASE III)
RDb
CASE I )
DQb
DQa
DQa
0
DQb
1
DQb
2
DQb
3
2
(Gapless Operation)
3
CASE II )
CASE III )
DQa
0
DQa
1
DQa
DQa
2
2
3
DQb
0
DQb
1
0
DQb
DQb
DQb
3
DQa
0
DQa
1
DQb
DQb
1
2 DQb3
@RL = 2, CL = 5, BL = 4; 75 MHz
CLK
tVCVC=4
tCC=15ns
CASE I)
CMD
RDa
RDb
ACT
CASE II)
RDb
CASE III)
RDb
CASE I )
DQb
DQa
DQa
0
DQb
1
DQb
2
DQb
3
2
(Gapless Operation)
3
CASE II )
CASE III )
DQa
0
DQa
1
DQa
DQa
2
2
3
DQb
0
DQb
1
0
DQb
DQb
DQb
3
DQa
0
DQa
1
DQb
DQb
1
2 DQb3
@RL = 1, CL = 4, BL = 4; 50 MHz
CLK
tVCVC=3
tCC=20ns
CASE I)
RDb
CMD
RDa
RDb
ACT
CASE II)
CASE III)
RDb
CASE I )
DQb
DQa
DQa
0
DQb
1
DQb
2
DQb
3
2
CASE II )
CASE III )
DQa
0
DQb
1
DQb
DQb
3
DQa
1
2
(Gapless Operation)
DQa
0
DQa
1
2
DQa
3
DQb
0
DQb
1
DQb
2
DQb3
: Invalid Data
30
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
AC Characteristics for Boot Block Read Operation
Symbol
Parameter
Condition
Min
Max
Units
CS = DQM
= VIL
tACC
Address to Output Delay
170
ns
tOE
tDF
tOH
DQM to Output Delay
CS = VIL
60
40
ns
ns
ns
DQM High to Output Float
Output Hold from Address
0
AC Waveforms for Boot Block Read Operation
ADDRESS
ADDRESS VALID
CS
tOE
DQM
tDF
tACC
tOH
HIGH-Z
OUTPUT
OUTPUT VALID
31
1940B–FLASH–11/01
l
3-volt Program and Erase Cycle Characteristics
Symbol
tPGM
tEC
Parameter
Typ
Max
600
Units
µs
Word/Double Word Programming Time
Sector/Boot Block Erase Cycle Time
Boot Block Lockout Enable Time
VCC Current during Program and Erase Cycle
50
2.0/300
10
seconds/ms
ms
tBBL
ICC2
150
mA
High-speed 12-volt Program and Erase Cycle Characteristics
Symbol
tPGM
tEC
Parameter
Typ
Max
200
Units
µs
Word/Double Word Programming Time
Sector/Boot Block Erase Cycle Time
VCC Current During Program and Erase Cycle
VPP Current During Program and Erase Cycle
15
1.2/200
75
seconds/ms
mA
ICC3
IPP3
75
mA
Program Cycle Waveforms
PROGRAM CYCLE
CLK
CS
t
PGM
WE
RAS
CAS
AA
AA
55
55
2A
55
RA
55
CA
ADDR
DATA
PRECHARGE COMMAND
PRECHARGE COMMAND
PRECHARGE COMMAND
PRECHARGE COMMAND
AA
A0
D
IN
Sector Erase Cycle Waveforms
SECTOR ERASE CYCLE
CLK
CS
tEC
WE
RAS
CAS
AA
55
55
2A
55
AA
AA
55
55
2A
55
SA
X
55
80
ADDR
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
AA
AA
30
DATA
Notes: 1. The Precharge command is optional. A Precharge command (CS, RAS, MR = L) during Program and Sector Erase cycles
(WE = L) will be treated as NOP, and the number of clock cycles between the bus cycle and the Precharge command or vice
versa should be “Don’t Care”.
2. For boot block programming, RA = CA = A0 ~ A12 and be held valid throughout program cycle; DQM should be held “H” dur-
ing the four-bus cycle command operation.
3. For boot block erasing, SA = X; DQM should be held “H” during the six-bus cycle command operation.
32
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Data Polling Waveforms
tPGM/tEC
CLK
DQM
CS
WE
RAS
CAS
RA
CA
RA
CA
ADDR
READ
READ
(DATA POLLING)
DQ7
DATA
DATA
(RL2, CL5, BL4)
Note:
During Program cycle, DATA = complement of loaded DQ7.
After Program cycle, DATA = same state as loaded DQ7.
During Sector Erase cycle, DATA = “0”; after Sector Erase cycle, DATA = “1”.
Data Polling Waveforms for Boot Block
t
/t
PGM EC
CLK
DQM
CS
WE
RAS
CAS
VALID ADDRESS
ADDR
READ
READ
(DATA POLLING)
DQ7
DATA
DATA
(RL2, CL5, BL4)
Note:
During Program cycle, DATA = complement of loaded DQ7.
After Program cycle, DATA = same state as loaded DQ7.
During Sector Erase cycle, DATA = “0”; after Sector Erase cycle, DATA = “1”.
33
1940B–FLASH–11/01
Product ID Cycle Waveforms
PRODUCT ID CYCLE
CLK
DQM
CS
WE
RAS
CAS
ADDR
A7
DATA
DC
MC
C
(CL5, BL4, X16)
DATA
(CL5, BL4, X32)
MR
MRS
READ
Note:
For x16 Mode, Manufacturer Code, MC = 001F(HEX), Device Code, DC = 32C2 (HEX).
For x32 Mode, Code, C = 32C2001F (HEX).
Continuity Test Mode Entry Waveforms
CLK
DQM
CS
WE
RAS
CAS
AA
AA
55
2A
55
AA
55
AA
55
70
55
55
80
ADDR
DATA
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
AA
AA
34
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Boot Block Lockout Cycle Waveforms
BOOT BLOCK LOCKOUT CYCLE
CLK
CS
t
BBL
WE
RAS
CAS
AA
AA
55
55
2A
55
AA
55
AA
55
40
55
80
ADDR
DATA
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
AA
AA
Boot Block Lockout Verify Cycle Waveforms
BOOT BLOCK LOCKOUT VERIFY CYCLE
CLK
CS
200 ns
WE
RAS
CAS
AA
55
55
2A
55
AA
AA
55
AA
55
55
80
ADDR
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
READ
DATA
(CL5, BL4)
AA
DQ
AA
90
Note:
DQ = XX00 (Hex) implies Boot Block not activated and Lockout not enabled.
DQ = XX01 (Hex) implies Boot Block not activated and Lockout enabled.
DQ = XX02 (Hex) implies Boot Block activated and Lockout not enabled.
DQ = XX03 (Hex) implies Boot Block activated and Lockout enabled.
35
1940B–FLASH–11/01
Boot Block Lockout Verify Exit Cycle Waveforms
BOOT BLOCK LOCKOUT VERIFY EXIT CYCLE
CLK
CS
10 µs
WE
RAS
CAS
AA
AA
55
55
2A
55
AA
55
AA
55
F0
55
80
ADDR
DATA
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
PRECHARGE
COMMAND
AA
AA
36
AT49LD3200(B)
1940B–FLASH–11/01
AT49LD3200(B)
Ordering Information
ICC (mA)
Max Freq
(MHz)
Active
Standby
Ordering Code
Package
Operation Range
100
150
0.05
AT49LD3200-10TC
86T
Commercial
(0L to 70LC)
150
150
150
150
150
0.05
0.05
0.05
0.05
0.05
AT49LD3200-10TI
AT49LD3200-13TC
AT49LD3200-13TI
AT49LD3200-20TC
AT49LD3200-20TI
86T
86T
86T
86T
86T
Industrial
(-40L to 85LC)
75
50
Commercial
(0L to 70LC)
Industrial
(-40L to 85LC)
Commercial
(0L to 70LC)
Industrial
(-40L to 85LC)
Package Type
86-lead, Thin Small Outline Package (TSOP Type II)
86T
37
1940B–FLASH–11/01
Packaging Information
86T – TSOP Type II
0˚ ~ 8˚
c
E
E1
L
PIN 1 Identifier
L1
b
PIN 1
GAGE PLANE
SEATING PLANE
D
A
e
A2
A1
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
0.15
1.05
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
22.12
11.56
10.06
0.40
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation EC.
2. Dimensions D and E1 do not include mold protrusion. Allowable
protrusion on E1 is 0.25 mm per side and on D is 0.15 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
22.22
11.76
10.16
0.50
22.32 Note 2
11.96
E
E1
L
10.26 Note 2
0.60
L1
b
0.25 BASIC
0.22
0.17
0.12
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
86T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
86T, 86-lead (10.16 mm Body Width) Thin Small Outline Package
(TSOP Type ll)
B
R
38
AT49LD3200(B)
1940B–FLASH–11/01
Atmel Headquarters
Atmel Operations
Corporate Headquarters
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TEL 1(408) 441-0311
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FAX 1(408) 436-4314
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Europe
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e-mail
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Web Site
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL® is the registered trademark of Atmel. SFlash™ is a trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
1940B–FLASH–11/01
/xM
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