AT49F8011T-70CI [ATMEL]
8-megabit (512K x 16/ 1M x 8) 5-volt Only Flash Memory; 8兆位（ 512K ×16 / 1M ×8 ）， 5伏只有闪存
| 型号： | AT49F8011T-70CI |
| 厂家： | 
ATMEL |
| 描述： | 8-megabit (512K x 16/ 1M x 8) 5-volt Only Flash Memory |
| 文件： | 总20页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 4.5V to 5.5V Read/Write
• Access Time - 70 ns
• Sector Erase Architecture
– Fourteen 32K Word (64K Byte) Sectors with Individual Write Lockout
– Two 16K Word (32K Byte) Sectors with Individual Write Lockout
– Two 8K Word (16K Byte) Sectors with Individual Write Lockout
– Four 4K Word (8K Byte) Sectors with Individual Write Lockout
• Fast Word Program Time - 10 µs
• Fast Sector Erase Time - 200 ms
• Dual Plane Organization, Permitting Concurrent Read while Program/Erase
– Memory Plane A: Four 4K Word, Two 8K Word and Two 16K Word Sectors
– Memory Plane B: Fourteen 32K Word Sectors
• Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
• Low-power Operation
8-megabit
(512K x 16/
1M x 8)
5-volt Only
Flash Memory
– 40 mA Active
– 10 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• RESET Input for Device Initialization
• Sector Program Unlock Command
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
AT49F8011
AT49F8011T
Description
The AT49F8011(T) is a 5.0 volt 8-megabit Flash memory organized as 524,288 words
of 16 bits each or 1,048,576 bytes of 8 bits each. The x16 data appears on I/O0 -
I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 22 sectors for
erase operations. The device is offered in 48-pin TSOP and 48-ball CBGA packages.
The device has CE, and OE control signals to avoid any bus contention. This device
can be read or reprogrammed using a single 5.0V power supply, making it ideally
suited for in-system programming.
Not Recommended
for New Designs
Pin Configurations
Pin Name
A0 - A18
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
OE
WE
RESET
RDY/BUSY
I/O0 - I/O14
I/O15 (A-1)
READY/BUSY Output
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
NC
Selects Byte or Word Mode
No Connect
DC
Don’t Connect
1264D–FLASH–5/03
TSOP Top View
Type 1
CBGA Top View
1
2
3
4
5
6
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
BYTE
GND
I/O15/A-1
I/O7
A
B
C
D
E
F
3
A3
A4
A7 RDY/BUSY WE
A9
A13
A12
A14
A15
A16
4
5
6
I/O14
I/O6
A17
A6
NC RESET A8
7
A8
8
I/O13
I/O5
A2
A18
NC
NC
NC
A10
A11
I/O7
NC
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O12
I/O4
WE
A1
A5
RESET
NC
VCC
I/O11
I/O3
NC
A0
I/O0
I/O8
I/O9
I/O1
I/O2
I/O5
RDY/BUSY
A18
A17
A7
I/O10
I/O2
CE
OE
VSS
I/O10 I/O12 I/O14 BYTE
I/O9
I/O1
G
H
A6
I/O8
I/O11 VCC I/O13 I/O15
/A-1
A5
I/O0
A4
OE
I/O3
I/O4
I/O6
VSS
A3
GND
CE
A2
A1
A0
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector. Once the data protection for a given sector is enabled, the data in that
sector cannot be changed using input levels between ground and VCC
.
The device is segmented into two memory planes. Reads from memory plane B may be per-
formed even while program or erase functions are being executed in memory plane A and vice
versa. This operation allows improved system performance by not requiring the system to wait
for a program or erase operation to complete before a read is performed. To further increase
the flexibility of the device, it contains an Erase Suspend feature. This feature will put the
Erase on hold for any amount of time and let the user read data from or program data to any of
the remaining sectors within the same memory plane. There is no reason to suspend the
erase operation if the data to be read is in the other memory plane. The end of a program or
an Erase cycle is detected by the Ready/Busy pin, Data polling, or by the toggle bit.
A six byte command (bypass unlock) sequence to remove the requirement of entering the
three byte program sequence is offered to further improve programming time. After entering
the six byte code, only single pulses on the write control lines are required for writing into the
device. This mode (single pulse byte/word program) is exited by powering down the device, or
by pulsing the RESET pin low for a minimum of 50ns and then bringing it back to VCC. Erase
and Erase Suspend/Resume commands will not work while in this mode; if entered they will
result in data being programmed into the device. It is not recommended that the six byte code
reside in the software of the final product but only exist in external programming code.
The BYTE pin controls whether the device data I/O pins operate in the byte or word configura-
tion. If the BYTE pin is set at logic “1”, the device is in word configuration, I/O0-I/O15 are
active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins
I/O0-I/O7 are active and controlled by CE and OE. The data I/O pins I/O8-I/O14 are tri-stated,
and the I/O15 pin is used as an input for the LSB (A-1) address function.
2
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
Block Diagram
I/O0 - I/O15/A-1
OUTPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
INPUT
A0 - A18
BUFFER
STATUS
CE
REGISTER
WE
COMMAND
REGISTER
OE
RESET
BYTE
ADDRESS
LATCH
DATA
RDY/BUSY
COMPARATOR
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
Y-DECODER
X-DECODER
Y-GATING
VCC
GND
PLANE B
SECTORS
PLANE A SECTORS
Device
Operation
READ: The AT49F8011(T) is accessed like an EPROM. When CE and OE are low and WE is
high, the data stored at the memory location determined by the address pins are asserted on
the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or
standby mode depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table (I/O8 - I/O15 are don't care inputs for
the command codes). The command sequences are written by applying a low pulse on the
WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Standard microprocessor write timings are used. The address locations used in the
command sequences are not affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. When a high level is reasserted on the RESET pin, the device returns to the Read or
Standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin any sector can be reprogrammed even if the sector lockout feature
has been enabled (see Sector Programming Lockout Override section).
3
1264D–FLASH–5/03
ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-
mand or individual sectors can be erased by using the Sector Erase commands.
CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is tEC
.
If the sector lockout has been enabled, the Chip Erase will not erase the data in the sector that
has been locked; it will erase only the unprotected sectors. After the chip erase, the device will
return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 22 sec-
tors that can be individually erased. The Sector Erase command is a six bus cycle operation.
The sector address is latched on the falling WE edge of the sixth cycle while the 30H data
input command is latched on the rising edge of WE. The sector erase starts after the rising
edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically
time to completion. The maximum time to erase a section is tSEC. When the sector program-
ming lockout feature is not enabled, the sector will erase (from the same sector erase
command). Once a sector has been protected, data in the protected sectors cannot be
changed unless the RESET pin is taken to 12V ± 0.5V. An attempt to erase a sector that has
been protected will result in the operation terminating in 2 µs.
BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi-
cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the
internal device command register and is a 4-bus cycle operation. The device will automatically
generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle
time. The DATA polling feature or the toggle bit feature may be used to indicate the end of a
program cycle.
SECTOR PROGRAMMING LOCKOUT: Each sector has a programming lockout feature. This
feature prevents programming of data in the designated sectors once the feature has been
enabled. These sectors can contain secure code that is used to bring up the system. Enabling
the lockout feature will allow the boot code to stay in the device while data in the rest of the
device is updated. This feature does not have to be activated; any sector’s usage as a write
protected region is optional to the user.
Once the feature is enabled, the data in the protected sectors can no longer be erased or pro-
grammed when input levels of 5.5V or less are used. Data in the remaining sectors can still be
changed through the regular programming method. To activate the lockout feature, a series of
six program commands to specific addresses with specific data must be performed. Please
refer to the Command Definitions table.
SECTOR LOCKOUT DETECTION: A software method is available to determine if program-
ming of a sector is locked out. When the device is in the software product identification mode
(see Software product Identification Entry and Exit sections) a read from address location
00002H within a sector will show if programming the sector is locked out. If the data on I/O0 is
low, the sector can be programmed; if the data on I/O0 is high, the program lockout feature
has been enabled and the sector cannot be programmed. The software product identification
exit code should be used to return to standard operation.
SECTOR PROGRAMMING LOCKOUT OVERRIDE: The user can override the sector pro-
gramming lockout by taking the RESET pin to 12V ± 0.5V. By doing this protected data can be
altered through a chip erase, sector erase or byte/word programming. When the RESET pin is
brought back to TTL levels the sector programming lockout feature is again active.
4
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
ERASE SUSPEND/ERASE RESUME: The erase suspend command allows the system to
interrupt a sector erase operation and then program or read data from a different sector within
the same plane. Since this device has a dual plane architecture, there is no need to use the
erase suspend feature while erasing a sector when you want to read data from a sector in the
other plane. After the erase suspend command is given, the device requires a maximum time
of 15 µs to suspend the erase operation. After the erase operation has been suspended, the
plane which contains the suspended sector enters the erase-suspend-read mode. The system
can then read data or program data to any other sector within the device. An address is not
required during the erase suspend command. During a sector erase suspend, another sector
cannot be erased. To resume the sector erase operation, the system must write the erase
resume command. The erase resume command is a one bus cycle command that does
require the plane address which is determined by A18 - A16. The device also supports an
erase suspend during a complete chip erase. While the chip erase is suspended, the user can
read from any sector within the memory that is protected. The command sequence for a chip
erase suspend and a sector erase suspend are the same.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-
ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
DATA POLLING: The AT49F8011(T) features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the last byte/word loaded will result in the
complement of the loaded data on I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin. During a chip or sector erase opera-
tion, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has
completed, true data will be read from the device. DATA polling may begin at any time during
the program cycle. Please see “Status Bit Table” for more details.
TOGGLE BIT: In addition to DATA polling the AT49F8011(T) provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2 which can be used in conjunction with the toggle
bit which is available on I/O6. While a sector is erase suspended, a read or a
program operation from the suspended sector will result in the I/O2 bit toggling. Please see
“Status Bit Table” for more details.
RDY/BUSY: An open drain READY/BUSY output pin provides another method of detecting
the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal
program and erase cycles and is released at the completion of the cycle. The open drain con-
nection allows for OR-tying of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs
to the AT49F8011(T) in the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the
program function is inhibited. (b) VCC power on delay: once VCC has reached the VCC sense
level, the device will automatically time out 10 ms (typical) before programming. (c) Program
inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 4.5V to 5.5V power supply, the address inputs and
control inputs (OE, CE, and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
5
1264D–FLASH–5/03
Command Definition in Hex(1)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles Addr Data
Addr
Data Addr Data Addr Data
Addr
Data
Addr
Data
Read
1
6
6
4
6
1
Addr DOUT
Chip Erase
5555
5555
5555
5555
Addr
AA
AA
AA
AA
DIN
2AAA
2AAA
2AAA
2AAA
55
55
55
55
5555
5555
5555
5555
80
80
A0
80
5555
5555
Addr
5555
AA
AA
DIN
AA
2AAA
2AAA
55
55
5555
10
30
Sector Erase
Byte/Word Program
Bypass Unlock
SA(3)(4)
2AAA
2AAA
55
55
5555
A0
40
Single Pulse
Byte/Word Program
Sector Lockout
Erase Suspend
Erase Resume
Product ID Entry
Product ID Exit(2)
Product ID Exit(2)
6
1
1
3
3
1
5555
xxxx
PA(5)
5555
5555
xxxx
AA
B0
30
2AAA
55
5555
80
5555
AA
SA(3)(4)
AA
AA
F0
2AAA
2AAA
55
55
5555
5555
90
F0
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, A14 - A18 (Don’t Care).
2. Either one of the Product ID Exit commands can be used.
3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next two
pages for details).
4. When the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command).
Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET pin is taken to
12V ± 0.5V.
5. PA is the plane address (A18 - A16).
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias............................... -55°C to +125°C
Storage Temperature.................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
6
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
AT49F8011 – Sector Address Table
x8
x16
Plane
A
Sector
SA0
Size (Bytes/Words)
16K/8K
Address Range (A18 - A-1)
Address Range (A18 - A0)
000000 - 003FFF
004000 - 00BFFF
00C000 - 00DFFF
00E000 - 00FFFF
010000 - 011FFF
012000 - 013FFF
014000 - 018FFF
01C000 - 01FFFF
020000 - 02FFFF
030000 - 03FFFF
040000 - 04FFFF
050000 - 05FFFF
060000 - 06FFFF
070000 - 07FFFF
080000 - 08FFFF
090000 - 09FFFF
0A0000 - 0AFFFF
0B0000 - 0BFFFF
0C0000 - 0CFFFF
0D0000 - 0DFFFF
0E0000 - 0EFFFF
0F0000 - 0FFFFF
00000 - 01FFF
02000 - 05FFF
06000 - 06FFF
07000 - 07FFF
08000 - 08FFF
09000 - 09FFF
0A000 - 0DFFF
0E000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
A
SA1
32K/16K
8K/4K
A
SA2
A
SA3
8K/4K
A
SA4
8K/4K
A
SA5
8K/4K
A
SA6
32K/16K
16K/8K
A
SA7
B
SA8
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
B
SA9
B
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
B
B
B
B
B
B
B
B
B
B
B
7
1264D–FLASH–5/03
AT49F8011T – Sector Address Table
x8
x16
Plane
B
Sector
SA0
Size (Bytes/Words)
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
16K/8K
Address Range (A18 - A-1)
Address Range (A18 - A0)
000000 - 00FFFF
010000 - 01FFFF
020000 - 02FFFF
030000 - 03FFFF
040000 - 04FFFF
050000 - 05FFFF
060000 - 06FFFF
070000 - 07FFFF
080000 - 08FFFF
090000 - 09FFFF
0A0000 - 0AFFFF
0B0000 - 0BFFFF
0C0000 - 0CFFFF
0D0000 - 0DFFFF
0E0000 - 0E3FFF
0E4000 - 0EBFFF
0EC000 - 0EDFFF
0EE000 - 0EFFFF
0F0000 - 0F1FFF
0F2000 - 0F3FFF
0F4000 - 0FBFFF
0FC000 - 0FFFFF
00000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 71FFF
72000 - 75FFF
76000 - 76FFF
77000 - 77FFF
78000 - 78FFF
79000 - 79FFF
7A000 - 7DFFF
7E000 - 7FFFF
B
SA1
B
SA2
B
SA3
B
SA4
B
SA5
B
SA6
B
SA7
B
SA8
B
SA9
B
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
B
B
B
A
A
32K/16K
8K/4K
A
A
8K/4K
A
8K/4K
A
8K/4K
A
32K/16K
16K/8K
A
8
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
DC and AC Operating Range
AT49F8011(T)-70
0°C - 70°C
AT49F8011(T)-90
0°C - 70°C
Com.
Operating
Temperature (Case)
Ind.
-40° C - 85° C
4.5V to 5.5V
-40° C - 85° C
4.5V to 5.5V
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
RESET
VIH
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program/Erase(2)
Standby/Program Inhibit
Program Inhibit
Program Inhibit
Output Disable
Reset
VIH
VIH
High Z
VIH
X
VIH
X
VIL
VIH
X
VIH
X
X
VIH
High Z
High Z
X
X
VIL
X
Product Identification
(3)
(3)
A1 - A18 = VIL, A9 = VH
A0 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
A1 - A18 = VIL, A9 = VH
A0 = VIH
A0 = VIL, A1 - A18 = VIL
A0 = VIH, A1 - A18 = VIL
Manufacturer Code(4)
Device Code(4)
Software(5)
VIH
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: 00CB-AT49F8011; 004A-AT49F8011T.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
10
10
1
Units
µA
µA
µA
mA
mA
mA
V
ILI
Input Load Current
VIN = 0V to VCC
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
VI/O = 0V to VCC
ISB1
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
f = 5 MHz; IOUT = 0 mA
ISB2
(1)
ICC
40
60
0.8
ICCRW
VIL
VCC Read While Write Current
Input Low Voltage
VIH
Input High Voltage
2.0
2.4
V
VOL
VOH
Output Low Voltage
IOL = 2.1 mA
0.45
V
Output High Voltage
IOH = -400 µA
V
Note:
1. In the erase mode, ICC is 50 mA.
9
1264D–FLASH–5/03
AC Read Characteristics
AT49F8011(T)-70
AT49F8011(T)-90
Symbol
Parameter
Min
Max
70
Min
Max
90
Units
ns
tACC
Address to Output Delay
CE to Output Delay
(1)
tCE
70
90
ns
(2)
tOE
OE to Output Delay
0
0
0
35
0
0
0
40
ns
(3)(4)
tDF
CE or OE to Output Float
Output Hold from OE, CE or Address, whichever occurred first
RESET to Output Delay
25
25
ns
tOH
tRO
ns
800
800
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
HIGH Z
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
10
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
Input Test Waveforms and Measurement Level
3.0
tR, tF < 5 ns
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
11
1264D–FLASH–5/03
AC Byte/Word Load Characteristics
Symbol
Parameter
Min
10
50
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
100
50
10
50
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
12
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte/Word Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
10
50
tAS
0
50
50
10
100
50
ns
tAH
ns
tDS
ns
tDH
Data Hold Time
ns
tWP
Write Pulse Width
ns
tWPH
tEC
Write Pulse Width High
Chip Erase Cycle Time
Sector Erase Cycle Time
ns
10
seconds
ms
tSEC
200
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
BP
t
WP
WPH
WE
t
t
t
AS
AH
DH
5555
5555
5555
2AAA
ADDRESS
A0 -A18
DATA
t
DS
INPUT
DATA
55
A0
AA
AA
Sector or Chip Erase Cycle Waveforms
(1)
OE
(4)
(4)
CE
t
t
WP
WPH
WE
A0-A18
DATA
t
t
t
DH
AS
AH
5555
5555
5555
Note 2
2AAA
2AAA
t
t
EC
DS
55
WORD 1
80
WORD 2
55
WORD 4
Note 3
WORD 5
AA
WORD 0
AA
WORD 3
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See
note 3 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
4. The tWPH time between the 5th and 6th bus cycle should be a minimum of 150 ns.
13
1264D–FLASH–5/03
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
A0-A18
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
14
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
Software Product Identification Entry(1)
Sector Lockout Enable Algorithm(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 80
TO
LOAD DATA 90
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA AA
TO
ENTER PRODUCT
IDENTIFICATION
ADDRESS 5555
(2)(3)(5)
MODE
LOAD DATA 55
TO
Software Product Identification Exit(1)(6)
ADDRESS 2AAA
OR
LOAD DATA AA
LOAD DATA F0
TO
TO
ADDRESS 5555
ANY ADDRESS
LOAD DATA 40
TO
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA 55
TO
ADDRESS 5555
ADDRESS 2AAA
PAUSE 200 µs(2)
LOAD DATA F0
TO
ADDRESS 5555
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex) Address Format: A15 - A0 (Hex), A-1, and
A15 - A18 (Don’t Care).
EXIT PRODUCT
IDENTIFICATION
MODE(4)
2. Sector lockout feature enabled.
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex) Address Format: A15 - A0 (Hex), A-1, and
A15 - A18 (Don’t Care).
2. A1 - A18 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH (x8); 001FH (x16)
6. Device Code:00CBH - AT49BV8011;
004AH - AT49BV8011T.
7. Either one of the Product ID Exit commands can be
used.
15
1264D–FLASH–5/03
Status Bit Table
Status Bit
I/O 6
I/O 7
I/O 2
Read Address In
While
Plane A
Plane B
Plane A
Plane B
Plane A
Plane B
Programming in Plane A
Programming in Plane B
I/O7
DATA
I/O7
TOGGLE
DATA
DATA
1
DATA
1
DATA
TOGGLE
DATA
Erasing in Plane A
Erasing in Plane B
0
DATA
0
TOGGLE
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
TOGGLE
Erase Suspended & Read
Erasing Sector
1
1
1
1
TOGGLE
DATA
TOGGLE
DATA
Erase Suspended & Read
Non-Erasing Sector
DATA
DATA
DATA
DATA
Erase Suspended &
Program Erasing Sector
1
1
1
1
TOGGLE
TOGGLE
TOGGLE
DATA
Erase Suspended &
Program Non-Erasing
Sector in Plane A
I/O7
DATA
TOGGLE
DATA
Erase Suspended &
Program Non-Erasing
Sector in Plane B
DATA
I/O7
DATA
TOGGLE
DATA
TOGGLE
16
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
AT49F8011(T) Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
90
70
90
40
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
AT49F8011-70CC
AT49F8011-70TC
48C3
48T
Commercial
(0°C to 70°C)
40
40
40
40
40
40
40
AT49F8011-70CI
AT49F8011-70TI
48C3
48T
Industrial
(-40°C to 85°C)
AT49F8011-90CC
AT49F8011-90TC
48C3
48T
Commercial
(0°C to 70°C)
AT49F8011-90CI
AT49F8011-90TI
48C3
48T
Industrial
(-40°C to 85°C)
AT49F8011T-70CC
AT49F8011T-70TC
48C3
48T
Commercial
(0°C to 70°C)
AT49F8011T-70CI
AT49F8011T-70TI
48C3
48T
Industrial
(-40°C to 85°C)
AT49F8011T-90CC
AT49F8011T-90TC
48C3
48T
Commercial
(0°C to 70°C)
AT49F8011T-90CI
AT49F8011T-90TI
48C3
48T
Industrial
(-40°C to 85°C)
Package Type
48C3
48T
48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA)
48-lead, Thin Small Outline Package (TSOP)
17
1264D–FLASH–5/03
Packaging Information
48C3 – CBGA
48C3, 48-ball (6 x 8 Array), 0.80 mm Pitch, 8 x 8 x 1.2 mm
Chip-scale Ball Grid Array Package (CBGA)
Dimensions in Millimeters and (Inches)*
8.10 (0.319)
7.90 (0.311)
A1 ID
8.10 (0.319)
7.90 (0.311)
0.30 (0.012)MIN
4.00(0.157)
2.00(0.079)REF
1.20 (0.047) MAX
6
5
4
3
2
1
A
B
C
0.80(0.0315) BSC
NON-ACCUMULATIVE
D
E
F
5.60(0.220)
G
H
1.20(0.047) REF
0.45 (0.018) DIA BALL TYP
0.80(0.0315) BSC
NON-ACCUMULATIVE
*Controlling dimension: millimeters
REV. A 04/11/2001
18
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
48T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
20.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
19.80
18.30
11.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation DD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
20.00
18.40
12.00
0.60
D1
E
18.50 Note 2
12.10 Note 2
0.70
L
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
48T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
R
19
1264D–FLASH–5/03
Atmel Corporation
Atmel Operations
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Tel: 1(408) 441-0311
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Web Site
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Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
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others.
Printed on recycled paper.
1264D–FLASH–5/03
xM
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