AT49F2048A [ATMEL]
2-megabit 256K x 8/ 128K x 16 5-volt Only CMOS Flash Memory; 2兆位256K ×8 / 128K ×16的5伏只有CMOS闪存
| 型号： | AT49F2048A |
| 厂家： | 
ATMEL |
| 描述： | 2-megabit 256K x 8/ 128K x 16 5-volt Only CMOS Flash Memory |
| 文件： | 总13页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single-voltage Operation
– 5V Read
– 5V Reprogramming
• Fast Read Access Time – 70 ns
• Internal Erase/Program Control
• Sector Architecture
– One 8K Word (16K Bytes) Boot Block with Programming Lockout
– Two 4K Word (8K Bytes) Parameter Blocks
– One 112K Word (224K bytes) Main Memory Array Block
• Fast Sector Erase Time – 10 seconds
• Byte-by-byte or Word-by-word Programming – 50 µs
• Hardware Data Protection
• Data Polling for End of Program Detection
• Low Power Dissipation
– 50 mA Active Current
– 100 µA CMOS Standby Current
• Typical 10,000 Write Cycles
2-megabit
(256K x 8/
128K x 16)
5-volt Only
CMOS Flash
Memory
Description
The AT49F2048A is a 5-volt-only, 2-megabit Flash memory organized as 262,144
words of 8 bits each or 128K words of 16 bits each. Manufactured with Atmel’s
(continued)
Pin Configurations
AT49F2048A
Pin Name
A0 - A16
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
OE
WE
RESET
I/O0 - I/O14 Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
TSOP Top View
I/O15 (A-1)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
Type 1
BYTE
NC
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
BYTE
GND
I/O15/A-1
I/O7
3
SOIC (SOP)
4
5
6
I/O14
I/O6
NC
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
7
2
A8
8
I/O13
I/O5
NC
3
A8
NC
9
A7
4
A9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O12
I/O4
A6
5
A10
WE
RESET
NC
A5
6
A11
VCC
I/O11
I/O3
A4
7
A12
NC
A3
8
A13
NC
I/O10
I/O2
A2
9
A14
NC
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
NC
I/O9
A0
A16
A7
I/O1
CE
BYTE
GND
I/O15/A-1
I/O7
A6
I/O8
GND
OE
A5
I/O0
A4
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
A3
GND
CE
I/O14
I/O6
A2
A1
A0
I/O13
I/O5
Rev. 1159F–04/01
I/O12
I/O4
Note:
“•” denotes a white dot marked on
the package.
VCC
advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just
275 mW. When deselected, the CMOS standby current is
less than 100 µA.
typical number of program and erase cycles is in excess of
10,000 cycles.
The optional 8K word boot block section includes a repro-
gramming lockout feature to provide data integrity. This
feature is enabled by a command sequence. Once the boot
block programming lockout feature is enabled, the data in
the boot block cannot be changed when input levels of 5.5
volts or less are used. The boot sector is designed to con-
tain user secure code.
To allow for simple in-system reprogrammability, the
AT49F2048A does not require high input voltages for pro-
gramming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM; it
has standard CE, OE and WE inputs to avoid bus connec-
tion. Reprogramming the AT49F2048A is performed by first
erasing a block of data and then programming on a byte-
by-byte or word-by-word basis.
The BYTE pin controls whether the device data I/O pins
operate in the byte or word configuration. If the BYTE pin is
set at a logic “1” or left open, the device is in word configu-
ration; I/O0 - I/O15 are active and controlled by CE and OE.
The device is erased by executing the Erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into four blocks for erase oper-
ations. There are two 4K word parameter block sections:
the boot block and the main memory array block. The
If the BYTE pin is set at logic “0”, the device is in byte con-
figuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the
LSB (A-1) address function.
Block Diagram
112
04000
03FFF
4
4
03000
02FFF
Device Operation
READ: The AT49F2048A is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high-
impedance state whenever CE or OE is high. This dual
line control gives designers flexibility in preventing bus
contention.
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
COMMAND SEQUENCES: When the device is first pow-
ered on, it will be reset to the read or standby mode,
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command codes).
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
2
AT49F2048A
AT49F2048A
returns to the read or standby mode, depending upon the
state of the control inputs. By applying a 12V 0.5V input
signal to the RESET pin, the boot block array can be repro-
grammed even if the boot block program lockout feature
has been enabled (see Boot Block Programming Lockout
Override section).
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The Data Polling feature may
also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write-protected region is
optional to the user. The address range of the boot block is
00000H to 01FFFH.
ERASURE: Before a byte or word can be reprogrammed, it
must be erased. The erased state of the memory bits is a
logic “1”. The entire device can be erased at one time by
using a 6-byte software code.
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC.
CHIP ERASE: The entire device can be erased at one time
by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
The maximum time to erase the chip is tEC
.
If the boot block lockout has been enabled, the chip erase
will not erase the data in the boot block; it will erase the
main memory block and the parameter blocks only. After
the chip erase, the device will return to the read or standby
mode.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been enabled and the block cannot be pro-
grammed. The software product identification exit code
should be used to return to standard operation.
SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into four sectors that can be individually
erased. There are two 4K word parameter block sections:
one boot block, and the main memory array block. The
Sector Erase command is a six-bus cycle operation. The
sector address is latched on the falling WE edge of the
sixth cycle while the 30H data input command is latched at
the rising edge of WE. The sector erase starts after the ris-
ing edge of WE of the sixth cycle. The erase operation is
internally controlled; it will automatically time to completion.
Whenever the main memory block is erased and repro-
grammed, the two parameter blocks should be erased and
reprogrammed before the main memory block is erased
again. Whenever a parameter block is erased and repro-
grammed, the other parameter block should be erased and
reprogrammed before the first parameter block is erased
again. Whenever the boot block is erased and repro-
grammed, the main memory block and the parameter
blocks should be erased and reprogrammed before the
boot block is erased again.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout
by taking the RESET pin to 12 volts during the entire chip
erase, sector erase or word programming operation. When
the RESET pin is brought back to TTL levels, the boot
block programming lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
BYTE/WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logic “0”) on a byte-by-byte
or word-by-word basis. Programming is accomplished via
the internal device command register and is a four-bus
cycle operation. The device will automatically generate the
required internal program pulses.
For details, see “Operating Modes” on page 5 (for hard-
ware operation) or “Software Product Identification
Entry/Exit” on page 10. The manufacturer and device
codes are the same for both modes.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset hap-
pens during programming, the data at the location being
DATA POLLING: The AT49F2048A features Data Polling
to indicate the end of a program cycle. During a program
3
cycle, an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the
program cycle has been completed, true data is valid on all
outputs and the next cycle may begin. During a chip or sec-
tor erase operation, an attempt to read the device will give
a “0” on I/O7. Once the program or erase cycle has com-
pleted, true data will be read from the device. Data Polling
may begin at any time during the program cycle.
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F2048A in
the following ways: (a) VCC sense: if VCC is below 3.8V (typ-
ical), the program function is inhibited. (b) VCC power-on
delay: once VCC has reached the VCC sense level, the
device will automatically time-out 10 ms (typical) before
programming. (c) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Noise
filter: pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
TOGGLE BIT: In addition to Data Polling, the AT49F2048A
provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
Command Definition (in Hex)(1)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
6
4
6
Addr
5555
5555
5555
5555
Chip Erase
Sector Erase
Word Program
2AAA
2AAA
2AAA
2AAA
55
55
55
55
5555
5555
5555
5555
80
80
A0
80
5555
5555
Addr
5555
AA
AA
DIN
AA
2AAA
2AAA
55
55
5555
SA(4)
10
30
AA
AA
Boot Block
Lockout(2)
AA
2AAA
55
5555
40
Product ID Entry
Product ID Exit(3)
Product ID Exit(3)
3
3
1
5555
5555
xxxx
AA
AA
F0
2AAA
2AAA
55
55
5555
5555
90
F0
Notes:
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex).
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1 and A15 - A16 (Don’t Care).
2. The 8K word boot sector has the address range 00000H to 01FFFH.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses: (A16-A0)
SA = 01XXX for BOOT BLOCK
SA = 02XXX for PARAMETER BLOCK 1
SA = 03XXX for PARAMETER BLOCK 2
SA = 1FXXX for MAIN MEMORY ARRAY
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
4
AT49F2048A
1159F–04/01
AT49F2048A
DC and AC Operating Range
AT49F2048A-70
0°C - 70°C
AT49F2048A-90
0°C - 70°C
Com.
Ind.
Operating
Temperature (Case)
-40°C - 85°C
5Vꢀ 10%
-40°C - 85°C
5Vꢀ 10%
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X (1)
X
WE
VIH
VIL
X
RESET
VIH
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program/Erase(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Reset
VIH
VIH
High-Z
VIH
X
VIH
X
VIL
VIH
X
VIH
X
X
VIH
High-Z
High-Z
X
X
VIL
X
Product Identification
A1 - A16 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
A1 - A16 = VIL, A9 = VH,(3)
A0 = VIH
A0 = VIL, A1 - A16 = VIL
A0 = VIH, A1 - A16 = VIL
Manufacturer Code(4)
Device Code(4)
Software(5)
VIH
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 001FH, Device Code: 0082H
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol Parameter
Condition
Min
Max
10.0
10.0
100.0
3.0
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
VIN = 0V to VCC
ILO
ISB1
ISB2
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
VI/O = 0V to VCC
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
(1)
ICC
VIL
50.0
0.8
Input Low Voltage
VIH
Input High Voltage
2.0
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.45
V
VOH1
VOH2
Note:
Output High Voltage
IOH = -400 µA
2.4
4.2
V
Output High Voltage CMOS
1. In the erase mode, ICC is 90 mA.
IOH = -100 µA; VCC = 4.5V
V
5
1159F–04/01
AC Read Characteristics
AT49F2048A-70
AT49F2048A-90
Symbol
Parameter
Min
Max
70
Min
Max
90
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
70
90
ns
(2)
tOE
30
0
0
0
30
ns
(3)(4)
tDF
0
0
25
25
ns
tOH
Output Hold from OE, CE or Address, whichever
occurred first
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
CE
ADDRESS VALID
tCE
tOE
OE
tDF
tOH
tACC
HIGHZ
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
30
Pin Capacitance
(f = 1 MHz, T = 25°C)(1)
Typ
4
Max
6
Units
pF
Conditions
CIN
COUT
Note:
VIN = 0V
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
6
AT49F2048A
AT49F2048A
AC Word Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Setup Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
50
0
ns
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Setup Time
ns
0
ns
50
50
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
40
ns
AC Byte/Word Load Waveforms
WE Controlled
OE
t
OES
t
t
OEH
ADDRESS
t
t
AH
AS
CH
CE
t
CS
WE
t
t
WPH
WP
t
t
DH
DS
DATA IN
CE Controlled
OE
t
OES
t
t
OEH
ADDRESS
t
t
AH
AS
CH
WE
t
CS
CE
t
t
WPH
WP
t
t
DH
DS
DATA IN
7
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
µs
tBP
Byte/Word Programming Time
Address Setup Time
Address Hold Time
Data Setup Time
50
tAS
0
ns
tAH
50
50
0
ns
tDS
ns
tDH
Data Hold Time
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
50
40
ns
tWPH
tEC
ns
5
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
t
t
t
BP
WP
WPH
WE
t
t
AS
AH
DH
A0-A16
DATA
5555
2AAA
5555
ADDRESS
5555
DS
INPUT
DATA
AA
55
A0
AA
Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
t
t
t
WP
WPH
WE
A0-A16
DATA
t
t
AS
AH
DH
5555
2AAA
5555
5555
2AAA
Note 2
t
t
EC
DS
AA
55
80
AA
55
Note 3
BYTE/
BYTE/
BYTE/
BYTE/
BYTE/
BYTE/
WORD 0
WORD 1
WORD 2
WORD 3
WORD 4
WORD 5
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See
note 4 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
8
AT49F2048A
AT49F2048A
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 6.
Data Polling Waveforms
WE
CE
t
OEH
OE
t
t
t
WR
DH
OE
HIGH Z
I/O7
A0-A16
An
An
An
An
An
Toggle Bit Characteristics(1)
Symbol Parameter
Min
Typ
Max
Units
ns
tDH
Data Hold Time
10
10
tOEH
tOE
tOEHP
tWR
OE Hold Time
ns
OE to Output Delay(2)
ns
OE High Pulse
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 6.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
t
t
OEH
OEHP
t
OE
t
t
WR
DH
OE
HIGH Z
I/O6
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
1159F–04/01
Software Product Identification Entry(1)
Boot Block Lockout
Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
(2)(3)(5)
MODE
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product Identification Exit(1)(6)
LOAD DATA 40
TO
ADDRESS 5555
OR
LOAD DATA AA
TO
LOAD DATA F0
TO
ADDRESS 5555
ANY ADDRESS
PAUSE 1 second
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care);
I/O7 - I/O0 (Hex)
Address Format: A15 - A0 (Hex); A-1 and A15 - A16
(Don’t Care).
LOAD DATA F0
TO
ADDRESS 5555
2. Boot Block Lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care);
I/O7 - I/O0 (Hex)
Address Format: A15 - A0 (Hex);
A-1 and A15 - A16 (Don’t Care).
2. A1 - A16 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH
Device Code: 0082H
6. Either one of the Product ID Exit commands can be
used.
10
AT49F2048A
AT49F2048A
Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
50
0.3
0.3
0.3
0.3
AT49F2048A-70RC
AT49F2048A-70TC
44R
48T
Commercial
(0° to 70°C)
50
50
50
AT49F2048A-70RI
AT49F2048A-70TI
44R
48T
Industrial
(-40° to 85°C)
90
AT49F2048A-90RC
AT49F2048A-90TC
44R
48T
Commercial
(0° to 70°C)
AT49F2048A-90RI
AT49F2048A-90TI
44R
48T
Industrial
(-40° to 85°C)
Package Type
44R
44-lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
48-lead, Thin Small Outline Package (TSOP)
48T
11
1159F–04/01
Packaging Information
44R, 44-lead, 0.525" Wide,
48T, 48-lead, Plastic Thin Small Outline Package
Plastic Gull Wing Small Outline (SOIC)
(TSOP)
Dimensions in Inches and (Millimeters)
Dimensions in Millimeters and (Inches) *
JEDEC OUTLINE MO-142 DD
*Controlling dimension: millimeters
12
AT49F2048A
1159F–04/01
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Europe
Atmel Rousset
Atmel SarL
Zone Industrielle
13106 Rousset Cedex
France
Route des Arsenaux 41
Casa Postale 80
CH-1705 Fribourg
Switzerland
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Atmel Smart Card ICs
Scottish Enterprise Technology Park
East Kilbride, Scotland G75 0QR
TEL (44) 1355-357-000
Asia
Atmel Asia, Ltd.
Room 1219
FAX (44) 1355-242-743
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Atmel Grenoble
Avenue de Rochepleine
BP 123
Hong Kong
38521 Saint-Egreve Cedex
France
TEL (33) 4-7658-3000
FAX (33) 4-7658-3480
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
e-mail
literature@atmel.com
1-(800) 292-8635
Web Site
http://www.atmel.com
International:
1-(408) 441-0732
BBS
1-(408) 436-4309
© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL®, Cache Logic®, AVR Studio® are the registered trademarks of Atmel Corporation; FPSLIC, FreeRAM
and HDLPlanner are the trademarks of Atmel Corporation.
Other terms and product names may be the trademark of others.
Printed on recycled paper.
1159F–04/01/xM
相关型号：
©2020 ICPDF网 联系我们和版权申明