AT49BV8011T-12TI_技术文档

Features

• Single Supply for Read and Write: 2.7V to 3.3V (BV), 3.0V to 3.3V (LV)

• Access Time – 90 ns

• Sector Erase Architecture

Fourteen 32K Word (64K Byte) Sectors with Individual Write Lockout

Two 16K Word (32K Byte) Sectors with Individual Write Lockout

Two 8K Word (16K Byte) Sectors with Individual Write Lockout

Four 4K Word (8K Byte) Sectors with Individual Write Lockout

• Fast Word Program Time – 20 µs

• Fast Sector Erase Time – 200 ms

• Dual Plane Organization, Permitting Concurrent Read while Program/Erase

Memory Plane A: Four 4K Word, Two 8K Word and Two 16K Word Sectors

Memory Plane B: Fourteen 32K Word Sectors

• Erase Suspend Capability

– Supports Reading/Programming Data from Any Sector by Suspending Erase of

Any Different Sector

• Low-power Operation

8-megabit

(512K x 16/1M x 8)

3-volt Only

Flash Memory

– 25 mA Active

– 10 µA Standby

• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

• Optional VPP Pin for Fast Programming

• RESET Input for Device Initialization

• Sector Program Unlock Command

• TSOP and CBGA Package Options

AT49BV8011

AT49BV8011T

AT49LV8011

AT49LV8011T

• Top or Bottom Boot Block Configuration Available

Description

The AT49BV/LV8011(T) is a 2.7- to 3.3-volt 8-megabit Flash memory organized as

524,288 words of 16 bits each or 1,048,576 bytes of 8 bits each. The x16 data

appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided

into 22 sectors for erase operations. The device is offered in 48-pin TSOP and 48-ball

CBGA packages. The device has CE, and OE control signals to avoid any bus

(continued)

Pin Configurations

Pin Name

A0 - A18

CE

Function

Addresses

Chip Enable

Output Enable

Write Enable

Reset

OE

WE

RESET

RDY/BUSY

READY/BUSY Output

Optional Power Supply for Faster

Program/Erase Operations

VPP

I/O0 - I/O14

I/O15 (A-1)

Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

BYTE

NC

Selects Byte or Word Mode

No Connect

Rev. 1265E–01/00

VCCQ

Output Power Supply

1

TSOP Top View

CBGA Top View

Type 1

1

2

3

4

5

6

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

2

BYTE

GND

I/O15/A-1

I/O7

A

B

C

D

E

F

3

A3

A4

A7 RDY/BUSY WE

A9

A13

A12

A14

A15

A16

4

5

6

I/O14

I/O6

A17

A6

NC RESET A8

7

A8

8

I/O13

I/O5

A2

A18

NC

VPP

NC

A10

A11

I/O7

NC

9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I/O12

I/O4

WE

A1

A5

RESET

VPP

NC

VCC

I/O11

I/O3

A0

I/O0

I/O8

I/O9

I/O1

I/O2

I/O5

RDY/BUSY

A18

A17

A7

I/O10

I/O2

CE

OE

VSS

I/O10 I/O12 I/O14 BYTE

I/O9

I/O1

G

H

A6

I/O8

I/O11 VCC I/O13 I/O15

/A-1

A5

I/O0

A4

OE

I/O3

I/O4

I/O6

VSS

A3

GND

CE

A2

A1

A0

contention. This device can be read or reprogrammed

using a single 2.7V power supply, making it ideally suited

for in-system programming.

A VPP pin is provided to improve program/erase times.

This pin can be tied to V_CC. To take advantage of faster

programming and erasing, the pin should supply 4.5 to

5.5 volts during program and erase operations.

The device powers on in the read mode. Command

sequences are used to place the device in other operation

modes such as Program and Erase. The device has the

capability to protect the data in any sector. Once the data

protection for a given sector is enabled, the data in that

sector cannot be changed using input levels between

A 6-byte command (bypass unlock) sequence to remove

the requirement of entering the 3-byte program sequence

is offered to further improve programming time. After enter-

ing the 6-byte code, only single pulses on the write control

lines are required for writing into the device. This mode

(single-pulse byte/word program) is exited by powering

down the device, or by pulsing the RESET pin low for a

minimum of 50 ns and then bringing it back to V_CC. Erase

and Erase Suspend/Resume commands will not work while

in this mode; if entered they will result in data being pro-

grammed into the device. It is not recommended that the

6-byte code reside in the software of the final product but

only exist in external programming code.

ground and V_CC

.

The device is segmented into two memory planes. Reads

from memory plane B may be performed even while pro-

gram or erase functions are being executed in memory

plane A and vice versa. This operation allows improved

system performance by not requiring the system to wait for

a program or erase operation to complete before a read is

performed. To further increase the flexibility of the device, it

contains an Erase Suspend feature. This feature will put

the Erase on hold for any amount of time and let the user

read data from or program data to any of the remaining

sectors within the same memory plane. There is no reason

to suspend the erase operation if the data to be read is in

the other memory plane. The end of a program or an Erase

cycle is detected by the Ready/Busy pin, Data polling, or by

the toggle bit.

The BYTE pin controls whether the device data I/O pins

operate in the byte or word configuration. If the BYTE pin is

set at logic “1”, the device is in word configuration,

I/O0 - I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte con-

figuration, and only data I/O pins I/O0 - I/O7 are active and

controlled by CE and OE. The data I/O pins I/O8 - I/O14

are tri-stated, and the I/O15 pin is used as an input for the

LSB (A-1) address function.

AT49BV/LV8011(T)

2

AT49BV/LV8011(T)

Block Diagram

I/O0 - I/O15/A-1

OUTPUT

BUFFER

INPUT

BUFFER

IDENTIFIER

REGISTER

INPUT

A0 - A18

BUFFER

STATUS

CE

REGISTER

WE

COMMAND

OE

REGISTER

RESET

BYTE

ADDRESS

LATCH

DATA

RDY/BUSY

VPP

COMPARATOR

WRITE STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

Y-DECODER

X-DECODER

Y-GATING

VCC

GND

PLANE B

SECTORS

PLANE A SECTORS

Device Operation

READ: The AT49BV/LV8011(T) is accessed like an

EPROM. When CE and OE are low and WE is high, the

data stored at the memory location determined by the

address pins are asserted on the outputs. The outputs are

put in the high impedance state whenever CE or OE is

high. This dual line control gives designers flexibility in pre-

venting bus contention.

locations used in the command sequences are not affected

by entering the command sequences.

RESET: A RESET input pin is provided to ease some sys-

tem applications. When RESET is at a logic high level, the

device is in its standard operating mode. A low level on the

RESET input halts the present device operation and puts

the outputs of the device in a high impedance state. When

a high level is reasserted on the RESET pin, the device

returns to the read or standby mode, depending upon the

state of the control inputs. By applying a 12V 0.5V input

signal to the RESET pin, any sector can be reprogrammed

even if the sector lockout feature has been enabled (see

“Sector Programming Lockout Override” section).

COMMAND SEQUENCES: When the device is first pow-

ered on it will be reset to the read or standby mode,

depending upon the state of the control line inputs. In order

to perform other device functions, a series of command

sequences are entered into the device. The command

sequences are shown in the Command Definitions table

(I/O8 - I/O15 are don’t care inputs for the command codes).

The command sequences are written by applying a low

pulse on the WE or CE input with CE or WE low (respec-

tively) and OE high. The address is latched on the falling

edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Standard

microprocessor write timings are used. The address

ERASURE: Before a byte/word can be reprogrammed, it

must be erased. The erased state of memory bits is a logi-

cal “1”. The entire device can be erased by using the Chip

Erase command or individual sectors can be erased by

using the Sector Erase commands.

3

CHIP ERASE: The entire device can be erased at one time

by using the 6-byte chip erase software code. After the chip

erase has been initiated, the device will internally time the

erase operation so that no external clocks are required.

sectors can still be changed through the regular program-

ming method. To activate the lockout feature, a series of

six program commands to specific addresses with specific

data must be performed. Please refer to the Command

Definitions table.

The maximum time to erase the chip is t_EC

.

If the sector lockout has been enabled, the Chip Erase will

not erase the data in the sector that has been locked; it will

erase only the unprotected sectors. After the chip erase,

the device will return to the read or standby mode.

SECTOR LOCKOUT DETECTION: A software method is

available to determine if programming of a sector is locked

out. When the device is in the software product identifica-

tion mode (see “Software Product Identification Entry/Exit”

sections), a read from address location 00002H within a

sector will show if programming the sector is locked out. If

the data on I/O0 is low, the sector can be programmed; if

the data on I/O0 is high, the program lockout feature has

been enabled and the sector cannot be programmed. The

software product identification exit code should be used to

return to standard operation.

SECTOR ERASE: As an alternative to a full chip erase, the

device is organized into 22 sectors that can be individually

erased. The Sector Erase command is a six bus cycle

operation. The sector address is latched on the falling WE

edge of the sixth cycle while the 30H Data Input command

is latched on the rising edge of WE. The sector erase starts

after the rising edge of WE of the sixth cycle. The erase

operation is internally controlled; it will automatically time to

SECTOR PROGRAMMING LOCKOUT OVERRIDE: The

user can override the sector programming lockout by taking

the RESET pin to 12V 0.5V. By doing this, protected data

can be altered through a chip erase, sector erase or

byte/word programming. When the RESET pin is brought

back to TTL levels, the sector programming lockout feature

is again active.

completion. The maximum time to erase a section is t_SEC

.

When the sector programming lockout feature is not

enabled, the sector will erase (from the same Sector Erase

command). Once a sector has been protected, data in the

protected sectors cannot be changed unless the RESET

pin is taken to 12V 0.5V. An attempt to erase a sector

that has been protected will result in the operation terminat-

ing in 2 µs.

ERASE SUSPEND/ERASE RESUME: The Erase Sus-

pend command allows the system to interrupt a sector

erase operation and then program or read data from a dif-

ferent sector within the same plane. Since this device has a

dual plane architecture, there is no need to use the erase

suspend feature while erasing a sector when you want to

read data from a sector in the other plane. After the Erase

Suspend command is given, the device requires a maxi-

mum time of 15 µs to suspend the erase operation. After

the erase operation has been suspended, the plane that

contains the suspended sector enters the erase-suspend-

read mode. The system can then read data or program

data to any other sector within the device. An address is

not required during the Erase Suspend command. During a

sector erase suspend, another sector cannot be erased. To

resume the sector erase operation, the system must write

the Erase Resume command. The Erase Resume com-

mand is a one bus cycle command that does require the

plane address, which is determined by A18 - A16. The

device also supports an erase suspend during a complete

chip erase. While the chip erase is suspended, the user

can read from any sector within the memory that is pro-

tected. The command sequence for a chip erase suspend

and a sector erase suspend are the same.

BYTE/WORD PROGRAMMING: Once a memory block is

erased, it is programmed (to a logical “0”) on a byte-by-byte

or on a word-by-word basis. Programming is accomplished

via the internal device command register and is a four bus

cycle operation. The device will automatically generate the

required internal program pulses.

Any commands written to the chip during the embedded

programming cycle will be ignored. If a hardware reset hap-

pens during programming, the data at the location being

programmed will be corrupted. Please note that a data “0”

cannot be programmed back to a “1”; only erase operations

can convert “0”s to “1”s. Programming is completed after

the specified t_BPcycle time. The DATA polling feature or

the toggle bit feature may be used to indicate the end of a

program cycle.

SECTOR PROGRAMMING LOCKOUT: Each sector has a

programming lockout feature. This feature prevents pro-

gramming of data in the designated sectors once the

feature has been enabled. These sectors can contain

secure code that is used to bring up the system. Enabling

the lockout feature will allow the boot code to stay in the

device while data in the rest of the device is updated. This

feature does not have to be activated; any sector’s usage

as a write-protected region is optional to the user.

PRODUCT IDENTIFICATION: The product identification

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product.

Once the feature is enabled, the data in the protected sec-

tors can no longer be erased or programmed when input

levels of 5.5V or less are used. Data in the remaining

AT49BV/LV8011(T)

4

AT49BV/LV8011(T)

For details, see “Operating Modes” (for hardware opera-

tion) or “Software Product Identification”. The manufacturer

and device code is the same for both modes.

the I/O2 bit toggling. Please see “Status Bit Table” for more

details.

RDY/BUSY: An open drain READY/BUSY output pin pro-

vides another method of detecting the end of a program or

erase operation. RDY/BUSY is actively pulled low during

the internal program and erase cycles and is released at

the completion of the cycle. The open drain connection

allows for OR-tying of several devices to the same

RDY/BUSY line.

DATA POLLING: The AT49BV/LV8011(T) features DATA

polling to indicate the end of a program cycle. During a pro-

gram cycle an attempted read of the last byte/word loaded

will result in the complement of the loaded data on I/O7.

Once the program cycle has been completed, true data is

valid on all outputs and the next cycle may begin. During a

chip or sector erase operation, an attempt to read the

device will give a “0” on I/O7. Once the program or erase

cycle has completed, true data will be read from the device.

DATA polling may begin at any time during the program

cycle. Please see “Status Bit Table” for more details.

HARDWARE DATA PROTECTION: Hardware features

protect against inadvertent programs to the

AT49BV/LV8011(T) in the following ways: (a) V_CCsense: if

V_CCis below 1.8V (typical), the program function is inhib-

ited. (b) V_CCpower on delay: once V_CChas reached the

V_CCsense level, the device will automatically time out

10 ms (typical) before programming. (c) Program inhibit:

holding any one of OE low, CE high or WE high inhibits

program cycles. (d) Noise filter: pulses of less than 15 ns

(typical) on the WE or CE inputs will not initiate a program

cycle.

TOGGLE BIT: In addition to DATA polling, the

AT49BV/LV8011(T) provides another method for determin-

ing the end of a program or erase cycle. During a program

or erase operation, successive attempts to read data from

the same memory plane will result in I/O6 toggling between

“1” and “0”. Once the program cycle has completed, I/O6

will stop toggling and valid data will be read. Examining the

toggle bit may begin at any time during a program cycle.

INPUT LEVELS: While operating with a 2.7V to 3.3V

power supply, the address inputs and control inputs (OE,

CE, and WE) may be driven from 0 to 5.5V without

adversely affecting the operation of the device. The I/O

lines can only be driven from 0 to V_CC+ 0.6V.

An additional toggle bit is available on I/O2, which can be

used in conjunction with the toggle bit that is available on

I/O6. While a sector is erase suspended, a read or a

program operation from the suspended sector will result in

5

Command Definition in (Hex)⁽¹⁾

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Command

Sequence

Bus

Cycles Addr Data

Addr

Data Addr Data Addr Data

Addr

Data

Addr

Data

Read

1

6

4

6

Addr D_OUT

Chip Erase

5555

AA

2AAA

55

5555

80

A0

80

5555

Addr

5555

AA

D_IN

AA

2AAA

55

5555

10

30

Sector Erase

Byte/Word Program

Bypass Unlock

SA⁽³⁾⁽⁴⁾

2AAA

55

5555

A0

40

Single-pulse

Byte/Word Program

1

Addr

D_IN

Sector Lockout

Erase Suspend

Erase Resume

Product ID Entry

Product ID Exit⁽²⁾

6

1

3

1

5555

xxxx

PA⁽⁵⁾

5555

xxxx

AA

B0

30

2AAA

55

5555

80

5555

AA

SA⁽³⁾⁽⁴⁾

AA

F0

2AAA

55

5555

90

F0

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex). Address A18 through A14 are Don’t Care in the

word mode. Address A18 through A14 and A-1 are Don’t Care in the byte mode.

2. Either one of the Product ID Exit commands can be used.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next two

pages for details).

4. When the sector programming lockout feature is not enabled, the sector will erase (from the same Sector Erase command).

Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET pin is taken to

12V 0.5V.

5. PA is the plane address (A18 - A16).

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V_CC+ 0.6V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49BV/LV8011(T)

6

AT49BV/LV8011(T)

AT49BV/LV8011 – Sector Address Table

x8

x16

Plane

A

Sector

SA0

Size (Bytes/Words)

16K/8K

Address Range (A18 - A-1)

000000 - 003FFF

004000 - 00BFFF

00C000 - 00DFFF

00E000 - 00FFFF

010000 - 011FFF

012000 - 013FFF

014000 - 018FFF

01C000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

Address Range (A18 - A0)

00000 - 01FFF

02000 - 05FFF

06000 - 06FFF

07000 - 07FFF

08000 - 08FFF

09000 - 09FFF

0A000 - 0DFFF

0E000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

A

SA1

32K/16K

8K/4K

A

SA2

A

SA3

8K/4K

A

SA4

8K/4K

A

SA5

8K/4K

A

SA6

32K/16K

16K/8K

A

SA7

B

SA8

64K/32K

B

SA9

B

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

B

7

AT49BV/LV8011T – Sector Address Table

x8

x16

Plane

B

Sector

SA0

Size (Bytes/Words)

64K/32K

16K/8K

Address Range (A18 - A-1)

000000 - 00FFFF

010000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0E3FFF

0E4000 - 0EBFFF

0EC000 - 0EDFFF

0EE000 - 0EFFFF

0F0000 - 0F1FFF

0F2000 - 0F3FFF

0F4000 - 0FBFFF

0FC000 - 0FFFFF

Address Range (A18 - A0)

00000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 71FFF

72000 - 75FFF

76000 - 76FFF

77000 - 77FFF

78000 - 78FFF

79000 - 79FFF

7A000 - 7DFFF

7E000 - 7FFFF

B

SA1

B

SA2

B

SA3

B

SA4

B

SA5

B

SA6

B

SA7

B

SA8

B

SA9

B

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

B

A

32K/16K

8K/4K

A

8K/4K

A

8K/4K

A

8K/4K

A

32K/16K

16K/8K

A

AT49BV/LV8011(T)

8

AT49BV/LV8011(T)

DC and AC Operating Range

AT49LV8011(T)-90

0°C - 70°C

AT49BV8011(T)-12

0°C - 70°C

Com.

Operating

Temperature (Case)

Ind.

-40°C - 85°C

3.0V to 3.3V

-40°C - 85°C

2.7V to 3.3V

V_CCPower Supply

Operating Modes

Mode

(6)

CE

V_IL

V_IH

X

OE

V_IL

V_IH

X⁽¹⁾

X

WE

V_IH

V_IL

X

RESET

V_IH

V_PP

Ai

X

I/O

Read

X

V_CC

X

D_OUT

D_IN

Program/Erase⁽²⁾

Standby/Program Inhibit

Program Inhibit

Output Disable

Reset

V_IH

High-Z

V_IH

X

V_IH

X

V_IL

V_IH

X

V_IH

X

V_IH

X

High-Z

X

V_IL

X

Product Identification

A1 - A18 = V_IL, A9 = V_H⁽³⁾, A0 = V_IL

A1 - A18 = V_IL, A9 = V_H⁽³⁾, A0 = V_IH

A0 = V_IL, A1 - A18 = V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Hardware

V_IL

V_IH

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Software⁽⁵⁾

A0 = V_IH, A1 - A18 = V_IL

Notes: 1. X can be V_ILor V_IH.

2. Refer to AC programming waveforms.

3. V_H= 12.0V 0.5V.

4. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: 00CB-AT49BV8011; 004A-AT49BV8011T.

5. See details under “Software Product Identification Entry/Exit”.

6. For faster program/erase operations, V_PP= 5V 10%.

DC Characteristics

Symbol

Parameter

Condition

Min

Max

10

1

Units

µA

mA

V

I_LI

Input Load Current

V_IN= 0V to V_CC

I_LO

Output Leakage Current

V_CCStandby Current CMOS

V_CCStandby Current TTL

V_CCActive Current

V_I/O= 0V to V_CC

I_SB1

CE = V_CC- 0.3V to V_CC

CE = 2.0V to V_CC

f = 5 MHz; I_OUT= 0 mA

I_SB2

(1)

I_CC

30

50

0.6

I_CCRW

V_IL

V_CCRead while Write Current

Input Low Voltage

V_IH

Input High Voltage

2.0

2.4

V

V_OL

V_OH

Output Low Voltage

I_OL= 2.1 mA

I_OH= -400 µA

0.45

V

Output High Voltage

V

Note:

1. In the erase mode, I_CCis 50 mA.

9

AC Read Characteristics

AT49LV8011(T)-90

AT49BV8011(T)-12

Symbol

Parameter

Min

Max

90

Min

Max

120

50

Units

ns

t_ACC

Address to Output Delay

CE to Output Delay

(1)

t_CE

90

ns

(2)

t_OE

OE to Output Delay

0

40

0

ns

(3)(4)

t_DF

CE or OE to Output Float

Output Hold from OE, CE or Address, whichever occurred first

RESET to Output Delay

25

30

ns

t_OH

t_RO

ns

800

ns

AC Read Waveforms^(1)(2)(3)(4)

ADDRESS

ADDRESS VALID

CE

tCE

tOE

OE

tDF

tOH

tACC

tRO

RESET

HIGH Z

OUTPUT

VALID

OUTPUT

Notes: 1. CE may be delayed up to t_ACC- t_CEafter the address transition without impact on t_ACC

2. OE may be delayed up to t_CE- t_OEafter the falling edge of CE without impact on t_CEor by t_ACC- t_OEafter an address change

without impact on t_ACC

.

3. t_DFis specified from OE or CE whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and

Measurement Level

Output Test Load

t_R, t_F< 5 ns

Pin Capacitance

f = 1 MHz, T = 25°C⁽¹⁾

Symbol

C_IN

Typ

4

Max

6

Units

pF

Conditions

V_IN= 0V

C_OUT

8

12

pF

V_OUT= 0V

Note:

1. This parameter is characterized and is not 100% tested.

AT49BV/LV8011(T)

10

AT49BV/LV8011(T)

AC Byte/Word Load Characteristics

Symbol

Parameter

Min

10

Max

Units

ns

t

_AS, t_OES

Address, OE Setup Time

Address Hold Time

t_AH

t_CS

t_CH

t_WP

t_DS

100

0

ns

Chip Select Setup Time

Chip Select Hold Time

Write Pulse Width (WE or CE)

Data Setup Time

ns

0

ns

100

10

ns

t

_DH, t_OEH

Data, OE Hold Time

Write Pulse Width High

ns

t_WPH

50

ns

AC Byte/Word Load Waveforms

WE Controlled

CE Controlled

11

Program Cycle Characteristics

Symbol

Parameter

Min

Typ

Max

Units

µs

t_BP

Byte/Word Programming Time

Address Setup Time

Address Hold Time

Data Setup Time

20

50

t_AS

0

ns

t_AH

100

10

ns

t_DS

ns

t_DH

Data Hold Time

ns

t_WP

Write Pulse Width

100

50

ns

t_WPH

t_EC

Write Pulse Width High

Chip Erase Cycle Time

Sector Erase Cycle Time

ns

10

seconds

ms

t_SEC

200

Program Cycle Waveforms

PROGRAM CYCLE

OE

CE

t

BP

t

WP

WPH

WE

t

AS

AH

DH

5555

2AAA

ADDRESS

A0 -A18

DATA

t

DS

INPUT

DATA

55

A0

AA

Sector or Chip Erase Cycle Waveforms

OE ⁽¹⁾

(4)

CE

t

WP

WPH

WE

A0-A18

DATA

t

DH

AS

AH

5555

Note 2

2AAA

t

EC

DS

55

WORD 1

80

WORD 2

55

WORD 4

Note 3

WORD 5

AA

WORD 0

AA

WORD 3

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See

note 3 under command definitions.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

4. The t_WPHtime between the 5th and 6th bus cycle should be a minimum of 150 ns.

AT49BV/LV8011(T)

12

AT49BV/LV8011(T)

Data Polling Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

Write Recovery Time

ns

t_WR

0

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in “AC Read Characteristics”.

Data Polling Waveforms

A0-A18

Toggle Bit Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

t_OEHP

t_WR

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

OE High Pulse

ns

150

0

ns

Write Recovery Time

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in “AC Read Characteristics”.

Toggle Bit Waveforms^(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

The t_OEHPspecification must be met by the toggling input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

13

Software Product Identification Entry⁽¹⁾Sector Lockout Enable Algorithm⁽¹⁾

LOAD DATA AA

TO

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 80

TO

LOAD DATA 90

TO

ADDRESS 5555

LOAD DATA AA

TO

ENTER PRODUCT

IDENTIFICATION

ADDRESS 5555

(2)(3)(5)

MODE

LOAD DATA 55

TO

Software Product Identification Exit⁽¹⁾⁽⁷⁾

ADDRESS 2AAA

OR

LOAD DATA AA

LOAD DATA F0

TO

ADDRESS 5555

ANY ADDRESS

LOAD DATA 40

TO

EXIT PRODUCT

IDENTIFICATION

ADDRESS 5555

LOAD DATA 55

TO

(4)

MODE

ADDRESS 2AAA

PAUSE 200 µs⁽²⁾

LOAD DATA F0

TO

ADDRESS 5555

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t

Care).

EXIT PRODUCT

IDENTIFICATION

2. Sector lockout feature enabled.

(4)

MODE

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t

Care).

2. A1 - A18 = V_IL.

Manufacture Code is read for A0 = V_IL;

Device Code is read for A0 = V_IH

.

3. The device does not remain in identification mode if pow-

ered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH(x8); 001FH(x16)

6. Device Code:00CB-AT49BV8011;

004A-AT49BV8011T.

7. Either one of the Product ID Exit commands can be used.

AT49BV/LV8011(T)

14

AT49BV/LV8011(T)

Status Bit Table

Status Bit

I/O6

I/O7

I/O2

Read Address In

While

Plane A

Plane B

Plane A

Plane B

Plane A

Plane B

Programming in Plane A

Programming in Plane B

I/O7

DATA

I/O7

TOGGLE

DATA

1

DATA

1

DATA

TOGGLE

DATA

Erasing in Plane A

Erasing in Plane B

0

DATA

0

TOGGLE

DATA

TOGGLE

DATA

TOGGLE

Erase Suspended & Read

Erasing Sector

1

TOGGLE

DATA

TOGGLE

DATA

Erase Suspended & Read

Non-erasing Sector

DATA

Erase Suspended &

Program Erasing Sector

1

TOGGLE

DATA

Erase Suspended &

Program Non-erasing

Sector in Plane A

I/O7

DATA

TOGGLE

DATA

Erase Suspended &

Program Non-erasing

Sector in Plane B

DATA

I/O7

DATA

TOGGLE

DATA

TOGGLE

15

AT49BV/LV8011(T) Ordering Information

I

_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

25

0.01

AT49LV8011-90CC

AT49LV8011-90TC

48C3

48T

Commercial

(0° to 70°C)

90

120

90

25

AT49LV8011-90CI

AT49LV8011-90TI

48C3

48T

Industrial

(-40° to 85°C)

AT49BV8011-12CC

AT49BV8011-12TC

48C3

48T

Commercial

(0° to 70°C)

AT49BV8011-12CI

AT49BV8011-12TI

48C3

48T

Industrial

(-40° to 85°C)

AT49LV8011T-90CC

AT49LV8011T-90TC

48C3

48T

Commercial

(0° to 70°C)

AT49LV8011T-90CI

AT49LV8011T-90TI

48C3

48T

Industrial

(-40° to 85°C)

AT49BV8011T-12CC

AT49BV8011T-12TC

48C3

48T

Commercial

(0° to 70°C)

120

AT49BV8011T-12CI

AT49BV8011T-12TI

48C3

48T

Industrial

(-40° to 85°C)

Package Type

48C3

48T

48-ball, Plastic Chip-size Ball Grid Array Package (CBGA)

48-lead, Thin Small Outline Package (TSOP)

AT49BV/LV8011(T)

16

Packaging Information

48C3, 48-ball, Plastic Chip-size Ball Grid Array

Package (CBGA)

48T, 48-lead, Plastic Thin Small Outline Package

(TSOP)

Dimensions in Millimeters and (Inches)*

JEDEC OUTLINE MO-142 DD

7.15 (0.281)

6.85 (0.270)

7.15 (0.281)

6.85 (0.270)

0.30 (0.012)

1.20 (0.047)

4.0 (0.157)

6

5

4

3

2

1

1.00 (0.039)

A

B

C

D

E

F

5.6 (0.220)

G

H

0.80 (0.031) BSC

0.46 (0.018) DIA BALL TYP

NON-ACCUMULATIVE

*Controlling dimension: millimeters

AT49BV/LV8011(T)

17

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Europe

Atmel Rousset

Zone Industrielle

13106 Rousset Cedex

France

Atmel U.K., Ltd.

Coliseum Business Centre

Riverside Way

Camberley, Surrey GU15 3YL

England

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

TEL (44) 1276-686-677

FAX (44) 1276-686-697

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life support devices or systems.

®

™

Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.

Terms and product names in this document may be trademarks of others.

Printed on recycled paper.

1265E–01/00/xM


型号：	AT49BV8011T-12TI
厂家：	ATMEL
描述：	8-megabit (512K x 16/1M x 8) 3-volt Only Flash Memory 8兆位（ 512K ×16 / 1M ×8 ）的3伏只快闪记忆体
文件：	总18页 (文件大小：307K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT49BV8011T-12TI [ATMEL]

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