AT49BV161-70CI_技术文档

Features

• Single Voltage Read/Write Operation: 2.65V to 3.3V (BV), 3.0V to 3.6V (LV)

• Access Time – 70 ns

• Sector Erase Architecture

– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout

– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

• Fast Word Program Time – 20 µs

• Fast Sector Erase Time – 300 ms

• Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming from Any Sector by Suspending Erase of a

Different Sector

– Supports Reading Any Byte/Word by Suspending Programming of Any Other

Byte/Word

• Low-power Operation

16-megabit

(1M x 16/2M x 8)

3-volt Only

– 30 mA Active

– 10 µA Standby

• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

• VPP Pin for Write Protection and Accelerated Program/Erase Operations

• RESET Input for Device Initialization

Flash Memory

• Sector Lockdown Support

• TSOP and CBGA Package Options

• Top or Bottom Boot Block Configuration Available

• 128-bit Protection Register

AT49BV160

AT49LV160

AT49BV160T

AT49BV161

AT49LV161

AT49BV161T

AT49LV161T

Description

The AT49BV/LV16X(T) is a 3.0-volt 16-megabit Flash memory organized as 1,048,576

words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0

- I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 39 sectors for

erase operations. The device is offered in a 48-lead TSOP, 45-ball and 48-ball CBGA

packages. The device has CE and OE control signals to avoid any bus contention.

This device can be read or reprogrammed using a single 2.65V power supply, making

it ideally suited for in-system programming.

Pin Configurations

Pin Name

A0 - A19

CE

Function

Addresses

Chip Enable

Output Enable

Write Enable

Reset

OE

WE

RESET

RDY/BUSY

VPP

READY/BUSY Output

Write Protection and Power Supply for Accelerated Program/Erase

Operations

I/O0 - I/O14

I/O15 (A-1)

Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

BYTE

NC

Selects Byte or Word Mode

No Connect

Rev. 1427L–FLASH–02/03

VCCQ

Output Power Supply

1

TSOP Top View

CBGA Top View

Type 1

8

1

2

3

4

5

6

7

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

2

VCCQ

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

OE

A

B

C

D

E

F

3

A13

A14

A15

A16

A11

A10

A8

WE

VPP

RST

A19

A17

A6

A7

A5

A4

A2

4

5

A18

6

7

A12

A9

A3

A1

A8

8

NC

9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I/O14

I/O5

I/O6

I/O13

I/O11

I/O12

I/O4

I/O2

I/O3

I/O8

I/O9

CE

A0

WE

RESET

VPP

NC

AT49BV/LV160(T)

VCCQ I/O15

I/O0

I/O1

GND

OE

GND

I/O7

VCC I/O10

A19

A18

A17

A7

A6

A5

A4

A3

GND

CE

A2

A1

A0

TSOP Top View

CBGA Top View

Type 1

1

2

3

4

5

6

A15

1

48

A16

A14

A13

A12

A11

A10

A9

2

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

BYTE

GND

I/O15/A-1

I/O7

A

B

C

D

E

F

3

A3

A4

A7 RDY/BUSY WE

A9

A13

A12

A14

A15

A16

4

5

6

I/O14

I/O6

A17

A6

NC RESET A8

7

A8

8

I/O13

I/O5

A2

A18

NC

VPP

A19

I/O5

A10

A11

I/O7

A19

NC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I/O12

I/O4

WE

A1

A5

RESET

VPP

NC

VCC

I/O11

I/O3

AT49BV/LV161(T)

A0

I/O0

I/O8

I/O9

I/O1

I/O2

RDY/BUSY

A18

A17

A7

I/O10

I/O2

CE

OE

VSS

I/O10 I/O12 I/O14 BYTE

I/O9

G

H

I/O1

I/O11 VCC I/O13 I/O15

/A-1

A6

I/O8

A5

I/O0

A4

OE

I/O3

I/O4

I/O6

VSS

A3

GND

CE

A2

A1

A0

2

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

The device powers on in the read mode. Command sequences are used to place the device in

other operation modes such as program and erase. The device has the capability to protect

the data in any sector. (See “Sector Lockdown” section.)

To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend

feature. This feature will put the Erase or Program on hold for any amount of time and let the

user read data from or program data to any of the remaining sectors within the memory. The

end of a program or an erase cycle is detected by the Ready/Busy pin, Data Polling or by the

toggle bit.

The VPP pin provides data protection and faster programming. When the V_PPinput is below

0.8V, the program and erase functions are inhibited. When V_PPis at 1.65V or above, normal

program and erase operations can be performed. With V_PPat 5.0V or 12.0V, the program and

erase operations are accelerated.

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement

of entering the three-byte program sequence is offered to further improve programming time.

After entering the six-byte code, only single pulses on the write control lines are required for

writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering

down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing

it back to V_CC. Erase, Erase Suspend/Resume, and Program Suspend/Resume commands

will not work while in this mode; if entered they will result in data being programmed into the

device. It is not recommended that the six-byte code reside in the software of the final product

but only exist in external programming code.

When using the AT49BV/LV160(T) pinout configuration, the device always operates in the

word mode. In the AT49BV/LV161(T) configuration, the BYTE pin controls whether the device

data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic “1”, the

device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins

I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-

stated, and the I/O15 pin is used as an input for the LSB (A-1) address function.

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1427L–FLASH–02/03

Block Diagram

I/O0 - I/O15/A-1

OUTPUT

BUFFER

INPUT

BUFFER

IDENTIFIER

REGISTER

INPUT

A0 - A19

BUFFER

STATUS

CE

REGISTER

WE

COMMAND

REGISTER

OE

RESET

BYTE

ADDRESS

LATCH

DATA

RDY/BUSY

VPP

COMPARATOR

WRITE STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

Y-DECODER

X-DECODER

Y-GATING

VCC

GND

MAIN

MEMORY

4

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

Device

Operation

READ: The AT49BV/LV16X(T) is accessed like an EPROM. When CE and OE are low and

WE is high, the data stored at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE

is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or

standby mode, depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the “Command Definition in Hex” table on page 13 (I/O8 - I/O15 are

don’t care inputs for the command codes). The command sequences are written by applying a

low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address

is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the

first rising edge of CE or WE. Standard microprocessor write timings are used. The address

locations used in the command sequences are not affected by entering the command

sequences.

RESET: A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high-impedance

state. When a high level is reasserted on the RESET pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of

memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-

mand or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase

software code. After the chip erase has been initiated, the device will internally time the erase

operation so that no external clocks are required. The maximum time to erase the chip is t_EC

.

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sec-

tors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus

cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while

the 30H data input command is latched on the rising edge of WE. The sector erase starts after

the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a sector is t_SEC. When the sec-

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector

Erase command). An attempt to erase a sector that has been protected will result in the oper-

ation terminating in 2 µs.

BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi-

cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the

internal device command register and is a four-bus cycle operation. The device will automati-

cally generate the required internal program pulses.

5

1427L–FLASH–02/03

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified t_BPcycle

time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a

program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the

erase or program operation was performed successfully.

VPP PIN: The circuitry of the AT49BV/LV16X(T) is designed so that the device can be pro-

grammed or erased from the V_CCpower supply or from the VPP input pin. When V_PPis greater

than 1.65V and less than or equal to the VCC pin, the device selects the V_CCsupply for pro-

gramming and erase operations. When the VPP pin is greater than the V_CCsupply, the device

will select the V_PPinput as the power supply for programming and erase operations. The

device will allow for some variations between the V_PPinput and the V_CCpower supply in its

selection of V_CCor V_PPfor program or erase operations. If the VPP pin is within 0.3V of V_CCfor

2.65V < V_CC< 3.6V, then the program or erase operations will use V_CCand disregard the V_PP

input signal. When the V_PPsignal is used for program and erase operations, the V_PPmust be

in the 5V 0.5V or 12V 0.5V range to ensure proper operation. The V_pppin cannot be left

floating.

PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a

program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 12

and the following four sections describe the function of these bits. To provide greater flexibility

for system designers, the AT49BV/LV16X(T) contains a programmable configuration register.

The configuration register allows the user to specify the status bit operation. The configuration

register can be set to one of two different values, “00” or “01”. If the configuration register is set

to “00”, the part will automatically return to the read mode after a successful program or erase

operation. If the configuration register is set to a “01”, a Product ID Exit command must be

given after a successful program or erase operation before the part will return to the read

mode. It is important to note that whether the configuration register is set to a “00” or to a “01”,

any unsuccessful program or erase operation requires using the Product ID Exit command to

return the device to read mode. The default value (after power-up) for the configuration regis-

ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the

“Command Definition in Hex” table on page 13, the value of the configuration register can be

changed. Voltages applied to the RESET pin will not alter the value of the configuration regis-

ter. The value of the configuration register will affect the operation of the I/O7 status bit as

described below.

DATA POLLING: The AT49BV/LV16X(T) features Data Polling to indicate the end of a pro-

gram cycle. If the status configuration register is set to a “00”, during a program cycle an

attempted read of the last byte/word loaded will result in the complement of the loaded data on

I/O7. Once the program cycle has been completed, true data is valid on all outputs and the

next cycle may begin. During a chip or sector erase operation, an attempt to read the device

will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read

from the device. Data Polling may begin at any time during the program cycle. Please see

“Status Bit Table” on page 12 for more details.

6

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the

device is actively programming or erasing data. I/O7 will go high when the device has com-

pleted a program or erase operation. Once I/O7 has gone high, status information on the other

pins can be checked.

The Data Polling status bit must be used in conjunction with the erase/program and V_PPstatus

bit as shown in the algorithm in Figures 1 and 2 on page 10.

TOGGLE BIT: In addition to Data Polling, the AT49BV/LV16X(T) provides another method for

determining the end of a program or erase cycle. During a program or erase operation, suc-

cessive attempts to read data from the memory will result in I/O6 toggling between one and

zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be

read. Examining the toggle bit may begin at any time during a program cycle. Please see “Sta-

tus Bit Table” on page 12 for more details.

The toggle bit status bit should be used in conjunction with the erase/program and V_PPstatus

bit as shown in the algorithm in Figures 3 and 4 on page 11.

ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates

whether the program or erase operation has exceeded a specified internal pulse count limit. If

the status bit is a “1”, the device is unable to verify that an erase or a byte/word program oper-

ation has been successfully performed. The device may also output a “1” on I/O5 if the system

tries to program a “1” to a location that was previously programmed to a “0”. Only an erase

operation can change a “0” back to a “1”. If a program (Sector Erase) command is issued to a

protected sector, the protected sector will not be programmed (erased). The device will go to a

status read mode and the I/O5 status bit will be set high, indicating the program (erase) opera-

tion did not complete as requested. Once the erase/program status bit has been set to a “1”,

the system must write the Product ID Exit command to return to the read mode. The

erase/program status bit is a “0” while the erase or program operation is still in progress.

Please see “Status Bit Table” on page 12 for more details.

V_PPSTATUS BIT: The AT49BV/LV16X(T) provides a status bit on I/O3, which provides infor-

mation regarding the voltage level of the VPP pin. During a program or erase operation, if the

voltage on the VPP pin is not high enough to perform the desired operation successfully, the

I/O3 status bit will be a “1”. Once the V_PPstatus bit has been set to a “1”, the system must

write the Product ID Exit command to return to the read mode. On the other hand, if the volt-

age level is high enough to perform a program or erase operation successfully, the V_PPstatus

bit will output a “0”. Please see “Status Bit Table” on page 12 for more details.

SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre-

vents programming of data in the designated sectors once the feature has been enabled.

These sectors can contain secure code that is used to bring up the system. Enabling the lock-

down feature will allow the boot code to stay in the device while data in the rest of the device is

updated. This feature does not have to be activated; any sector’s usage as a write-protected

region is optional to the user.

At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector,

the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked

down, the contents of the sector is read-only and cannot be erased or programmed.

SECTOR LOCKDOWN DETECTION: A software method is available to determine if program-

ming of a sector is locked down. When the device is in the software product identification

mode (see “Software Product Identification Entry/Exit” sections on page 24), a read from

address location 00002H within a sector will show if programming the sector is locked down. If

the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program

lockdown feature has been enabled and the sector cannot be programmed. The software

product identification exit code should be used to return to standard operation.

7

1427L–FLASH–02/03

SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is

through reset or power-up cycles. After power-up or reset, the content of a sector that is

locked down can be erased and reprogrammed.

ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to

interrupt a sector erase or chip erase operation and then program or read data from a different

sector within the memory. After the Erase Suspend command is given, the device requires a

maximum time of 15 µs to suspend the erase operation. After the erase operation has been

suspended, the system can then read data or program data to any other sector within the

device. An address is not required during the Erase Suspend command. During a sector erase

suspend, another sector cannot be erased. To resume the sector erase operation, the system

must write the Erase Resume command. The Erase Resume command is a one-bus cycle

command. The device also supports an erase suspend during a complete chip erase. While

the chip erase is suspended, the user can read from any sector within the memory that is pro-

tected. The command sequence for a chip erase suspend and a sector erase suspend are the

same.

PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the

system to interrupt a programming operation and then read data from a different byte/word

within the memory. After the Program Suspend command is given, the device requires a max-

imum of 15 µs to suspend the programming operation. After the programming operation has

been suspended, the system can then read data from any other byte/word within the device.

An address is not required during the program suspend operation. To resume the program-

ming operation, the system must write the Program Resume command. The program suspend

and resume are one-bus cycle commands. The command sequence for the erase suspend

and program suspend are the same, and the command sequence for the erase resume and

program resume are the same.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-

ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware

operation mode can be used by an external programmer to identify the correct programming

algorithm for the Atmel product.

For details, see “Operating Modes” on page 17 (for hardware operation) or “Software Product

Identification Entry/Exit” on page 24. The manufacturer and device codes are the same for

both modes.

128-BIT PROTECTION REGISTER: The AT49BV/LV16X(T) contains a 128-bit register that

can be used for security purposes in system design. The protection register is divided into two

64-bit blocks. The two blocks are designated as block A and block B. The data in block A is

non-changeable and is programmed at the factory with a unique number. The data in block B

is programmed by the user and can be locked out such that data in the block cannot be repro-

grammed. To program block B in the protection register, the four-bus cycle Program

Protection Register command must be used as shown in the “Command Definition in Hex”

table on page 13. To lock out block B, the four-bus cycle Lock Protection Register command

must be used as shown in the “Command Definition in Hex” table on page 13. Data bit D1

must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are

don’t cares. To determine whether block B is locked out, the Product ID Entry command is

given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked.

If data bit D1 is one, block B can be reprogrammed. Please see the “Protection Register

Addressing Table” on page 14 for the address locations in the protection register. To read the

protection register, the Product ID Entry command is given followed by a normal read opera-

tion from an address within the protection register. After determining whether block B is

protected or not, or reading the protection register, the Product ID Exit command must be

given prior to performing any other operation.

8

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

RDY/BUSY: For the AT49BV/LV161(T), an open-drain READY/BUSY output pin provides

another method of detecting the end of a program or erase operation. RDY/BUSY is actively

pulled low during the internal program and erase cycles and is released at the completion of

the cycle. The open-drain connection allows for OR-tying of several devices to the same

RDY/BUSY line. Please see “Status Bit Table” on page 12 for more details.

HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against

inadvertent programs to the AT49BV/LV16X(T) in the following ways: (a) V_CCsense: if V_CCis

below 1.8V (typical), the program function is inhibited. (b) V_CCpower-on delay: once V_CChas

reached the V_CCsense level, the device will automatically time out 10 ms (typical) before pro-

gramming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits

program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will

not initiate a program cycle. (e) Program inhibit: V_PPis less than V_ILPP. (f) V_PPpower-on delay:

once V_PPhas reached 1.65V, program and erase operations can occur after 100 ns.

INPUT LEVELS: While operating with a 2.65V to 3.6V power supply, the address inputs and

control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the

operation of the device. The I/O lines can only be driven from 0 to V_CC+ 0.6V.

OUTPUT LEVELS: For the AT49BV/LV160(T), output high levels (V_OH) are equal to V_CCQ

-

0.2V (not V_CC). For 2.65V - 3.6V output levels, V_CCQmust be tied to V_CC. For 1.8V - 2.2V out-

put levels, V_CCQmust be regulated to 2.0V 10%, while V_CCmust be regulated to 2.65V - 3.0V

(for minimum power).

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1427L–FLASH–02/03

Figure 1. Data Polling Algorithm

Figure 2. Data Polling Algorithm

(Configuration Register = 00)

(Configuration Register = 01)

START

Read I/O7 - I/O0

Addr = VA

Read I/O7 - I/O0

Addr = VA

NO

I/O7 = 1?

YES

I/O7 = Data?

NO

YES

NO

I/O3, I/O5 = 1?

NO

I/O3, I/O5 = 1?

YES

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

Program/Erase

Operation Not

Successful, Write

Product ID

Read I/O7 - I/O0

Addr = VA

Exit Command

Note:

1. VA = Valid address for programming. During a sec-

YES

I/O7 = Data?

NO

tor erase operation, a valid address is any sector

address within the sector being erased. During

chip erase, a valid address is any non-protected

sector address.

Program/Erase

Operation Not

Successful, Write

Product ID

Program/Erase

Operation

Successful,

Device in

Exit Command

Read Mode

Notes: 1. VA = Valid address for programming. During a sec-

tor erase operation, a valid address is any sector

address within the sector being erased. During

chip erase, a valid address is any non-protected

sector address.

2. I/O7 should be rechecked even if I/O5 = “1”

because I/O7 may change simultaneously with

I/O5.

10

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

Figure 3. Toggle Bit Algorithm

Figure 4. Toggle Bit Algorithm

(Configuration Register = 00)

(Configuration Register = 01)

START

Read I/O7 - I/O0

NO

Toggle Bit =

Toggle?

Toggle Bit =

Toggle?

YES

NO

I/O3, I/O5 = 1?

YES

Read I/O7 - I/O0

Twice

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

Toggle Bit =

Toggle?

NO

YES

Program/Erase

Operation Not

Successful, Write

Product ID

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

Program/Erase

Operation Not

Successful, Write

Product ID

Program/Erase

Operation

Successful

Exit Command

Note:

1. The system should recheck the toggle bit even if

I/O5 = “1” because the toggle bit may stop toggling

as I/O5 changes to “1”.

Note:

1. The system should recheck the toggle bit even if

I/O5 = “1” because the toggle bit may stop toggling

as I/O5 changes to “1”.

11

1427L–FLASH–02/03

Status Bit Table

Status Bit

I/O7

00

I/O7

0

I/O7

01

0

I/O6

00/01

I/O5⁽¹⁾

I/O3⁽²⁾

I/O2

00/01

RDY/BUSY

Configuration Register:

Programming

00/01

TOGGLE

1

0

1

0

1

Erasing

0

TOGGLE

Erase Suspended & Read

Erasing Sector

1

Erase Suspended & Read

Non-erasing Sector

DATA

I/O7

DATA

0

DATA

0

DATA

0

DATA

1

0

Erase Suspended &

TOGGLE

Program Non-erasing Sector

Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or

sector erase operation is performed on a protected sector.

2. I/O3 switches to a “1” when the V_PPlevel is not high enough to successfully perform program and erase operations.

12

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

Command Definition in Hex⁽¹⁾

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Command

Sequence

Bus

Cycles

Addr

555

Data

D_OUT

AA

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read

1

6

4

Chip Erase

AAA⁽²⁾

AAA

55

555

80

A0

555

AA

D_IN

AAA

55

555

SA⁽³⁾⁽⁴⁾

10

30

Sector Erase

Byte/Word Program

555

AA

555

AA

AAA

Addr

Enter Single Pulse

Program Mode

6

555

AA

AAA

55

555

80

555

AA

AAA

55

555

A0

60

Single Pulse

Byte/Word Program

1

6

1

Addr

555

D_IN

AA

B0

Sector Lockdown

AAA

55

555

80

555

AA

SA⁽³⁾⁽⁴⁾

Erase/Program

Suspend

XXX

Erase/Program

Resume

1

XXX

30

Product ID Entry

Product ID Exit⁽⁵⁾

3

1

555

AA

F0

AAA

55

555

90

F0

XXX

Program Protection

Register

4

555

AA

AAA

55

555

C0

90

Addr

080

80

D_IN

X0

Lock Protection

Register - Block B

Status of Block B

Protection

(6)

D_OUT

Set Configuration

Register

D0

XXX

00/01⁽⁷⁾

Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don’t Care.

The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don’t Care

in the word mode. Address A19 through A11 and A-1 are Don’t Care in the byte mode.

2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.

3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 15 and

16 for details).

4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power

cycled.

5. Either one of the Product ID Exit commands can be used.

6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.

7. The default state (after power-up) of the configuration register is “00”.

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V_CC+ 0.6V

Voltage on OE and V_PP

with Respect to Ground...................................-0.6V to +13.0V

13

1427L–FLASH–02/03

Protection Register Addressing Table

Word

Use

Factory

User

Block

A7

A6

0

A5

0

A4

0

A3

0

A2

0

A1

0

A0

1

0

1

2

3

4

5

6

7

A

B

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

User

1

0

1

0

User

1

0

1

User

1

0

1

0

Note:

1. All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.

14

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

AT49BV/LV160/161 – Sector Address Table

x8

x16

Sector

SA0

Size (Bytes/Words)

8K/4K

Address Range (A19 - A-1)

000000 - 001FFF

002000 - 003FFF

004000 - 005FFF

006000 - 007FFF

008000 - 009FFF

00A000 - 00BFFF

00C000 - 00DFFF

00E000 - 00FFFF

010000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

100000 - 10FFFF

110000 - 11FFFF

120000 - 12FFFF

130000 - 13FFFF

140000 - 14FFFF

150000 - 15FFFF

160000 - 16FFFF

170000 - 17FFFF

180000 - 18FFFF

190000 - 19FFFF

1A0000 - 1AFFFF

1B0000 - 1BFFFF

1C0000 - 1CFFFF

1D0000 - 1DFFFF

1E0000 - 1EFFFF

1F0000 - 1FFFFF

Address Range (A19 - A0)

00000 - 00FFF

01000 - 01FFF

02000 - 02FFF

03000 - 03FFF

04000 - 04FFF

05000 - 05FFF

06000 - 06FFF

07000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F7FFF

F8000 - FFFFF

SA1

8K/4K

SA2

8K/4K

SA3

8K/4K

SA4

8K/4K

SA5

8K/4K

SA6

8K/4K

SA7

8K/4K

SA8

64K/32K

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

15

1427L–FLASH–02/03

AT49BV/LV160T/161T – Sector Address Table

x8

x16

Sector

SA0

Size (Bytes/Words)

64K/32K

8K/4K

Address Range (A19 - A-1)

000000 - 00FFFF

010000 - 01FFFF

020000 - 02FFFF

030000 - 03FFFF

040000 - 04FFFF

050000 - 05FFFF

060000 - 06FFFF

070000 - 07FFFF

080000 - 08FFFF

090000 - 09FFFF

0A0000 - 0AFFFF

0B0000 - 0BFFFF

0C0000 - 0CFFFF

0D0000 - 0DFFFF

0E0000 - 0EFFFF

0F0000 - 0FFFFF

100000 - 10FFFF

110000 - 11FFFF

120000 - 12FFFF

130000 - 13FFFF

140000 - 14FFFF

150000 - 15FFFF

160000 - 16FFFF

170000 - 17FFFF

180000 - 18FFFF

190000 - 19FFFF

1A0000 - 1AFFFF

1B0000 - 1BFFFF

1C0000 - 1CFFFF

1D0000 - 1DFFFF

1E0000 - 1EFFFF

1F0000 - 1F1FFF

1F2000 - 1F3FFF

1F4000 - 1F5FFF

1F6000 - 1F7FFF

1F8000 - 1F9FFF

1FA000 - 1FBFFF

1FC000 - 1FDFFF

1FE000 - 1FFFFF

Address Range (A19 - A0)

00000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F7FFF

F8000 - F8FFF

F9000 - F9FFF

FA000 - FAFFF

FB000 - FBFFF

FC000 - FCFFF

FD000 - FDFFF

FE000 - FEFFF

FF000 - FFFFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

8K/4K

16

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

DC and AC Operating Range

AT49BV/LV16X(T)-70

-40°C - 85°C

AT49BV/LV16X(T)-90

-40°C - 85°C

Operating Temperature (Case)

_CCPower Supply

Ind.

V

2.65V to 3.3V/3.0V to 3.6V

Operating Modes

Mode

CE

V_IL

V_IH

X

OE

WE

V_IH

V_IL

X

RESET

V_IH

V_PP

Ai

X

I/O

Read

V_IL

V_IH

X⁽¹⁾

X

D_OUT

D_IN

Program/Erase⁽²⁾

Standby/Program Inhibit

V_IH

V_IHPP

(6)

V_IH

X

High-Z

V_IH

X

V_IH

Program Inhibit

X

V_IL

X

V_IH

(7)

X

V_IH

V_ILPP

Output Disable

Reset

X

V_IH

X

V_IH

X

High-Z

X

V_IL

X

Product Identification

A1 - A19 = V_IL, A9 = V_H⁽³⁾, A0 = V_IL

A1 - A19 = V_IL, A9 = V_H⁽³⁾, A0 = V_IH

A0 = V_IL, A1 - A19 = V_IL

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Hardware

V_IL

V_IH

Manufacturer Code⁽⁴⁾

Device Code⁽⁴⁾

Software⁽⁵⁾

A0 = V_IH, A1 - A19 = V_IL

Notes: 1. X can be V_ILor V_IH.

2. Refer to AC programming waveforms on page 23.

3. V_H= 12.0V 0.5V.

4. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C0H (x8)-AT49BV/LV16X; 00C0H (x16)-AT49BV/LV16X;

C2H (x8)-AT49BV/LV16XT; 00C2H (x16)-AT49BV/LV16XT.

5. See details under “Software Product Identification Entry/Exit” on page 24.

6. V_IHPP(min) = 1.65V; V_IHPP(max) = 3.6V. For faster erase/program operations, V_PPcan be set to 5.0V 0.5V or 12V 0.5V.

7. V_ILPP(max) = 0.8V.

17

1427L–FLASH–02/03

DC Characteristics

Symbol

Parameter

Condition

Min

Max

10

1

Units

µA

mA

µA

mA

µA

mA

V

I_LI

Input Load Current

V_IN= 0V to V_CC

I_LO

Output Leakage Current

V_CCStandby Current CMOS

V_CCStandby Current TTL

V_CCActive Read Current

V_CCProgramming Current (V_PP= V_CC

V_I/O= 0V to V_CC

I_SB1

I_SB2

I_SB3

CE = V_CC- 0.3V to V_CC

CE = 2.0V to V_CC

CE = 2.0V to V_CC, V_CC= 2.85V

f = 5 MHz; I_OUT= 0 mA, 3.3V≤ V_CC

10

30

45

10

40

5

(1)(2)

I_CC

I_CC1

)

V

_PP= 0V, V_CC= 3.0V

I_PP1

V_PPInput Load Current

V_PP= V_CC= 3.0V

I_CC2

I_PP2

I_CC3

I_PP3

V_IL

V_CCProgramming Current (V_PP= 5.0V 0.5V)

V_PPProgramming Current (V_PP= 5.0V 0.5V)

V_CCProgramming Current (V_PP= 12.0V 0.5V)

V_PPProgramming Current (V_PP= 12.0V 0.5V)

Input Low Voltage

40

6

0.6

V_IH

Input High Voltage

2.0

V

V_OL1

V_OL2

Output Low Voltage

I_OL= 2.1 mA

I_OL= 1.0 mA

0.45

0.20

V

Output Low Voltage

V

V_CCQ- 0.2

[AT49BV/LV160(T)]

I_OH= -400 µA

V

_CCQ< 2.6V

V

V_OH1

Output High Voltage

I

_OH= -400 µA

V_CCQ≥ 2.6V

2.4 [AT49BV/LV160(T)]

2.4 [AT49BV/LV161(T)]

V

_CCQ- 0.1

I_OH= -100 µA

V

_CCQ< 2.6V

V

[AT49BV/LV160(T)]

2.5 [AT49BV/LV160(T)]

2.5 [AT49BV/LV161(T)]

V_OH2

I

_OH= -100 µA

V_CCQ≥ 2.6V

Notes: 1. In the erase mode, I_CCis 50 mA.

2. For 3.3V < V_CC< 3.6V, I_CC(max) = 35 mA

18

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

.

AC Read Characteristics

AT49BV/LV16X(T)-70

AT49BV/LV16X(T)-90

Symbol

t_RC

Parameter

Min

Max

70

Min

Max

90

Units

ns

Read Cycle Time

t_ACC

Address to Output Delay

CE to Output Delay

OE to Output Delay

CE or OE to Output Float

70

90

ns

(1)

t_CE

70

90

ns

(2)

t_OE

0

35

0

40

ns

(3)(4)

t_DF

25

ns

Output Hold from OE, CE or Address, whichever occurred

first

t_OH

t_RO

0

ns

RESET to Output Delay

100

AC Read Waveforms^(1)(2)(3)(4)

tRC

ADDRESS

CE

ADDRESS VALID

tCE

tOE

OE

tDF

tOH

tACC

tRO

RESET

HIGH Z

OUTPUT

VALID

OUTPUT

Notes: 1. CE may be delayed up to t_ACC- t_CEafter the address transition without impact on t_ACC

2. OE may be delayed up to t_CE- t_OEafter the falling edge of CE without impact on t_CEor by t_ACC- t_OEafter an address change

without impact on t_ACC

.

3. t_DFis specified from OE or CE, whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

19

1427L–FLASH–02/03

Input Test Waveforms and Measurement Level

Output Test Load

Pin Capacitance

f = 1 MHz, T = 25°C⁽¹⁾

Symbol

C_IN

Typ

4

Max

6

Units

pF

Conditions

V_IN= 0V

C_OUT

8

12

pF

V_OUT= 0V

Note:

1. This parameter is characterized and is not 100% tested

20

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

.

AC Byte/Word Load Characteristics

Symbol

Parameter

Min

0

Max

Units

ns

t

_AS, t_OES

Address, OE Setup Time

Address Hold Time

t_AH

t_CS

t_CH

t_WP

t_DS

40

0

ns

Chip Select Setup Time

Chip Select Hold Time

Write Pulse Width (WE or CE)

Data Setup Time

ns

0

ns

40

30

0

ns

t

_DH, t_OEH

Data, OE Hold Time

Write Pulse Width High

ns

t_WPH

30

ns

AC Byte/Word Load Waveforms

WE Controlled

CE Controlled

21

1427L–FLASH–02/03

Program Cycle Characteristics

Symbol

Parameter

Min

Typ

20

Max

200

100

Units

µs

t_BP

Byte/Word Programming Time (V_IHPP< V_PP< 4.5V)

Byte/Word Programming Time (V_PP> 4.5V)

Address Setup Time

t_BPVPP

t_AS

10

µs

0

40

30

0

ns

t_AH

Address Hold Time

ns

t_DS

Data Setup Time

ns

t_DH

Data Hold Time

ns

t_WP

Write Pulse Width

40

30

70

500

50

ns

t_WPH

t_WC

Write Pulse Width High

ns

Write Cycle Time

ns

t_RP

Reset Pulse Width

ns

t_RH

Reset High Time before Read

Chip Erase Cycle Time (V_PP< 4.5V)

Chip Erase Cycle Time (V_PP> 4.5V)

Sector Erase Cycle Time

Erase or Program Suspend Time

ns

t_EC

12

6

seconds

ms

t_ECVPP

t_SEC

t_EPS

300

400

15

µs

Program Cycle Waveforms

PROGRAM CYCLE

OE

CE

t

WP

BP

WPH

WE

t

DH

AS

AH

555

t

AAA

555

ADDRESS

555

A0 -A19

DATA

WC

t

DS

INPUT

DATA

AA

55

A0

AA

Sector or Chip Erase Cycle Waveforms

(1)

OE

CE

t

WP

WPH

WE

A0-A19

DATA

t

DH

AS

AH

555

t

AAA

555

AAA

Note

2

WC

t

EC

DS

AA

WORD

55

WORD

80

WORD

AA

WORD

55

WORD

Note 3

0

1

2

3

4

WORD 5

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.

(See note 3 under Command Definitions.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

22

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

Data Polling Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

Write Recovery Time

ns

t_WR

0

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in “AC Read Characteristics” on page 19.

Data Polling Waveforms

Toggle Bit Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

t_OEHP

t_WR

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

OE High Pulse

ns

50

0

ns

Write Recovery Time

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in “AC Read Characteristics” on page 19.

Toggle Bit Waveforms^(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

The t_OEHPspecification must be met by the toggling input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

23

1427L–FLASH–02/03

Sector Lockdown Enable Algorithm⁽¹⁾

Software Product Identification

Entry⁽¹⁾

LOAD DATA AA

TO

LOAD DATA AA

TO

ADDRESS 555

LOAD DATA 55

TO

LOAD DATA 55

TO

ADDRESS AAA

LOAD DATA 80

TO

LOAD DATA 90

TO

ADDRESS 555

LOAD DATA AA

TO

ENTER PRODUCT

IDENTIFICATION

ADDRESS 555

(2)(3)(5)

MODE

LOAD DATA 55

TO

Software Product Identification

ADDRESS AAA

Exit⁽¹⁾⁽⁶⁾

OR

LOAD DATA AA

TO

LOAD DATA F0

TO

LOAD DATA 60

TO

ADDRESS 555

ANY ADDRESS

SECTOR ADDRESS

EXIT PRODUCT

IDENTIFICATION

LOAD DATA 55

TO

(4)

MODE

ADDRESS AAA

(2)

PAUSE 200 µs

LOAD DATA F0

TO

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), A-1, and A11 - A19

(Don’t Care).

ADDRESS 555

2. Sector Lockdown feature enabled.

EXIT PRODUCT

IDENTIFICATION

(4)

MODE

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), A-1, and A11 - A19

(Don’t Care).

2. A1 - A19 = V_IL. Manufacturer Code is read for A0 = V_IL;

Device Code is read for A0 = V_IH. Additional Device Code

is read for address 0003H

3. The device does not remain in identification mode if pow-

ered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH(x8); 001FH(x16)

Device Code: C0H (x8) - AT49BV/LV16X;

00C0H (x16) - AT49BV/LV16X;

C2H (x8) - AT49BV/LV16XT;

00C2H (x16) - AT49BV/LV16XT.

Additional Device Code: 08H (x8) - AT49BV/LV16X(T)

0008H (x16) - AT49BV/LV16X(T)

6. Either one of the Product ID Exit commands can be used.

24

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

AT49BV160(T)/161(T) Ordering Information

I_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

70

25

0.01

AT49BV160-70CI

AT49BV160-70TI

45C1

48T

Industrial

(-40° to 85°C)

90

70

90

70

90

70

90

25

0.01

AT49BV160-90CI

AT49BV160-90TI

45C1

48T

Industrial

(-40° to 85°C)

AT49BV160T-70CI

AT49BV160T-70TI

45C1

48T

Industrial

(-40° to 85°C)

AT49BV160T-90CI

AT49BV160T-90TI

45C1

48T

Industrial

(-40° to 85°C)

AT49BV161-70CI

AT49BV161-70TI

48C5

48T

Industrial

(-40° to 85°C)

AT49BV161-90CI

AT49BV161-90TI

48C5

48T

Industrial

(-40° to 85°C)

AT49BV161T-70CI

AT49BV161T-70TI

48C5

48T

Industrial

(-40° to 85°C)

AT49BV161T-90CI

AT49BV161T-90TI

48C5

48T

Industrial

(-40° to 85°C)

AT49LV160(T)/161(T) Ordering Information

I_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

90

25

0.01

AT49LV160-90TI

48T

Industrial

(-40° to 85°C)

70

25

0.01

AT49LV161-70CI

AT49LV161-70TI

48C5

48T

Industrial

(-40° to 85°C)

AT49LV161T-70CI

AT49LV161T-70TI

48C5

48T

Industrial

(-40° to 85°C)

Package Type

45C1

48C5

48T

45-ball, Plastic Chip-size Ball Grid Array Package (CBGA)

48-ball, Plastic Chip-size Ball Grid Array Package (CBGA)

48-lead, Plastic Thin Small Outline Package (TSOP)

25

1427L–FLASH–02/03

Packaging Information

45C1 – CBGA

Dimensions in Millimeters and (Inches).

Controlling dimension: millimeters.

6.60 (0.260)

6.40 (0.252)

A1 ID

7.60 (0.299)

7.40 (0.291)

0.15 (0.006)MIN

1.20 (0.047) MAX

1

5.25 (0.207)

0.625 (0.025) REF

8

7

6

5

4

3

2

1.875(0.074) REF

A

B

C

D

3.75 (0.148)

0.75 (0.0295) BSC

E

F

NON-ACCUMULATIVE

0.30 (0.014)

DIA BALL TYP

0.75 (0.0295) BSC

NON-ACCUMULATIVE

4/11/01

DRAWING NO. REV.

45C1

TITLE

2325 Orchard Parkway

San Jose, CA 95131

45C1, 45-ball (8 x 6 Array), 0.75 mm Pitch, 6.5 x 7.5 x 1.2 mm

Chip-scale Ball Grid Array Package (CBGA)

A

R

26

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

AT49BV/LV160(T)/161(T)

48C5 – CBGA

Dimensions in Millimeters and (Inches).

Controlling dimension: millimeters.

6.10 (0.240)

5.90 (0.232)

A1 ID

8.10 (0.319)

7.90 (0.311)

0.25 (0.010)MIN

1.20 (0.047) MAX

TOP VIEW

SIDE VIEW

1.00(0.039) REF

4.00(0.157)

6

5

4

3

2

1

1.20 (0.047) REF

A

B

C

D

E

F

0.80 (0.0315) BSC

NON-ACCUMULATIVE

5.60 (0.220)

G

H

0.80 (0.0315) BSC

0.40 (0.016)

NON-ACCUMULATIVE

DIA BALL TYP

BOTTOM VIEW

10/18/01

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

48C5, 48-ball (6 x 8 Array), 0.80 mm Pitch, 6 x 8 x 1.2 mm

Chip-scale Ball Grid Array Package (CBGA)

48C5

A

R

27

1427L–FLASH–02/03

48T – TSOP

PIN 1

0º ~ 8º

c

Pin 1 Identifier

D1

D

L

b

L1

e

A2

E

GAGE PLANE

A

SEATING PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

A1

MIN

–

MAX

1.20

0.15

1.05

20.20

NOM

–

NOTE

SYMBOL

A

A1

A2

D

0.05

0.95

19.80

18.30

11.90

0.50

–

1.00

Notes:

1. This package conforms to JEDEC reference MO-142, Variation DD.

2. Dimensions D1 and E do not include mold protrusion. Allowable

protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

20.00

18.40

12.00

0.60

D1

E

18.50 Note 2

12.10 Note 2

0.70

L

L1

b

0.25 BASIC

0.22

0.17

0.10

0.27

0.21

c

–

e

0.50 BASIC

10/18/01

DRAWING NO. REV.

48T

TITLE

2325 Orchard Parkway

San Jose, CA 95131

48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline

Package, Type I (TSOP)

B

R

28

AT49BV/LV160(T)/161(T)

1427L–FLASH–02/03

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

TEL (41) 26-426-5555

FAX (41) 26-426-5500

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

TEL (33) 2-40-18-18-18

FAX (33) 2-40-18-19-60

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

BP 123

38521 Saint-Egreve Cedex, France

TEL (33) 4-76-58-30-00

FAX (33) 4-76-58-34-80

ASIC/ASSP/Smart Cards

Zone Industrielle

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

13106 Rousset Cedex, France

TEL (33) 4-42-53-60-00

FAX (33) 4-42-53-60-01

Japan

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

FAX 1(719) 540-1759

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

TEL (44) 1355-803-000

FAX (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®is the registered trademark of Atmel.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

1427L–FLASH–02/03

/xM


型号：	AT49BV161-70CI
厂家：	ATMEL
描述：	16-megabit (1M x 16/2M x 8) 3-volt Only Flash Memory 16兆位（ 1M ×16 / 2M ×8 ）的3伏只快闪记忆体
文件：	总29页 (文件大小：308K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT49BV161-70CI [ATMEL]

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