AT43301-AC [ATMEL]
Low-cost USB Hub Controller; 低成本的USB集线器控制器
| 型号： | AT43301-AC |
| 厂家： | 
ATMEL |
| 描述： | Low-cost USB Hub Controller |
| 文件： | 总27页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Full Compliance with USB Spec Rev 1.1
• Four Downstream Ports
• Full-speed and Low-speed Data Transfers
• Bus-powered Controller
• Bus-powered or Self-powered Hub Operation
• Port Overcurrent Monitoring
• Port Power Switching
• 5V Operation with On-chip 3.3V Regulator
• 24-lead SOIC and 32-lead LQFP
Low-cost USB
Hub Controller
1. Description
The AT43301 is a 5-port USB hub chip supporting one upstream and four down-
stream ports. The AT43301 connects to an upstream hub or host/root hub via Port0,
while the other ports connect to external downstream USB devices. The hub re-trans-
mits the USB differential signal between Port0 and Ports[1:4] in both directions. The
AT43301 is designed for very low-cost bus-powered or self-powered hub applications
and is available in a 24-lead SOIC and a 32-lead LQFP packages. The 32-lead ver-
sion of the AT43301, the AT43301-AC, has a 48 MHz clock input.
AT43301
The AT43301 supports the 12 Mb/s full speed as well as 1.5 Mb/s slow speed USB
transactions. To reduce EMI, the AT43301’s oscillator frequency is 6 MHz even
though some internal circuitry operates at 48 MHz.
Figure 1-1. Pin Configurations
32-lead LQFP Top View
24-lead SOIC Top View
AT43301-SC
VCC
VSS
1
24
23
22
21
20
19
18
17
16
15
14
13
NC
2
DP4
DM4
DP3
DM3
DP2
DM2
DP1
DM1
DP0
DM0
VSS
CEXT1
OSC1
OSC2
LFT
3
NC
DM4
DP4
1
2
3
4
5
6
7
8
24 NC
23 DP0
4
22 DM0
5
48
21 VSS
AT43301-AC
6
VCC
VSS
CEXT1
NC
20 NC
STAT
7
19 SELF/BUS
18 TEST
17 LPSTAT
PWR
8
OVC
9
LPSTAT
TEST
10
11
12
SELF/BUS
1137J–USB–01/06
The AT43301 consists of a Serial Interface Engine, a Hub Repeater, and a Hub Controller.
The Serial Interface Engine’s tasks are:
• Manage the USB communication protocol
• USB signaling detection/generation
• Clock/data separation, data encoding/decoding, CRC generation/checking
• Data serialization/deserialization
The Hub Repeater is responsible for:
• Providing upstream connectivity between the selected device and the host
• Managing connectivity setup and tear-down
• Handling bus fault detection and recovery
• Detecting connect/disconnect on each port
The Hub Controller is responsible for:
• Hub enumeration
• Providing configuration information to the Host
• Providing status of each port to the Host
• Controlling each port per host command
• Managing port power supply
1.1
Block Diagram
Figure 1-2. AT43301 Block Diagram
UPSTREAM PORT
PORT 0
SERIAL
HUB
CONTROLLER
HUB
REPEATER
INTERFACE
ENGINE
ENDPOINT 0
ENDPOINT 1
PORT 3
PORT 4
PORT 1
PORT 2
TO DOWNSTREAM DEVICES
Note:
This document assumes that the reader is familiar with the Universal Serial Bus and therefore only
describes the unique features of the AT43301 controller. For detailed information about the USB
and its operation, the reader should refer to the Universal Serial Bus Specification Version 1.1,
September 23, 1998.
2
AT43301
1137J–USB–01/06
AT43301
1.2
Pin Assignment
Type:
= Input,
IS = Input, Schmitt Trigger
= Output
OD = Output, open drain
I
O
B
V
= Bi-directional
= Power supply, ground
Table 1-1.
24-lead SOIC AT43301-SC Pin Assignment
Pin Number
Signal
VCC
Type
V
V
O
I
1
2
VSS
3
CEXT1
OSC1
OSC2
LFT
4
5
O
I
6
7
STAT
PWR
OVC
O
O
IS
IS
I
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LPSTAT
TEST
SELF/BUS
VSS
IS
V
B
B
B
B
B
B
B
B
B
B
-
DM0
DP0
DM1
DP1
DM2
DP2
DM3
DP3
DM4
DP4
NC
3
1137J–USB–01/06
Table 1-2.
32-lead AT43301-AC Pin Assignment
Pin Number
Signal
NC
Type
–
1
2
DM4
DP4
48
B
B
I
3
4
5
VCC
VSS
CEXT
NC
V
V
O
–
6
7
8
9
VSS
OSC1
OSC2
LFT
V
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
O
I
STAT
PWR
NC
O
O
–
OVC
LPSTAT
TEST
SELF/BUS
NC
IS
IS
I
IS
–
VSS
DM0
DP0
NC
V
B
B
–
NC
–
DM1
DP1
DM2
DP2
DM3
DP3
NC
B
B
B
B
B
B
–
4
AT43301
1137J–USB–01/06
AT43301
Table 1-3.
Signal Descriptions
External Capacitor. For proper operation of the on-chip regulator, a 0.27 µF capacitor must be connected to
CEXT1.
CEXT1
O
Upstream Plus USB I/O. This pin should be connected to the CEXT1 pin through an external 1.5 kΩ pull-up
resistor. DP0 and DM0 form the differential signal pin pairs connected to the USB host controller or an
upstream Hub.
DP0
B
DM0
B
B
B
I
Upstream Minus USB I/O.
Port Plus USB I/O. This pin should be connected to VSS through an external 15 kΩ resistor. DP[1:4] and DM[1:4]
are the differential signal pin pairs to connect downstream USB devices.
DP[1:4]
DM[1:4]
LFT
Port Minus USB I/O. This pin should be connected to VSS through an external 15 kΩ resistor.
PLL Filter. For proper operation of the PLL, this pin should be connected through a 2.2 nF capacitor in parallel
with a 100Ω resistor in series with a 10 nF capacitor to ground (VSS).
Local Power Status. Schmitt Trigger input pin that is used in the self-powered mode to indicate the condition of the
local power supply. This pin should be connected to the local power supply through a 100 kΩ resistor.
LPSTAT
48
I
I
48 MHz Select, 32-lead LQFP only. This pin sets the clock input to the AT43301-AC. If it is tied low, a 48 MHz
clock must be input to OSC1. If it is tied high (to CEXT1 or to 5V through a 47 kΩ resistor), a 6 MHz crystal must
be connected between OSC1 and OSC2, or a 6 MHz clock input to OSC1.
OSC1
OSC2
I
Oscillator Input. Input to the inverting 6 MHz oscillator amplifier.
Oscillator Output. Output of the inverting oscillator amplifier.
O
Port Overcurrent. This is the Schmitt Trigger input signal used to indicate to the AT43301 that there is a power
supply problem with the ports. If OVC is asserted, the AT43301 will de-assert PWR and report the status to the
USB Host.
OVC
I
Power Switch. This is an output signal to enable or disable the external port power switch for the port power
supply. PWR is de-asserted when an overcurrent is detected at OVC.
PWR
O
I
Power Mode. Schmitt Trigger input pin to set power mode of hub. If high, the AT43301 works in the self-powered
mode. If low, the bus-powered mode.
SELF/BUS
Status. Output pin which is asserted by the AT43301 whenever it is enumerated. STAT is de-asserted when the
hub enters the suspend state. An LED in series with a resistor can be connected to this pin to provide visual
feedback to the user.
STAT
O
TEST
VCC
VSS
NC
I
Test. This pin has an internal pull up and should be left unconnected in the normal operating mode.
V
V
-
5V Power Supply from the USB.
Ground.
No Connect. This pin should be left unconnected.
5
1137J–USB–01/06
2. Functional Description
2.1
Summary
The Atmel AT43301 USB hub controller chip contains various features that makes it the ideal
solution for very low-cost USB hubs. These features are: on-chip regulator, low-frequency oscil-
lator, bus or self-powered operation, ganged port power switching and global overcurrent
protection. Such a hub can be a stand-alone hub used with portable computers to allow conve-
nient connectivity to standard desktop peripheral devices. Alternatively, the hub can be added to
an existing non-USB peripheral such a keyboard. The AT43301 provides 4 downstream USB
ports and can operate in a self-powered or bus-powered mode.
2.2
2.3
USB Ports
The AT43301’s upstream port, Port0, is a full speed port. A 1.5 kΩ pull-up resistor to the 3.3V
regulator output, CEXT, is required for proper operation. The downstream ports support both
full-speed as well as low-speed devices. 15 kΩ pull down resistors are required at their inputs.
Full speed signal requirements demand controlled rise/fall times and impedance matching of the
USB ports. To meet these requirements, 22Ω resistors must be inserted in series between the
USB data pins and the USB connectors.
Hub Repeater
The Hub Repeater is responsible for port connectivity setup and teardown. It also supports
exception handling such as bus fault detection and recovery, and connect/disconnect detection.
Port0 is the root port and is connected to the root hub or an upstream hub. When a packet is
received at Port0, the AT43301 propagates it to all the enabled downstream ports. Conversely, a
packet from a downstream port is transmitted from Port0.
The AT43301 supports downstream port data signaling at both 1.5 Mb/s and 12 Mb/s. Devices
attached to the downstream ports are determined to be either full speed or low speed depending
which data line (DP or DM) is pulled high. If a port is enumerated as low speed, its output buffers
operate at a slew rate of 75-300 ns, and the AT43301 will not propagate any traffic to that port
unless it is prefaced with a preamble PID. Low speed data following the preamble PID is propa-
gated to both low- and full-speed devices. The AT43301 will enable low-speed drivers within four
full-speed bit times of the last bit of a preamble PID, and will disable them at the end of an EOP.
The upstream traffic from all ports is propagated by Port0 using the full speed 4-20ns slew rate
drivers.
All the AT43301 ports independently drive and monitor their DP and DM pins so that they are
able to detect and generate the ‘J’, ‘K’, and SE0 bus signaling states. Each hub port has single-
ended and differential receivers on its DP and DM lines. The ports’ I/O buffers comply with the
voltage levels and drive requirements as specified in the USB Specifications Rev 1.0.
The Hub Repeater implements a frame timer which is timed by the 12 MHz USB clock and gets
reset every time an SOF token is received from the host.
2.4
Serial Interface Engine
The Serial Interface Engine handles the USB communication protocol. It performs the USB
clock/data separation, the NRZI data encoding/decoding, bit stuffing, CRC generation and
checking, USB packet ID decoding and generation, and data serialization and de-serialization.
6
AT43301
1137J–USB–01/06
AT43301
The on-chip phase locked loop generates the high frequency clock for the clock/data separation
circuit.
2.5
Power Management
A hub is allowed to draw up to 500 mA of power from the host or upstream hub. The AT43301’s
itself and its external circuitry typically consume about 24 mA. Therefore, in the bus-powered
mode, 100 mA is available for each of the hub’s downstream devices. In the self-powered mode,
an external power supply is required which must be capable of supplying 500 mA per port. The
power supplied to the ports is monitored and controlled by the AT43301.
The AT43301 reports overcurrent on a global basis. The overcurrent signal, which needs to be
detected by an external device, is read through the OVC pin. A logic low at OVC is interpreted as
an overcurrent condition. This could be caused by an overload, or a short circuit, and causes the
AT43301 to set the Over-Current Indicator bit of the Hub Status Field, wHubStatus, as well as
the Over-Current Indicator Change bit of the Hub Change Field, wHubChange. At the same
time, power to the ports is switched off by de-asserting PWR.
An external device is needed to perform the actual switching of the ports’ power under control of
the AT43301. Any type of suitable switch or device is acceptable. However, the switch should
have a low-voltage drop across it even when the port absorbs full power. In its simplest form, this
switch can be a high side MOSFET switch. The advantage of using a MOSFET switch is its very
low-voltage drop.
The power control pin, PWR, is asserted only when a SetPortFeature[PORT-POWER] request is
received from the host. PWR is de-asserted under the following conditions:
1. Power up
2. Reset and initialization
3. Overcurrent condition
4. Requested by the host though a ClearPortFeature[PORT_POWER] for ALL the ports
2.5.1
Self-powered Mode
In the self-powered mode, power to the downstream ports must be supplied by an external
power supply. This power supply must be capable of supplying 500 mA per port or 2A total with
good voltage tolerance and regulation. At full hub operating power, that is all downstream ports
drawing 500 mA each, the minimum voltage at the downstream port connector must be 4.75V.
The USB specification requires that the voltage drop at the power switch and board traces be no
more than 100 mV. A good conservative maximum drop at the power switch itself should be no
more than 75 mV. Careful design and selection of the power switch and PC board layout is
required to meet the specifications. When using a MOSFET switch, its resistance must be 40
mΩ or less under worst case conditions. A suitable MOSFET switch for an AT43301 based hub
is an integrated highside MOSFET switch such as the Micrel MIC2505.
2.5.2
Bus-Powered Mode
In the bus-powered mode all the power for the hub itself as well as the downstream ports is sup-
plied by the root hub or upstream hub through the USB. Only 100 mA is available for each of the
hub’s downstream devices and therefore only low-power devices are supported.
The power switch works exactly like the self-powered mode, except that the allowable switch
resistance is higher: 140 mΩ or less under the worst case condition. An example of a suitable
high side switch for a bus-powered hub is the Micrel MIC2525.
7
1137J–USB–01/06
The diagrams of Figure 2-1 and Figure 2-2 show examples of the power supply and power man-
agement scheme in the self-powered mode and bus-powered mode using an integrated switch
with built-in overcurrent protection.
Figure 2-1. Bus-powered Hub
BUS_POWER
GND
U1
GND
VCC
OVC
FLG
AT43301
PORT_POWER
GND
PWR
PORT_POWER
GND
U2
CTL
IN
TO
DOWNSTREAM
DEVICES
PORT_POWER
GND
OUT
SWITCH
PORT_POWER
GND
Figure 2-2. Self-powered Hub
BUS_POWER
GND
U1
GND
VCC
OVC
FLG
AT43301
PORT_POWER
GND
PWR
PORT_POWER
GND
PS5
U2
CTL
IN
TO
POWER SUPPLY
DOWNSTREAM
DEVICES
PORT_POWER
GND
5V OUT
GND
OUT
SWITCH
PORT_POWER
GND
8
AT43301
1137J–USB–01/06
AT43301
2.6
Hub Controller
The Hub Controller of the AT43301 provides the mechanism for the host to enumerate the hub
and the AT43301 to provide the host with its configuration information. It also provides a mecha-
nism for the host to monitor and control the downstream ports.
The Hub Controller supports two endpoints, Endpoint0 and Endpoint1.
The Hub Controller maintains a status register, Controller Status Register, which reflects the
AT43301's current settings. At power up, all bits in this register will be set to 0’s.
Table 2-1.
Controller Status Register
Bit Function
Value
Description
Set to 0 or 1 by a Set_Configuration Request
Hub is not currently configured
0
1
Hub configuration status
0
1
Hub is currently configured
Set to 0 or 1 by ClearFeature or SetFeature request.
Default value is 0.
Hub remote wakeup status
0
1
Hub is currently not enabled to request remote wakeup
Hub is currently enabled to request remote wakeup
0
1
Endpoint0 is not stalled
Endpoint0 is stalled
2
3
Endpoint0 STALL status
Endpoint1 STALL status
0
1
Endpoint1 is not stalled
Endpoint1 is stalled
2.6.1
Endpoint 0
Endpoint 0 is the AT43301’s default endpoint used for enumeration of the hub and exchange of
configuration information and requests between the host and the AT43301. Endpoint 0 supports
control transfers.
The Hub Controller supports the following descriptors through Endpoint 0: Device Descriptor,
Configuration Descriptor, Interface Descriptor, Endpoint Descriptor, and Hub Descriptor. These
descriptors are described in detail elsewhere in this document. Standard USB Device Requests
and class-specific Hub Requests are also supported through Endpoint 0. There is no endpoint
descriptor for Endpoint0.
2.6.2
Endpoint 1
Endpoint1 is used by the Hub Controller to send status change information to the host. This end-
point supports interrupt transfers.
The Hub Controller samples the changes at the end of every frame at time marker EOF2 in prep-
aration for a potential data transfer in the subsequent frame. The sampled information is stored
in a byte wide register, the Status Change Register, using a bitmap scheme.
9
1137J–USB–01/06
Each bit in the Status Change Register corresponds to one port as shown below:
Table 2-2.
Bit
Status Change Register
Function
Value
Meaning
0
1
No change in status
0
1
2
3
Hub status change
Port1 status change
Port2 status change
Port3 status change
Change in status detected
0
1
No change in status
Change in status detected
0
1
No change in status
Change in status detected
0
1
No change in status
Change in status detected
0
1
No change in status
4
Port4 status change
Reserved
Change in status detected
5-7
000
Default values
An IN Token packet from the host to Endpoint 1 indicates a request for port change status. If the
hub has not detected any change on its ports, or any changes in itself, then all bits in this regis-
ter will be 0 and the Hub Controller will return a NAK to requests on Endpoint1. If any of bits 0-4
is 1, the Hub Controller will transfer the whole byte. The Hub Controller will continue to report a
status change when polled until that particular change has been removed by a ClearPortFeature
request from the Host. No status change will be reported by Endpoint 1 until the AT43301 has
been enumerated and configured by the host.
2.7
Oscillator and Phase-Locked-Loop
All the clock signals required to run the AT43301 are derived from an on-chip oscillator. To
reduce EMI and power dissipation in the system, the AT43301 is designed to operate with a 6
MHz crystal. An on-chip PLL generates the high frequency for the clock/data separator of the
Serial Interface Engine. In the suspended state, the oscillator circuitry is turned off. To assure
quick startup, a crystal with a high Q, or low ESR, should be used. To meet the USB hub fre-
quency accuracy and stability requirements for hubs, the crystal should have an accuracy and
stability of better than 100 ppm. Even though the oscillator circuit would work with a ceramic res-
onator, its use is not recommended because a resonator would not have the frequency accuracy
and stability.
A 6 MHz parallel resonance quartz crystal with a load capacitance of approximately 10 pF is rec-
ommended. The oscillator is a special low-power design and in most cases no external
capacitors and resistors are necessary. If the crystal requires a higher value capacitance, exter-
nal capacitors can be added to the two terminals of the crystal and ground to meet the required
value. If the crystal used cannot tolerate the drive levels of the oscillator, a series resistor
between OSC2 and the crystal pin is recommended.
The clock can also be externally sourced. In this case, connect the clock source to the OSC1
pin, while leaving OSC2 pin floating. The switching level at the OSC1 pin can be as low as 0.47V
(see “Electrical Specification” on page 12) and a CMOS device is required to drive this pin to
maintain good noise margins at the low switching level. The 32-lead AT43301-AC can also be
driven by a 48 MHz external clock instead. In this case, connect the 48N pin to ground.
10
AT43301
1137J–USB–01/06
AT43301
For proper operation of the PLL, an external RC filter consisting of a series RC network of 100Ω
and 10 nF in parallel with a 2 nF capacitor must be connected from the LFT pin to VSS.
2.8
Status Pin
The status pin, STAT, is provided to allow feedback to the user. If an LED and a series resistor is
connected between STAT and VCC, the LED will light when the hub is enumerated. During an
overcurrent condition, the LED will blink. It will continue to blink until the host turns off the power
to the ports or until the hub is re-enumerated.
The I/O pins of the AT43301 should not be directly connected to voltages less than VSS or more
than the voltage at the CEXT pins. If it is necessary to violate this rule, insert a series resistor
between the I/O pin and the source of the external signal source that limits the current into the
I/O pin to less than 0.2 mA. Under no circumstance should the external voltage exceed 5.5V. To
do so will put the chip under excessive stress.
Figure 2-3. External Oscillator and PLL Circuit
U1
OSC1
Y1
6.000 MHz
OSC2 AT43301
R1
100
LFT
C1
C2
10nF
2nF
2.9
Power Supply
The AT43301 is powered from the USB bus, but has an internal voltage regulator to supply the
3.3V operating power to its circuitry. For proper operation, an external high quality, low ESR,
0.27 µF, or larger, capacitor should be connected to the output of the regulator, CEXT1 and
ground. The CEXT1 pin can also be used to supply the voltage to the 1.5 kΩ pull up resistor at
Port 0’s DP pin.
To provide the best operating condition for the AT43301, careful consideration of the power sup-
ply connections are recommended. Use short, low impedance connections to all power supply
lines: VCC and VSS. Use sufficient decoupling capacitance to reduce noise: 0.1 µF of high quality
ceramic capacitor soldered as close as possible to the VCC and VSS package pins are
recommended.
The AT43301 can also operate directly off a 3.3V power supply. In this case, leave the VCC pin
floating and connect the 3.3V power to CEXT1.
11
1137J–USB–01/06
3. Electrical Specification
3.1
Absolute Maximum Ratings*
Symbol
VCC5
Parameter
Condition
Min
Max
Unit
5V Power Supply
5.5
V
V
CEXT + 0.3
4.6 max
VI
DC Input Voltage
-0.3V
-0.3
V
V
VCEXT + 0.3
4.6 max
VO
TO
DC Output Voltage
Operating Temperature
Storage Temperature
-40
-65
+125
°C
°C
TS
+150
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
3.2
DC Characteristics
The values shown in this table are valid for TA = 0°C to 85°C, VCC = 4.4V to 5.25V, unless otherwise noted.
Table 3-1.
Symbol
VCC
Power Supply
Parameter
Condition
Min
Max
5.25
24
Unit
V
5V Power Supply
5V Supply Current
Suspended Device Current
4.4
ICC
mA
µA
ICCS
150
Table 3-2.
Symbol
VIH
USB Signals: DPx, DMx
Parameter
Condition
Min
2.0
2.7
Max
Unit
V
Input Level High (driven)
Input Level High (floating)
Input Level Low
VIHZ
3.6
0.8
V
VIL
V
VDI
Differential Input Sensitivity
Differential Common Mode Range
Static Output Low
DPx and DMx
0.2
0.8
V
VCM
2.5
0.3
3.6
2.0
20
V
VOL1
RL of 1.5 kΩ to 3.6V
RL of 15 kΩ to GND
V
VOH1
VCRS
CIN
Static Output High
2.8
1.3
V
Output Signal Crossover
Input Capacitance
V
pF
12
AT43301
1137J–USB–01/06
AT43301
Table 3-3.
Symbol
VOL2
PWR, STAT, OVC
Parameter
Condition
IOL = 4 mA
1 MHz
Min
Max
0.5
Unit
V
Output Low Level, PWR, STAT
Output Capacitance
Input Low Level
COUT
10
pF
V
VIL3
0.3VCEXT
VIH3
Input High Level
0.7VCEXT
V
COUT
Output Capacitance
Output High Level, PWR
1 MHz
10
pF
V
VOH2
IOH = 4 mA
VCEXT - 0.5
Table 3-4.
Symbol
VLH
Oscillator Signals: OSC1, OSC2
Parameter
Condition
Min
0.47
0.67
Max
1.20
1.44
17
Unit
V
OSC1 Switching Level
OSC1 Switching Level
Input Capacitance, OSC1
Output Capacitance, OSC2
OSC1/2 Capacitance
Start-up Time
VHL
V
CX1
pF
pF
pF
ms
µW
CX2
17
C12
1
tsu
6 MHz, fundamental
2
DL
Drive Level
VCC = 3.3V, 6 MHz crystal, 100Ω equiv series resistor
150
Note:
OSC2 must not be used to drive other circuitry.
3.3
AC Characteristics
Table 3-5.
DPx, DMx Driver Characteristics, Full Speed Operation
Symbol
tR
Parameter
Condition
CL = 50 pF
CL = 50 pF
Min
4
Max
20
Unit
ns
ns
%
Rise Time
tF
Fall Time
4
20
tRFM
ZDRV
Note:
tR/tF Matching
Driver Output Resistance(1)
90
28
110
44
Steady state drive
Ω
1. With external 22Ω series resistor.
13
1137J–USB–01/06
Table 3-6.
Symbol
tDRATE
DPx, DMx Source Timings, Full Speed Operation
Parameter
Condition
Min
Max
12.03
1.0005
42.0
Unit
Mb/s
ms
Full Speed Data Rate(1)
Average bit rate
11.97
0.9995
tFRAME
Frame Interval(1)
tRFI
Consecutive Frame Interval Jitter(1)
Consecutive Frame Interval Jitter(1)
No clock adjustment
With clock adjustment
ns
tRFIADJ
126.0
ns
Source Diff Driver Jitter
To Next Transition
tDJ1
tDJ2
-3.5
-4.0
3.5
4.0
ns
ns
For Paired Transitions
tFDEOP
Source Jitter for Differential Transition to SEO Transitions
-2.0
5.0
ns
Recvr Data Jitter Tolerance
To Next Transition
tJR1
tJR2
-18.5
-9.0
18.5
9.0
ns
ns
For Paired Transitions
tFEOPT
tFEOPR
tFST
Source SEO interval of EOP
160.0
82.0
175.0
ns
ns
ns
Receiver SEO interval of EOP
Width of SEO interval during differential transition
14.0
Note:
1. With 6.000 MHz, 100 ppm crystal.
Table 3-7.
DPx, DMx Driver Characteristics, Low-speed Operation
Symbol
Parameter
Rise time
Condition
Min
75.0
75.0
80.0
Max
300.0
300.0
125.0
Unit
ns
tR
CL = 200 - 600 pF
CL = 200 - 600 pF
tF
Fall time
ns
tRFM
tR/tF matching
%
Table 3-8.
Symbol
tHDD2
DPx, DMx Hub Timings, High-Speed Operation
Parameter
Condition
Min
Max
Unit
Hub Differential Data Delay without Cable
44.0
ns
Hub Diff Driver Jitter
To Next Transition
tHDJ1
tHDJ2
-3.0
-1.0
3.0
1.0
ns
ns
For Paired Transitions
tFSOP
Data Bit Width Distortion after SOP
Hub EOP Delay Relative to tHDD
Hub EOP Output Width Skew
-5.0
0
5.0
ns
ns
ns
tFEOPD
tFHESK
15.0
15.0
-15.0
14
AT43301
1137J–USB–01/06
AT43301
Table 3-9.
DPx, DMx Hub Timings, Low-speed Operation
Symbol Parameter
Condition
Min
Max
Unit
tLHDD
Hub Differential Data Delay
300.0
ns
Downstr Hub Diff Driver Jitter
To Next Transition, downst
For Paired Transitions, downst
To Next Transition, upstr
tLHDJ1
tLHDJ2
tLUHJ1
tLUHJ2
-45.0
-15.0
-45.0
-45.0
45.0
15.0
45.0
45.0
ns
ns
ns
ns
For Paired Transitions, upstr
tSOP
Data Bit Width Distortion after SOP
Hub EOP Delay Relative to tHDD
Hub EOP Output Width Skew
-60.0
0
60.0
200.0
300.0
ns
ns
ns
tLEOPD
tLHESK
-300.0
Table 3-10. Hub Event Timings
Symbol Parameter
Condition
Min
Max
Unit
Time to Detect a Downstream Port Connect Event
Awake Hub
tDCNN
2.5
2.5
2000.0
µs
µs
Suspended Hub
12000.0
Time to Detect a Disconnect Event on Downstream Port
tDDIS
Awake Hub
2.5
2.5
2.5
µs
µs
Suspended Hub
10000.0
Time from Detecting Downstream Resume to
Rebroadcast
tURSM
tDRST
100.0
20.0
µs
Only for a SetPortFeature
(PORT_RESET) request
Duration of Driving Reset to a Downstream Device
10.0
ms
tURLK
Time to Detect a Long K from Upstream
Time to Detect a Long SEO from Upstream
2.5
2.5
100.0
µs
µs
tURLSEO
10000.0
FS bit
time
tURPSEO
Duration of repeating SEO Upstream
23
15
1137J–USB–01/06
4. Timing Waveforms
Figure 4-1. Data Signal Rise and Fall Time
RISE TIME
90%
FALL TIME
10%
VCRS
90%
10%
DIFFERENTIAL
DATA LINES
tF
tR
Figure 4-2. Full-speed Load
RS
TxD+
CL
RS
TxD-
CL
CL = 50pF
Figure 4-3. Low-speed Downstream Port Load
RS
TxD+
CL
3.6V
RS
1.5KΩ
TxD-
CL
CL = 200pF to 600pF
Figure 4-4. Differential Data Jitter
TPERIOD
CROSSOVER
DIFFERENTIAL
DATA LINES
POINTS
CONSECUTIVE
TRANSITIONS
N*TPERIOD+TXJR1
PAIRED
TRANSITIONS
N*TPERIOD+TXJR2
16
AT43301
1137J–USB–01/06
AT43301
Figure 4-5. Differential-to-EOP Transition Skew and EOP Width
CROSSOVER
POINT
EXTENDED
TPERIOD
DIFFERENTIAL
DATA LINES
DIFF. DATA-to-
SE0 SKEW
N*TPERIOD+TDEOP
SOURCE EOP WIDTH: TFEOPT
TLEOPT
RECEIVER EOP WIDTH: TFEOPR,
TLEOPR
Figure 4-6. Receiver Jitter Tolerance
TPERIOD
DIFFERENTIAL
DATA LINES
TJR
TJR1
TJR2
CONSECUTIVE
TRANSITIONS
N*TPERIOD+TJR1
CONSECUTIVE
TRANSITIONS
N*TPERIOD+TJR1
17
1137J–USB–01/06
Figure 4-7. Hub Differential Delay, Differential Jitter, and SOP Distortion
UPSTREAM
CROSSOVER
POINT
DOWNSTREAM
END OF
CABLE
PORT
50% POINT OF
INITIAL SWING
VSS
VSS
HUB DELAY
DOWNSTREAM
THDD1
DIFFERENTIAL
DATA LINES
HUB DELAY
UPSTREAM
THDD2
CROSSOVER
POINT
CROSSOVER
POINT
UPSTREAM
PORT
VSS
VSS
A. DOWNSTREAM HUB DELAY WITH CABLE
B. UPSTREAM HUB DELAY WITHOUT CABLE
CROSSOVER
POINT
DOWNSTREAM
PORT
VSS
UPSTREAM
PORT OR END
OF CABLE
VSS
HUB DELAY
UPSTREAM
THDD1, THDD2
CROSSOVER
POINT
C. UPSTREAM HUB DELAY WITH OR WITHOUT CABLE
Hub Differential Jitter:
T
T
HDJ1 = THDDX(J) - THDDX(K) or THDDX(K) - THDDX(J) Consecutive Transitions
HDJ2 = THDDX(J) - THDDX(J) or THDDX(K) - THDDX(K) Paired Transitions
Bit After Sop Width Distortion (Same as Data Jitter for Sop and Next J Transition):
SOP = THDDX(NEXTJ) - THDDX(SOP)
Low-speed timings are determined in the same way for:
LHDD, TLDHJ1, TLDJH2, TLUHJ1, TLUJH2, and TLSOP
T
T
18
AT43301
1137J–USB–01/06
AT43301
Figure 4-8. Hub EOP Delay and EOP Skew
50% POINT OF
INITIAL SWING
UPSTREAM
END OF
CROSSOVER
POINT
UPSTREAM
PORT
CABLE
EXTENDED
V
V
SS
SS
T
CROSSOVER
POINT
CROSSOVER
EOP+
DOWNSTREAM
PORT
DOWNSTREAM
PORT
T
T
T
EOP-
EOP+
EOP-
POINT
EXTENDED
EXTENDED
V
SS
V
SS
A. DOWNSTREAM EOP DELAY WITH CABLE
B. DOWNSTREAM EOP DELAY WITHOUT CABLE
DOWNSTREAM
PORT
CROSSOVER
POINT
EXTENDED
V
SS
UPSTREAM
PORT OR END
OF CABLE
CROSSOVER
T
T
EOP+
EOP-
POINT
EXTENDED
V
SS
C. UPSTREAM EOP DELAY WITH OR WITHOUT CABLE
EOP Delay:
TEOPD = TEOP - THDDX
EOP Skew:
T
HESK = TEOP + -TEOP-
Low-speed timings are determined in the same way for:
LEOPD and TLHESK
T
19
1137J–USB–01/06
5. Schematic Diagrams
The following pages show schematic diagrams of an AT43301 based bus-powered hub and self-
powered hub.
Figure 5-1. Bus-powered Hub
1
2
3
4
5
6
7
8
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
V S S
V S S
1 3
2
O V C
9
P W R
8
2
1
O S C
5
4
S
/ B U S E L F
1 2
7
A T S T
O S C
5
6
20
AT43301
1137J–USB–01/06
AT43301
Figure 5-2. Bus-powered Hub
1 0
1 2
1 1
1 0
9
1 2
1 1
9
21
1137J–USB–01/06
Figure 5-3. Self-powered Hub
1
2
3
4
5
6
7
8
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
V S S
V S S
1 3
2
O V C
9
P W R
8
2
1
O S C
5
4
S
/ B U S E L F
1 2
7
A T S T
O S C
5
6
22
AT43301
1137J–USB–01/06
AT43301
Figure 5-4. Self-powered Hub
1 0
1 2
1 1
1 0
1 2
1 1
9
9
23
1137J–USB–01/06
6. Ordering Information
6.1
AT43301 Standard Package Options
Ordering Code
Package
Operation Range
Commercial
AT43301-SC
AT43301-AC
24S – SOIC
(0°C to 70°C)
Commercial
32AA – LQFP
(0°C to 70°C)
6.2
AT43301 Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code
Package
Operation Range
Industrial
AT43301-AU
32AA – LQFP
(-40°C to 85°C)
Industrial
AT43301-SU
24S – SOIC
(-40°C to 85°C)
Package Type
24S
24-lead (0.300 in. body) Plastic Gull Wing Small Outline Package (SOIC)
32-lead, Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP)
32AA
24
AT43301
1137J–USB–01/06
AT43301
7. Packaging Information
7.1
32AA – LQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.60
0.15
1.45
9.25
7.10
9.25
7.10
0.45
0.20
0.75
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
1.35
8.75
6.90
8.75
6.90
0.30
0.09
0.45
1.40
9.00
7.00
9.00
7.00
–
D1
E
Note 2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-026, Variation BBA.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
C
–
3. Lead coplanarity is 0.10 mm maximum.
L
–
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
32AA, 32-lead, 7 x 7 mm Body Size, 1.4 mm Body Thickness,
0.8 mm Lead Pitch, Low Profile Plastic Quad Flat Package (LQFP)
32AA
B
R
25
1137J–USB–01/06
7.2
24S – SOIC
B
D1
D
PIN 1 ID
PIN 1
e
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
2.65
0.30
10.65
7.60
15.60
0.51
1.27
0.32
NOM
NOTE
SYMBOL
A
–
A1
A1
D
0.10
10.00
7.40
15.20
0.33
0.40
0.23
–
–
D1
E
–
0º ~ 8º
–
L1
B
–
L
–
–
L
L1
e
1.27 BSC
06/17/2002
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC)
24S
B
R
26
AT43301
1137J–USB–01/06
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
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Tel: 1(719) 576-3300
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Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
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Fax: (33) 4-76-58-34-80
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Room 1219
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77 Mody Road Tsimshatsui
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