AT40K05-2DQL [ATMEL]
Field Programmable Gate Array, 256 CLBs, 5000 Gates, CMOS, PQFP208, 28 X 28 MM, PLASTIC, QFP-208;
| 型号： | AT40K05-2DQL |
| 厂家： | 
ATMEL |
| 描述： | Field Programmable Gate Array, 256 CLBs, 5000 Gates, CMOS, PQFP208, 28 X 28 MM, PLASTIC, QFP-208 栅 可编程逻辑 |
| 文件： | 总67页 (文件大小：1589K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Ultra High Performance
– System Speeds to 100 MHz
– Array Multipliers > 50 MHz
– 10 ns Flexible SRAM
– Internal Tri-state Capability in Each Cell
• FreeRAM™
– Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM
– 2,048 - 18,432 Bits of Distributed SRAM Independent of Logic Cells
• 128 - 384 PCI Compliant I/Os
– 3V/5V Capability
– Programmable Output Drive
5K - 50K Gates
Coprocessor
FPGA with
– Fast, Flexible Array Access Facilitates Pin Locking
– Pin-compatible with XC4000, XC5200 FPGAs
• 8 Global Clocks
– Fast, Low Skew Clock Distribution
– Programmable Rising/Falling Edge Transitions
– Distributed Clock Shutdown Capability for Low Power Management
– Global Reset/Asynchronous Reset Options
– 4 Additional Dedicated PCI Clocks
FreeRAM™
• Cache Logic® Dynamic Full/Partial Re-configurability In-System
– Unlimited Re-programmability via Serial or Parallel Modes
– Enables Adaptive Designs
AT40K05
– Enables Fast Vector Multiplier Updates
– QuickChange™ Tools for Fast, Easy Design Changes
• Pin-compatible Package Options
AT40K05LV
AT40K10
AT40K10LV
AT40K20
AT40K20LV
AT40K40
– Plastic Leaded Chip Carriers (PLCC)
– Thin, Plastic Quad Flat Packs (LQFP, TQFP, PQFP)
– Ball Grid Arrays (BGAs)
• Industry-standard Design Tools
– Seamless Integration (Libraries, Interface, Full Back-annotation) with
Concept®, Everest, Exemplar™, Mentor®, OrCAD®, Synario™, Synopsys®,
Verilog®, Veribest®, Viewlogic®, Synplicity®
– Timing Driven Placement & Routing
– Automatic/Interactive Multi-chip Partitioning
– Fast, Efficient Synthesis
– Over 75 Automatic Component Generators Create 1000s
of Reusable, Fully Deterministic Logic and RAM Functions
• Intellectual Property Cores
AT40K40LV
– Fir Filters, UARTs, PCI, FFT and Other System Level Functions
• Easy Migration to Atmel Gate Arrays for High Volume Production
• Supply Voltage 5V for AT40K, and 3.3V for AT40KLV
Rev. 0896C–FPGA–04/02
Table 1. AT40K/AT40KLV Family(1)
AT40K05
AT40K10
AT40K20
AT40K40
Device
AT40K05LV
5K - 10K
16 x 16
256
AT40K10LV
AT40K20LV
AT40K40LV
Usable Gates
Rows x Columns
Cells
10K - 20K
24 x 24
576
20K - 30K
32 x 32
1,024
40K - 50K
48 x 48
2,304
Registers
256(1)
576(1)
4,608
192
1,024(1)
2,304(1)
18,432
384
RAM Bits
2,048
8,192
I/O (Maximum)
128
256
Note:
1. Packages with FCK will have 8 less registers.
Description
The AT40K/AT40KLV is a family of fully PCI-compliant, SRAM-based FPGAs with dis-
tributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM,
8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data),
automatic component generators, and range in size from 5,000 to 50,000 usable gates.
I/O counts range from 128 to 384 in industry standard packages ranging from 84-pin
PLCC to 352-ball Square BGA, and support 5V designs for AT40K and 3.3V designs for
AT40KLV.
The AT40K/AT40KLV is designed to quickly implement high-performance, large gate
count designs through the use of synthesis and schematic-based tools used on a PC or
Sun platform. Atmel’s design tools provide seamless integration with industry standard
tools such as Synplicity, ModelSim, Exemplar and Viewlogic.
The AT40K/AT40KLV can be used as a coprocessor for high-speed (DSP/processor-
based) designs by implementing a variety of computation intensive, arithmetic functions.
These include adaptive finite impulse response (FIR) filters, fast Fourier transforms
(FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required
for video compression and decompression, encryption, convolution and other multime-
dia applications.
Fast, Flexible and
Efficient SRAM
The AT40K/AT40KLV FPGA offers a patented distributed 10 ns SRAM capability where
the RAM can be used without losing logic resources. Multiple independent, synchronous
or asynchronous, dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can
be created using Atmel’s macro generator tool.
Fast, Efficient Array and The AT40K/AT40KLV’s patented 8-sided core cell with direct horizontal, vertical and
diagonal cell-to-cell connections implements ultra fast array multipliers without using
Vector Multipliers
any busing resources. The AT40K/AT40KLV’s Cache Logic capability enables a large
number of design coefficients and variables to be implemented in a very small amount
of silicon, enabling vast improvement in system speed at much lower cost than conven-
tional FPGAs.
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AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
Cache Logic Design
The AT40K/AT40KLV, AT6000 and FPSLIC families are capable of implementing
Cache Logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly)
for building adaptive logic and systems. As new logic functions are required, they can be
loaded into the logic cache without losing the data already there or disrupting the opera-
tion of the rest of the chip; replacing or complementing the active logic. The
AT40K/AT40KLV can act as a reconfigurable coprocessor.
Automatic Component
Generators
The AT40K/AT40KLV FPGA family is capable of implementing user-defined, automati-
cally generated, macros in multiple designs; speed and functionality are unaffected by
the macro orientation or density of the target device. This enables the fastest, most pre-
dictable and efficient FPGA design approach and minimizes design risk by reusing
already proven functions. The Automatic Component Generators work seamlessly with
industry standard schematic and synthesis tools to create the fastest, most efficient
designs available.
The patented AT40K/AT40KLV series architecture employs a symmetrical grid of small
yet powerful cells connected to a flexible busing network. Independently controlled
clocks and resets govern every column of cells. The array is surrounded by programma-
ble I/O.
Devices range in size from 5,000 to 50,000 usable gates in the family, and have 256 to
2,304 registers. Pin locations are consistent throughout the AT40K/AT40KLV series for
easy design migration in the same package footprint. The AT40K/AT40KLV series
FPGAs utilize a reliable 0.6µ single-poly, CMOS process and are 100% factory-tested.
Atmel’s PC- and workstation-based integrated development system (IDS) is used to cre-
ate AT40K/AT40KLV series designs. Multiple design entry methods are supported.
The Atmel architecture was developed to provide the highest levels of performance,
functional density and design flexibility in an FPGA. The cells in the Atmel array are
small, efficient and can implement any pair of Boolean functions of (the same) three
inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays
with large numbers of cells, greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient communication over medium and
long distances.
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The Symmetrical
Array
At the heart of the Atmel architecture is a symmetrical array of identical cells,
see Figure 1. The array is continuous from one edge to the other, except for bus repeat-
ers spaced every four cells, see Figure 2 on page 5. At the intersection of each repeater
row and column there is a 32 x 4 RAM block accessible by adjacent buses. The RAM
can be configured as either a single-ported or dual-ported RAM(1), with either synchro-
nous or asynchronous operation.
Note:
1. The right-most column can only be used as single-port RAM.
Figure 1. Symmetrical Array Surrounded by I/O (AT40K20)
= FreeRAM
= Repeater Row
= I/O Pad
= Repeater Column
= AT40K Cell
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AT40K/AT40KLV Series FPGA
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AT40K/AT40KLV Series FPGA
Figure 2. Floor Plan (Representative Portion)(1)
RV
RH
= Vertical Repeater
= Horizontal Repeater
= Core Cell
RAM
RAM
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RAM
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RAM
RAM
RAM
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RAM
RAM
RAM
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RAM
RAM
RAM
RAM
Note:
1. Repeaters regenerate signals and can connect any bus to any other bus (all path-
ways are legal) on the same plane. Each repeater has connections to two adjacent
local-bus segments and two express-bus segments. This is done automatically using
the integrated development system (IDS) tool.
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0896C–FPGA–04/02
The Busing Network
Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus
resources: a local-bus resource (the middle bus) and two express-bus (both sides)
resources. Bus resources are connected via repeaters. Each repeater has connections
to two adjacent local-bus segments and two express-bus segments. Each local-bus
segment spans four cells and connects to consecutive repeaters. Each express-bus
segment spans eight cells and “leapfrogs” or bypasses a repeater. Repeaters regener-
ate signals and can connect any bus to any other bus (all pathways are legal) on the
same plane. Although not shown, a local bus can bypass a repeater via a programma-
ble pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are
implemented through pass gates in the cell-bus interface. Express/Express turns are
implemented through separate pass gates distributed throughout the array.
Some of the bus resources on the AT40K/AT40KLV are used as a dual-function
resources. Table 2 shows which buses are used in a dual-function mode and which bus
plane is used. The AT40K/AT40KLV software tools are designed to accommodate dual-
function buses in an efficient manner.
Table 2. Dual-function Buses
Function
Type
Plane(s) Direction
Comments
Cell Output Enable
Local
5
Horizontal
and Vertical
RAM Output Enable Express
2
Vertical
Vertical
Vertical
Bus full length at array edge
Bus in first column to left of
RAM block
RAM Write Enable
RAM Address
Express
Express
1
Bus full length at array edge
Bus in first column to left of
RAM block
1 - 5
Buses full length at array edge
Buses in second column to left
of RAM block
RAM Data In
Local
Local
1
2
Horizontal
Horizontal
Data In connects to local
bus plane 1
RAM Data Out
Data out connects to local
bus plane 2
Clocking
Express
Express
4
5
Vertical
Vertical
Bus half length at array edge
Bus half length at array edge
Set/Reset
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AT40K/AT40KLV Series FPGA
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AT40K/AT40KLV Series FPGA
Figure 3. Busing Plane (One of Five)
= AT40K/AT40KLV Core Cell
= Local/Local or Express/Express Turn Point
= Row Repeater
= Column Repeater
Express
Bus
Express
Bus
Local
Bus
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Cell Connections
Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors.
Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per
busing plane) and five vertical local buses (1 per busing plane).
Figure 4. Cell Connections
CELL
CELL
CELL
CELL
CELL
CELL
CELL
Plane 5
Plane 4
Horizontal
Busing Plane
Plane 3
Plane 2
Plane 1
WXYZL
CELL
W
X
Y
Z
CELL
L
Vertical
Busing Plane
Diagonal
Direct Connect
CELL
Orthogonal
Direct Connect
(a) Cell-to-cell Connections
(b) Cell-to-bus Connections
The Cell
Figure 5 depicts the AT40K/AT40KLV cell. Configuration bits for separate muxes and
pass gates are independent. All permutations of programmable muxes and pass gates
are legal. Vn (V1 - V5) is connected to the vertical local bus in plane n. Hn (H1 - H5) is
connected to the horizontal local bus in plane n. A local/local turn in plane n is achieved
by turning on the two pass gates connected to Vn and Hn. Pass gates are opened to let
signals into the cell from a local bus or to drive a signal out onto a local bus. Signals
coming into the logic cell on one local bus plane can be switched onto another plane by
opening two of the pass gates. This allows bus signals to switch planes to achieve
greater route ability. Up to five simultaneous local/local turns are possible.
The AT40K/AT40KLV FPGA core cell is a highly configurable logic block based around
two 3-input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT.
This means that any core cell can implement two functions of 3 inputs or one function of
4 inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tri-
stated and fed back internally within the core cell. There is also a 2-to-1 multiplexer in
every cell, and an upstream AND gate in the “front end” of the cell. This AND gate is an
important feature in the implementation of efficient array multipliers.
With this functionality in each core cell, the core cell can be configured in several
“modes”. The core cell flexibility makes the AT40K/AT40KLV architecture well suited to
most digital design application areas, see Figure 6.
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AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
Figure 5. The Cell
"1"
N
E
S
Y
W
"1" NW NE SE SW
"1"
X
W
Z
X
W
Y
FB
8X1 LUT
OUT
8X1 LUT
OUT
"1"
"0" "1"
V1
H1
V2
H2
V3
H3
V4
H4
V5
H5
Pass gates
1
0
Z
L
"1" OE OE
H
V
D
Q
CLOCK
RESET/SET
Y
X
NW NE SE SW
N
E
S
W
X
Y
= Diagonal Direct Connect or Bus
= Orthogonal Direct Connect or Bus
W = Bus Connection
= Bus Connection
FB = Internal Feedback
Z
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0896C–FPGA–04/02
Figure 6. Some Single Cell Modes
Synthesis Mode. This mode is particularly important for
the use of VHDL/Verilog design. VHDL/Verilog Synthesis
tools generally will produce as their output large amounts
of random logic functions. Having a 4-input LUT structure
gives efficient random logic optimization without the
delays associated with larger LUT structures. The output
of any cell may be registered, tri-stated and/or fed back
into a core cell.
A
B
Q (Registered)
and/or
Q
D Q
C
D
SUM
or
Arithmetic Mode is frequently used in many designs.
As can be seen in the figure, the AT40K/AT40KLV core cell
can implement a 1-bit full adder (2-input adder with both
Carry In and Carry Out) in one core cell. Note that the
sum output in this diagram is registered. This output could
then be tri-stated and/or fed back into the cell.
A
B
C
D Q
SUM (Registered)
and/or
CARRY
DSP/Multiplier Mode. This mode is used to efficiently
implement array multipliers. An array multiplier is an array
of bitwise multipliers, each implemented as a full adder
with an upstream AND gate. Using this AND gate and the
diagonal interconnects between cells, the array multiplier
structure fits very well into the AT40K/AT40KLV
architecture.
PRODUCT (Registered)
or
PRODUCT
D Q
A
B
C
D
and/or
CARRY
Counter Mode. Counters are fundamental to almost all
digital designs. They are the basis of state machines,
timing chains and clock dividers. A counter is essentially
an increment by one function (i.e., an adder), with the
input being an output (or a decode of an output) from the
previous stage. A 1-bit counter can be implemented in one
core cell. Again, the output can be registered, tri-stated
and/or fed back.
D Q
Q
CARRY IN
and/or
CARRY
Tri-state/Mux Mode. This mode is used in many
telecommunications applications, where data needs to be
routed through more than one possible path. The output of
the core cell is very often tri-statable for many inputs to
many outputs data switching.
A
B
C
Q
EN
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AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
RAM
32 x 4 dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit
Input Data Bus connects to four horizontal local buses distributed over four sector rows
(plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed
over four sectors in the same column. A 5-bit Output Address Bus connects to five verti-
cal express buses in the same column. Ain (input address) and Aout (output address)
alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks,
Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the
left and Aout is tied off, thus it can only be configured as a single port. For single-ported
RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port.
Right-most RAM blocks can be used only for single-ported memories. WEN and OEN
connect to the vertical express buses in the same column.
Figure 7. RAM Connections (One Ram Block)
CLK
CLK
CLK
CLK
Din
Dout
Aout
32 x 4 RAM
Ain
WEN
OEN
CLK
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0896C–FPGA–04/02
Reading and writing of the 10 ns 32 x 4 dual-port FreeRAM are independent of each
other. Reading the 32 x 4 dual-port RAM is completely asynchronous. Latches are
transparent; when Load is logic 1, data flows through; when Load is logic 0, data is
latched. These latches are used to synchronize Write Address, Write Enable Not, and
Din signals for a synchronous RAM. Each bit in the 32 x 4 dual-port RAM is also a trans-
parent latch. The front-end latch and the memory latch together form an edge-triggered
flip flop. When a nibble (bit = 7) is (Write) addressed and LOAD is logic 1 and WE is
logic 0, data flows through the bit. When a nibble is not (Write) addressed or LOAD is
logic 0 or WE is logic 1, data is latched in the nibble. The two CLOCK muxes are con-
trolled together; they both select CLOCK (for a synchronous RAM) or they both select
“1” (for an asynchronous RAM). CLOCK is obtained from the clock for the sector-column
immediately to the left and immediately above the RAM block. Writing any value to the
RAM clear byte during configuration clears the RAM (see the “AT40K Configuration
Series” application note at www.atmel.com).
Figure 8. RAM Logic
CLOCK
“1”
“1”
0
1
1
0
Load
5
5
Read Address
Write Address
Ain
Aout
WEN
Din
Load
Latch
32 x 4
Dual-port
RAM
“1”
OE
Load
Latch
Write Enable NOT
Load
Latch
4
4
Din
Dout
Dout
Clear
RAM-Clear Byte
Figure 9 on page 13 shows an example of a RAM macro constructed using the
AT40K/AT40KLV’s FreeRAM cells. The macro shown is a 128 x 8 dual-ported asyn-
chronous RAM. Note the very small amount of external logic required to complete the
address decoding for the macro. Most of the logic cells (core cells) in the sectors occu-
pied by the RAM will be unused: they can be used for other logic in the design. This
logic can be automatically generated using the macro generators.
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AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
WE
Write
2-to-4
Decoder
Address
2-to-4
Read
Decoder
Address
Dout(0)
Dout(1)
Dout(2)
Dout(3)
Din(0)
Din(1)
Din(2)
Din(3)
Din
Ain
Dout
Aout
Din
Aout
Dout
Ain
Din
Ain
Dout
Aout
Din
Dout
Ain
Aout
WEN
OEN
WEN
OEN
WEN
OEN
WEN
OEN
Din(4)
Din(5)
Din(6)
Din(7)
Dout(4)
Dout(5)
Dout(6)
Dout(7)
Din
Ain
Dout
Aout
Din
Dout
Ain
Din
Ain
Dout
Aout
Din
Dout
Ain
Aout
Aout
Local Buses
WEN
OEN
WEN
OEN
WEN
OEN
WEN
OEN
Express Buses
Dedicated Connections
Clocking Scheme
There are eight Global Clock buses (GCK1 - GCK8) on the AT40K/AT40KLV FPGA.
Each of the eight dedicated Global Clock buses is connected to one of the dual-use Glo-
bal Clock pins. Any clocks used in the design should use global clocks where possible:
this can be done by using Assign Pin Locks to lock the clocks to the Global Clock loca-
tions. In addition to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4),
two per edge column of the array for PCI specification.
Each column of an array has a “Column Clock mux” and a “Sector Clock mux”. The Col-
umn Clock mux is at the top of every column of an array and the Sector Clock mux is at
every four cells. The Column Clock mux is selected from one of the eight Global Clock
buses. The clock provided to each sector column of four cells is inverted, non-inverted
or tied off to “0”, using the Sector Clock mux to minimize the power consumption in a
sector that has no clocks. The clock can either come from the Column Clock or from the
Plane 4 express bus, see Figure 10 on page 15. The extreme-left Column Clock mux
has two additional inputs, FCK1 and FCK2, to provide fast clocking to left-side I/Os. The
extreme-right Column Clock mux has two additional inputs as well, FCK3 and FCK4, to
provide fast clocking to right-side I/Os.
The register in each cell is triggered on a rising clock edge by default. Before configura-
tion on power-up, constant “0” is provided to each register’s clock pins. After
configuration on power-up, the registers either set or reset, depending on the user’s
choice.
The clocking scheme is designed to allow efficient use of multiple clocks with low clock
skew, both within a column and across the core cell array.
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AT40K/AT40KLV Series FPGA
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AT40K/AT40KLV Series FPGA
Figure 10. Clocking (for One Column of Cells)
}
FCK (2 per Edge Column of the Array)
GCK1 - GCK8
Column Clock Mux
“1”
Sector Clock Mux
Global Clock Line
(Buried)
Express Bus
(Plane 4; Half Length at Edge)
“1”
“1”
“1”
Repeater
Sector Clock Mux
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0896C–FPGA–04/02
Set/Reset Scheme
The AT40K/AT40KLV family reset scheme is essentially the same as the clock scheme
except that there is only one Global Reset. A dedicated Global Set/Reset bus can be
driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks).
The automatic placement tool will choose the reset net with the most connections to use
the global resources. You can change this by using an RSBUF component in your
design to indicate the global reset. Additional resets will use the express bus network.
The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux,
there is Sector Set/Reset mux at every four cells. Each sector column of four cells is
set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux,
see Figure 11 on page 17. The set/reset provided to each sector column of four cells is
either inverted or non-inverted using the Sector Reset mux.
The function of the Set/Reset input of a register is determined by a configuration bit in
each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or
Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a
high) is provided by each register (i.e., all registers are set at power-up).
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AT40K/AT40KLV Series FPGA
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AT40K/AT40KLV Series FPGA
Figure 11. Set/Reset (for One Column of Cells)
Each Cell has a Programmable Set or Reset
Sector Set/Reset Mux
Repeater
“1”
“1”
“1”
Global Set/Reset Line (Buried)
Express Bus
(Plane 5; Half Length at Edge)
“1”
Any User I/O can Drive Global Set/Reset Lone
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0896C–FPGA–04/02
I/O Structure
PAD
The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os
have pads: the ones without pads are called Unbonded I/Os. The number of unbonded
I/Os varies with the device size and package. These unbonded I/Os are used to perform
a variety of bus turns at the edge of the array.
PULL-UP/PULL-DOWN
Each pad has a programmable pull-up and pull-down attached to it. This supplies a
weak “1” or “0” level to the pad pin. When all other drivers are off, this control will dictate
the signal level of the pad pin.
The input stage of each I/O cell has a number of parameters that can be programmed
either as properties in schematic entry or in the I/O Pad Attributes editor in IDS.
TTL/CMOS
SCHMITT
The threshold level can be set to either TTL/CMOS-compatible levels.
A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenera-
tive comparator circuit that adds 1V hysteresis to the input. This effectively improves the
rise and fall times (leading and trailing edges) of the incoming signal and can be useful
for filtering out noise.
DELAYS
DRIVE
The input buffer can be programmed to include four different intrinsic delays as specified
in the AC timing characteristics. This feature is useful for meeting data hold require-
ments for the input signal.
The output drive capabilities of each I/O are programmable. They can be set to FAST,
MEDIUM or SLOW (using IDS tool). The FAST setting has the highest drive capability
(20 mA at 5V) buffer and the fastest slew rate. MEDIUM produces a medium drive
(14 mA at 5V) buffer, while SLOW yields a standard (6 mA at 5V) buffer.
TRI-STATE
The output of each I/O can be made tri-state (0, 1 or Z), open source (1 or Z) or open
drain (0 or Z) by programming an I/O’s Source Selection mux. Of course, the output can
be normal (0 or 1), as well.
SOURCE SELECTION MUX
The Source Selection mux selects the source for the output signal of an I/O, see
Figure 12 on page 20.
18
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
Primary, Secondary and
Corner I/Os
The AT40K/AT40KLV has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner
I/O. Every edge cell except corner cells on the AT40K/AT40KLV has access to one Pri-
mary I/O and two Secondary I/Os.
Primary I/O
Secondary I/O
Corner I/O
Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and
from a Primary I/O cell. The Primary I/O interfaces directly to its adjacent core cell. It
also connects into the repeaters on the row immediately above and below the adjacent
core cell. In addition, each Primary I/O also connects into the busing network of the
three nearest edge cells. This is an extremely powerful feature, as it provides logic cells
toward the center of the array with fast access to I/Os via local and express buses. It can
be seen from the diagram that a given Primary I/O can be accessed from any logic cell
on three separate rows or columns of the FPGA. See Figures 12a on page 20 and 13a
on page 21.
Every logic cell at the edge of the FPGA array has two direct diagonal connections to a
Secondary I/O cell. The Secondary I/O is located between core cell locations. This I/O
connects on the diagonal inputs to the cell above and the cell below. It also connects to
the repeater of the cell above and below. In addition, each Secondary I/O also connects
into the busing network of the two nearest edge cells. This is an extremely powerful fea-
ture, as it provides logic cells toward the center of the array with fast access to I/Os via
local and express buses. It can be seen from the diagram that a given Secondary I/O
can be accessed from any logic cell on two rows or columns of the FPGA. See Figure
12b on page 20 and Figure 13b.
Logic cells at the corner of the FPGA array have direct-connect access to five separate
I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary
I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40K/AT40KLV
FPGA with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can
be accessed both from the corner logic cell and the horizontal and vertical busing net-
works running along the edges of the array. This means that many different edge logic
cells can access the Corner I/Os. See Figure 14 on page 22.
19
0896C–FPGA–04/02
Figure 12. West I/O (Mirrored for East I/O) AT40K/AT40KLV
CELL
CELL
CELL
“0”
“1”
“0”
PULL-UP
“1”
PAD
PULL-DOWN
(a) Primary I/O
“0”
“1”
CELL
“0”
“1”
PULL-UP
PAD
PULL-DOWN
CELL
(b) Secondary I/O
20
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
Figure 13. South I/O (Mirrored for North I/O) AT40K/AT40KLV
CELL
CELL
CELL
“0”
“1”
“0”
“1”
PULL-UP
PAD
PULL-DOWN
(a) Primary I/O
“0”
“1”
CELL
“0”
“1”
PULL-UP
PAD
PULL-DOWN
CELL
(a) Secondary I/O
21
0896C–FPGA–04/02
Figure 14. Northwest Corner (Similar for NE/SE/SW Corners) AT40K/AT40KLV
PAD
PAD
VCC
GND
VCC
GND
TTL/CMOS
SCHMITT
TTL/CMOS
SCHMITT
DELAY
DRIVE
DRIVE
TRI-STATE
TRI-STATE
DELAY
“0”
“1”
“0”
“1”
PULL-UP
PAD
CELL
CELL
PULL-DOWN
CELL
22
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
Absolute Maximum Ratings – 5V Commercial/Industrial* AT40K
*NOTICE:
Stresses beyond those listed under Absolute
Operating Temperature.................................. -55°C to +125°C
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................-0.5V to VCC +7V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............250°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
DC and AC Operating Range – 5V Operation AT40K
Commercial -2
Industrial -2
-40°C - 85°C
5V 10%
Military -2
-55°C - 125°C
5V 10%
Operating Temperature (Case)
CC Power Supply
0°C - 70°C
5V 5%
V
High (VIHT
Low (VILT
High (VIHC
Low (VILC
)
2.0V - VCC
2.0V - VCC
2.0V - VCC
Input Voltage Level (TTL)
)
0V - 0.8V
0V - 0.8V
0V - 0.8V
)
70% - 100% VCC
0 - 30% VCC
70% - 100% VCC
0 - 30% VCC
70% - 100% VCC
0 - 30% VCC
Input Voltage Level (CMOS)
)
23
0896C–FPGA–04/02
DC Characteristics – 5V Operation Commercial/Industrial/Military AT40K
Symbol
Parameter
Conditions
CMOS
TTL
Minimum
70% VCC
2.0
Typical
Maximum
Units
V
V
V
V
VIH
High-level Input Voltage
CMOS
TTL
-0.3
30% VCC
0.8
VIL
Low-level Input Voltage
High-level Output Voltage
-0.3
IOH = 6mA
Ind. = 3.15
4.0
V
CC = VCC Minimum
Con = 3.325
V
V
IOH = 14mA
CC = VCC Minimum
Ind. = 3.15
4.0
V
VOH
Con = 3.325
IOH = 20mA
Commercial = 4.75V
Industrial/Military = 4.5V
Ind. = 3.15
4.0
Con = 3.325
V
V
V
IOL = -6mA
Commercial = 4.75V
Industrial/Military = 4.5V
0.4
0.4
IOL = -14mA
VOL
Low-level Output Voltage
Commercial = 4.75V
Industrial/Military = 4.5V
IOL = -20mA
Commercial = 4.75V
Industrial/Military = 4.5V
0.4
10.0
500.0
V
VIN = VCC Maximum
µA
µA
µA
IIH
High-level Input Current
Low-level Input Current
With pull-down, VIN = VCC
125.0
-10.0
250.0
V
IN = VSS
IIL
With pull-up, VIN = VSS
CON = -1 mA
to -250 µA
CON = -1 mA
to -250 µA
-250.0
250.0
µA
µA
µA
Without pull-down, VIN = VCC
With pull-down, VIN = VCC
10.0
High-level Tri-state Output
Leakage Current
IOZH
125.0
-10.0
500.0
Without pull-up, VIN = VSS
Maximum
µA
Low-level Tri-state Output
Leakage Current
IOZL
With pull-up, VIN = VSS
Maximum
-500.0
-250.0
0.6
-125.0
1.0
µA
mA
pF
ICC
Standby Current Consumption Standby, unprogrammed
Input Capacitance All pins
CIN
10.0
24
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 4.75V, temperature = 70°C
Minimum times based on best case: VCC = 5.25V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
.
Cell Function
Core
Parameter
Path
-2
Units
Notes
2-input Gate
3-input Gate
3-input Gate
4-input Gate
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
DFF
t
PD (Maximum)
x/y -> x/y
x/y/z -> x/y
x/y/w -> x/y
x/y/w/z -> x/y
y -> y
1.8
2.1
2.2
2.2
1.4
1.7
1.8
1.5
2.2
2.3
2.3
1.7
1.8
2.2
2.2
1.8
1.5
1.4
1.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
tPD (Maximum)
t
t
PD (Maximum)
PD (Maximum)
tPD (Maximum)
t
t
PD (Maximum)
PD (Maximum)
x -> y
y -> x
tPD (Maximum)
x -> x
t
t
t
t
t
PD (Maximum)
PD (Maximum)
PD (Maximum)
PD (Maximum)
PD (Maximum)
w -> y
w -> x
z -> y
z -> x
q -> x/y
R -> x/y
S -> x/y
q -> w
DFF
tPD (Maximum)
DFF
t
t
t
t
t
PD (Maximum)
PD (Maximum)
PD (Maximum)
PZX (Maximum)
PXZ (Maximum)
DFF
Incremental -> L
Local Output Enable
Local Output Enable
x/y -> L
oe -> L
oe -> L
1 unit load
1 unit load
25
0896C–FPGA–04/02
AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 4.75V, temperature = 70°C
Minimum times based on best case: VCC = 5.25V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50%
of VCC. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VCC
.
.
Cell Function
Repeaters
Repeater
Repeater
Repeater
Repeater
Repeater
Repeater
Parameter
Path
-2
Units
Notes
tPD (Maximum)
L -> E
E -> E
L -> L
E -> L
E -> IO
L -> IO
1.3
1.3
1.3
1.3
0.8
0.8
ns
ns
ns
ns
ns
ns
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
tPD (Maximum)
t
PD (Maximum)
PD (Maximum)
t
tPD (Maximum)
PD (Maximum)
t
All input IO characteristics measured from a VIH of 50% at the pad (CMOS threshold) to the internal VIH of 50% of VCC. All
output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VCC
.
Cell Function
IO
Parameter
Path
-2
Units
Notes
Input
t
t
t
t
t
PD (Maximum)
PD (Maximum)
PD (Maximum)
PD (Maximum)
PD (Maximum)
pad -> x/y
pad -> x/y
pad -> x/y
pad -> x/y
x/y/E/L -> pad
x/y/E/L -> pad
x/y/E/L -> pad
oe -> pad
1.2
3.6
7.3
10.8
5.9
4.8
3.9
6.2
1.3
4.8
1.9
3.7
1.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No extra delay
1 extra delay
2 extra delays
3 extra delays
50 pf load
Input
Input
Input
Output, Slow
Output, Medium
Output, Fast
Output, Slow
Output, Slow
Output, Medium
Output, Medium
Output, Fast
Output, Fast
tPD (Maximum)
50 pf load
tPD (Maximum)
tPZX (Maximum)
tPXZ (Maximum)
tPZX (Maximum)
tPXZ (Maximum)
50 pf load
50 pf load
oe -> pad
50 pf load
oe -> pad
50 pf load
oe -> pad
50 pf load
tPZX (Maximum)
PXZ (Maximum)
oe -> pad
50 pf load
t
oe -> pad
50 pf load
26
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 4.75V, temperature = 70°C
Minimum times based on best case: VCC = 5.25V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
.
.
Cell Function
Global Clocks and Set/Reset
PD (Maximum)
Parameter
Path
Device
-2
Units
Notes
GCLK Input Buffer
FCLK Input Buffer
Clock Column Driver
Clock Sector Driver
GSRN Input Buffer
Global Clock to Output
t
pad -> clock
pad -> clock
pad -> clock
pad -> clock
AT40K05
AT40K10
AT40K20
AT40K40
1.1
1.2
1.2
1.4
ns
ns
ns
ns
Rising edge clock
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
pad -> clock
pad -> clock
pad -> clock
pad -> clock
AT40K05
AT40K10
AT40K20
AT40K40
0.7
0.8
0.8
0.8
ns
ns
ns
ns
Rising edge clock
Rising edge clock
Rising edge clock
clock -> colclk
clock -> colclk
clock -> colclk
clock -> colclk
AT40K05
AT40K10
AT40K20
AT40K40
0.8
0.9
1.0
1.1
ns
ns
ns
ns
colclk -> secclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
AT40K05
AT40K10
AT40K20
AT40K40
0.5
0.5
0.5
0.5
ns
ns
ns
ns
pad -> GSRN
pad -> GSRN
pad -> GSRN
pad -> GSRN
AT40K05
AT40K10
AT40K20
AT40K40
3.0
3.7
4.3
5.6
ns
ns
ns
ns
From any pad to Global
Set/Reset network
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
AT40K05
AT40K10
AT40K20
AT40K40
8.3
8.4
8.6
8.8
ns
ns
ns
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
Fast Clock to Output
tPD (Maximum)
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
AT40K05
AT40K10
AT40K20
AT40K40
7.9
8.0
8.1
8.3
ns
ns
ns
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
27
0896C–FPGA–04/02
AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 4.75V, temperature = 70°C
Minimum times based on best case: VCC = 5.25V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
.
Cell Function
Async RAM
Write
Parameter
Path
-2
Units
Notes
tWECYC (Minimum)
cycle time
8.0
3.0
3.0
2.0
0.0
2.0
0.0
4.6
3.1
1.6
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
tWEL (Minimum)
we
Pulse width low
Pulse width high
Write
t
WEH (Minimum)
AWS (Minimum)
we
Write
t
wr addr setup -> we
wr addr hold -> we
din setup -> we
din hold -> we
din -> dout
rd addr -> dout
oe -> dout
Write
tAWH (Minimum)
Write
t
DS (Minimum)
DH (Minimum)
Write
t
Write/Read
Read
tDD (Maximum)
rd addr = wr addr
tAD (Maximum)
tOZX (Maximum)
tOXZ (Maximum)
Read
Read
oe -> dout
Sync RAM
Write
t
CYC (Minimum)
cycle time
8.0
3.0
3.0
2.0
0.0
2.0
0.0
2.0
0.0
3.5
3.1
1.6
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
tCLKL (Minimum)
clk
Pulse width low
Pulse width high
Write
tCLKH (Minimum)
tWCS (Minimum)
tWCH (Minimum)
tACS (Minimum)
tACH (Minimum)
tDCS (Minimum)
clk
Write
we setup -> clk
we hold -> clk
wr addr setup -> clk
wr addr hold -> clk
wr data setup -> clk
wr data hold -> clk
clk -> dout
Write
Write
Write
Write
Write
tDCH (Minimum)
Write/Read
Read
tCD (Maximum)
tAD (Maximum)
tOZX (Maximum)
tOXZ (Maximum)
rd addr = wr addr
rd addr -> dout
oe -> dout
Read
Read
oe -> dout
28
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
FreeRAM Asynchronous Timing Characteristics
Single-port Write/Read
t
WEL
WE
t
AWS
t
AWH
0
1
2
3
ADDR
OE
t
OH
t
t
DS
t
t
AD
t
OXZ
OZX
DH
DATA
Dual-port Write with
Read
t
WECYC
t
t
WEH
WEL
WE
t
AWS
t
t
AWH
0
1
2
WR ADDR
WR DATA
DH
PREV.
NEW
t
DD
RD ADDR = WR ADDR 1
t
WD
OLD
PREV.
NEW
RD DATA
Dual-port Read
0
1
RD ADDR
OE
tOZX
tAD
tOXZ
DATA
29
0896C–FPGA–04/02
FreeRAM Synchronous Timing Characteristics
Single-port Write/Read
t
CLKH
CLK
WE
t
t
WCS
WCH
t
t
ACH
ACS
0
1
2
3
ADDR
OE
t
t
OZX
t
AD
OXZ
t
t
DCS
DCH
DATA
Dual-port Write with
Read
tCYC
tCLKH
tCLKL
CLK
tWCH
tWCS
WE
WR ADDR
WR DATA
tACS
tACH
0
1
2
tDCS
tDCH
RD ADDR = WR ADDR 1
RD DATA
tCD
Dual-port Read
0
1
RD ADDR
OE
tOZX
tAD
tOXZ
DATA
30
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
Absolute Maximum Ratings – 3.3V Commercial/Industrial* AT40KLV
*NOTICE:
Stresses beyond those listed under Absolute
Operating Temperature.................................. -55°C to +125°C
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................-0.5V to VCC +7V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............250°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
DC and AC Operating Range – 3.3V Operation AT40KLV
Commercial
Industrial
-40°C - 85°C
3.3V 0.3V
Operating Temperature (Case)
CC Power Supply
0°C - 70°C
3.3V 0.3V
V
High (VIHC
Low (VILC
)
70% - 100% VCC
0 - 30% VCC
70% - 100% VCC
0 - 30% VCC
Input Voltage Level (CMOS)
)
31
0896C–FPGA–04/02
DC Characteristics – 3.3V Operation Commercial/Industrial AT40KLV
Symbol
Parameter
Conditions
CMOS
TTL
Minimum
70% VCC
2.0
Typical
Maximum
Units
V
V
V
V
V
VIH
High-level Input Voltage
CMOS
TTL
-0.3
30% VCC
0.8
VIL
Low-level Input Voltage
High-level Output Voltage
-0.3
IOH = 4 mA
2.1
V
CC = VCC Minimum
IOH = 12 mA
CC = 3.0V
2.1
2.1
V
V
V
V
V
VOH
V
IOH = 16 mA
CC = 3.0V
V
IOL = -4 mA
0.4
0.4
0.4
V
CC = 3.0V
IOL = -12 mA
CC = 3.0V
VOL
Low-level Output Voltage
V
IOL = -16 mA
V
CC = 3.0V
V
IN = VCC Maximum
10.0
µA
µA
µA
µA
µA
IIH
High-level Input Current
Low-level Input Current
With pull-down, VIN = VCC
IN = VSS
75.0
-10.0
-300.0
150.0
300.0
V
IIL
With pull-up, VIN = VSS
Without pull-down,
-150.0
-75.0
10.0
V
IN = VCC Maximum
High-level Tri-state Output
Leakage Current
IOZH
With pull-down,
75.0
150.0
300.0
µA
VIN = VCC Maximum
Without pull-up, VIN = VSS
With pull-up, VIN = VSS
-10.0
mA
µA
Low-level Tri-state Output
Leakage Current
IOZL
CON = -500 µA
TO -125 µA
-150.0
0.6
CON = -500 µA
TO -125 µA-
ICC
Standby Current
Consumption
Standby, unprogrammed
All pins
1.0
mA
pF
CIN
Input Capacitance
10.0
Note:
1. Parameter based on characterization and simulation; it is not tested in production.
32
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.00V, temperature = 70°C
Minimum times based on best case: VCC = 3.60V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
.
Cell Function
Core
Parameter
Path
-3
Units
Notes
2-input Gate
3-input Gate
3-input Gate
4-input Gate
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
DFF
t
PD (Maximum)
x/y -> x/y
x/y/z -> x/y
x/y/w -> x/y
x/y/w/z -> x/y
y -> y
2.9
2.8
3.4
3.4
2.3
2.9
3.0
2.3
3.4
3.4
3.4
2.4
2.8
3.2
3.0
2.7
2.4
2.8
2.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
tPD (Maximum)
t
PD (Maximum)
PD (Maximum)
t
tPD (Maximum)
t
PD (Maximum)
PD (Maximum)
x -> y
t
y -> x
tPD (Maximum)
x -> x
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
w -> y
w -> x
z -> y
z -> x
q -> x/y
R -> x/y
S -> x/y
q -> w
DFF
tPD (Maximum)
DFF
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPZX (Maximum)
tPXZ (Maximum)
DFF
Incremental -> L
Local Output Enable
Local Output Enable
x/y -> L
oe -> L
oe -> L
1 unit load
1 unit load
33
0896C–FPGA–04/02
AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C
Minimum times based on best case: VCC = 3.6V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of
DD. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD
.
V
.
Cell Function
Parameter
Path
-3
Units
Notes
Repeaters
Repeater
Repeater
Repeater
Repeater
Repeater
Repeater
t
PD (Maximum)
L -> E
E -> E
L -> L
E -> L
E -> IO
L -> IO
2.2
2.2
2.2
2.2
1.4
1.4
ns
ns
ns
ns
ns
ns
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
tPD (Maximum)
t
PD (Maximum)
PD (Maximum)
t
tPD (Maximum)
PD (Maximum)
t
All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of
DD. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD
V
.
Cell Function
Parameter
Path
-3
Units
Notes
IO
Input
t
t
t
PD (Maximum)
PD (Maximum)
PD (Maximum)
pad -> x/y
pad -> x/y
pad -> x/y
pad -> x/y
x/y/E/L -> pad
x/y/E/L -> pad
x/y/E/L -> pad
oe -> pad
1.9
5.8
11.5
17.4
9.1
7.6
6.2
9.5
2.1
7.4
2.7
5.9
2.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No extra delay
1 extra delay
2 extra delays
3 extra delays
50 pf load
Input
Input
Input
tPD (Maximum)
Output, Slow
Output, Medium
Output, Fast
Output, Slow
Output, Slow
Output, Medium
Output, Medium
Output, Fast
Output, Fast
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPZX (Maximum)
tPXZ (Maximum)
50 pf load
50 pf load
50 pf load
oe -> pad
50 pf load
tPZX (Maximum)
oe -> pad
50 pf load
tPXZ (Maximum)
tPZX (Maximum)
tPXZ (Maximum)
oe -> pad
50 pf load
oe -> pad
50 pf load
oe -> pad
50 pf load
34
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C
Minimum times based on best case: VCC = 3.6V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
.
.
Cell Function
Parameter
Path
Device
-3
Units
Notes
Global Clocks and Set/Reset
GCK Input Buffer
tPD
pad -> clock
pad -> clock
pad -> clock
pad -> clock
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
1.3
1.5
1.6
1.9
ns
ns
ns
ns
Rising edge clock
(Maximum)
FCK Input Buffer
tPD
pad -> clock
pad -> clock
pad -> clock
pad -> clock
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
0.7
0.8
0.8
0.9
ns
ns
ns
ns
Rising edge clock
Rising edge clock
Rising edge clock
(Maximum)
Clock Column Driver
Clock Sector Driver
GSRN Input Buffer
Global Clock to Output
tPD
clock -> colclk
clock -> colclk
clock -> colclk
clock -> colclk
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
1.5
1.8
2.0
2.5
ns
ns
ns
ns
(Maximum)
tPD
colclk -> secclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
1.0
1.0
1.0
1.0
ns
ns
ns
ns
(Maximum)
tPD
pad -> GSRN
pad -> GSRN
pad -> GSRN
pad -> GSRN
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
4.5
5.4
6.3
8.2
ns
ns
ns
ns
(Maximum)
tPD
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
13.0
13.4
13.8
14.5
ns
ns
ns
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
(Maximum)
Fast Clock to Output
tPD
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
12.4
12.7
13.0
13.5
ns
ns
ns
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
(Maximum)
35
0896C–FPGA–04/02
AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C
Minimum times based on best case: VCC = 3.6V, temperature = 0°C
Cell Function
Async RAM
Write
Parameter
Path
-3
Units
Notes
tWECYC (Minimum)
cycle time
12.0
5.0
5.0
5.3
0.0
5.0
0.0
8.7
6.3
2.9
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
tWEL (Minimum)
we
Pulse width low
Pulse width high
Write
t
WEH (Minimum)
AWS (Minimum)
we
Write
t
wr addr setup -> we
wr addr hold -> we
din setup -> we
din hold -> we
din -> dout
rd addr -> dout
oe -> dout
Write
tAWH (Minimum)
Write
t
DS (Minimum)
DH (Minimum)
Write
t
Write/Read
Read
tDD (Maximum)
rd addr = wr addr
tAD (Maximum)
tOZX (Maximum)
tOXZ (Maximum)
Read
Read
oe -> dout
Sync RAM
Write
t
CYC (Minimum)
cycle time
12.0
5.0
5.0
3.2
0.0
5.0
0.0
3.9
0.0
5.8
6.3
2.9
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
tCLKL (Minimum)
clk
Pulse width low
Pulse width high
Write
tCLKH (Minimum)
tWCS(Minimum)
tWCH (Minimum)
tACS (Minimum)
tACH (Minimum)
tDCS (Minimum)
clk
Write
we setup -> clk
we hold -> clk
wr addr setup -> clk
wr addr hold -> clk
wr data setup -> clk
wr data hold -> clk
clk -> dout
Write
Write
Write
Write
Write
tDCH (Minimum)
Write/Read
Read
tCD (Maximum)
tAD (Maximum)
tOZX (Maximum)
tOXZ (Maximum)
rd addr = wr addr
rd addr -> dout
oe -> dout
Read
Read
oe -> dout
Notes: 1. CMOS buffer delays are measured from a VIH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant.
2. Buffer delay is to a pad voltage of 1.5V with one output switching.
3. Parameter based on characterization and simulation; not tested in production.
4. Exact power calculation is available in Atmel FPGA Designer software.
36
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AT40K05
AT40K05LV
AT40K10
AT40K10LV
AT40K20
AT40K20LV
AT40K40
AT40K40LV
Left Side (Top to Bottom)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
PQFP(2)
SBGA(2)
GND
GND
GND
GND
12
13
4
5
1
2
1
2
1
2
2
4
1
2
304
303
GND(1)
D23
I/O1,
GCK1
(A16)
I/O1,
GCK1
(A16)
I/O1,
GCK1
(A16)
I/O1,
GCK1
(A16)
I/O2
(A17)
I/O2
(A17)
I/O2
(A17)
I/O2
(A17)
14
6
3
3
3
5
3
302
C25
I/O3
I/O4
I/O3
I/O4
I/O3
I/O4
I/O3
I/O4
4
5
4
5
6
7
4
5
301
300
D24
E23
I/O5
(A18)
I/O5
(A18)
I/O5
(A18)
I/O5
(A18)
15
16
7
8
4
5
6
7
6
7
8
9
6
7
299
298
C26
E24
I/O6
(A19)
I/O6
(A19)
I/O6
(A19)
I/O6
(A19)
GND
I/O7
I/O8
I/O9
D25
F23
I/O10
I/O11
I/O12
VCC
GND
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
GND
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
GND
I/O7
I/O8
VCC
GND
297
296
F24
E25
VCC(1)
GND(1)
I/O7
I/O8
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
8
9
10
11
12
13
8
9
295
294
293
292
D26
G24
F25
F26
I/O9
10
11
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
GND
12
13
291
290
289
288
287
H23
H24
G25
G26
GND
GND
8
9
10
11
12
14
15
16
14
15
16
GND(1)
I/O9,
FCK1
I/O13,
FCK1
I/O17,
FCK1
I/O25,
FCK1
286
J23
I/O10
I/O14
I/O18
I/O26
10
285
J24
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
3. On-chip tri-state.
37
0896C–FPGA–04/02
AT40K05
AT40K05LV
AT40K10
AT40K10LV
AT40K20
AT40K20LV
AT40K40
AT40K40LV
Left Side (Top to Bottom)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
PQFP(2)
SBGA(2)
I/O11
(A20)
I/O15
(A20)
I/O19
(A20)
I/O27
(A20)
17
18
9
6
7
11
12
13
14
17
18
17
18
284
283
H25
K23
I/O12
(A21)
I/O16
(A21)
I/O20
(A21)
I/O28
(A21)
10
VCC
I/O17
I/O18
VCC
I/O21
I/O22
VCC
I/O29
I/O30
GND
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
GND
VCC
19
20
21
282
280
279
VCC(1)
K24
J25
J26
L23
I/O23
I/O24
GND
278
277
L24
K25
22
GND(1)
VCC(1)
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
GND
I/O43
I/O44
I/O45
I/O46
I/O25
I/O26
I/O27
I/O28
276
275
274
273
L25
L26
I/O19
I/O20
19
20
23
24
M23
M24
I/O13
I/O14
I/O21
I/O22
I/O29
I/O30
13
14
15
16
21
22
25
26
272
271
M25
M26
11
8
I/O15
(A22)
I/O23
(A22)
I/O31
(A22)
I/O47
(A22)
19
20
12
13
9
15
16
17
18
23
24
27
28
270
269
N24
N25
I/O16
(A23)
I/O24
(A23)
I/O32
(A23)
I/O48
(A23)
10
GND
VCC
GND
VCC
GND
VCC
GND
VCC
21
22
23
24
14
15
16
17
11
12
13
14
17
18
19
20
19
20
21
22
25
26
27
28
29
30
31
32
268
267
266
265
GND(1)
VCC(1)
N26
I/O17
I/O18
I/O25
I/O26
I/O33
I/O34
I/O49
I/O50
I/O51
I/O52
I/O53
P25
I/O19
I/O27
I/O35
18
15
21
23
29
33
264
P23
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
3. On-chip tri-state.
38
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AT40K05
AT40K05LV
AT40K10
AT40K10LV
AT40K20
AT40K20LV
AT40K40
AT40K40LV
Left Side (Top to Bottom)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
I/O54
GND
PQFP(2)
SBGA(2)
I/O20
I/O28
I/O36
22
24
30
34
263
P24
I/O29
I/O30
I/O37
I/O38
I/O39
I/O40
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
VCC
31
32
35
36
262
261
260
259
R26
R25
R24
R23
VCC(1)
GND(1)
T26
GND
I/O41
I/O42
GND
37
I/O61
I/O62
I/O63
I/O64
I/O65
I/O66
GND
258
257
T25
T24
U25
I/O31
I/O32
VCC
I/O43
I/O44
VCC
I/O67
I/O68
VCC
38
39
40
41
42
43
256
255
253
252
251
250
T23
V26
VCC(1)
U24
I/O21
I/O22
I/O23
I/O33
I/O34
I/O35
I/O45
I/O46
I/O47
I/O69
I/O70
I/O71
25
26
19
20
16
17
23
24
25
25
26
27
33
34
35
V25
V24
I/O24,
FCK2
I/O36,
FCK2
I/O48,
FCK2
I/O72,
FCK2
26
27
28
29
36
37
44
45
249
U23
GND
GND
GND
I/O49
I/O50
I/O51
I/O52
GND
I/O73
I/O74
I/O75
I/O76
I/O77
I/O78
GND
I/O79
I/O80
I/O81
I/O82
248
247
246
245
244
GND(1)
Y26
W25
W24
V23
I/O37
I/O38
46
47
I/O39
I/O40
I/O53
I/O54
38
39
48
49
243
242
AA26
Y25
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
3. On-chip tri-state.
39
0896C–FPGA–04/02
AT40K05
AT40K05LV
AT40K10
AT40K10LV
AT40K20
AT40K20LV
AT40K40
AT40K40LV
Left Side (Top to Bottom)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
I/O25
192 I/O
I/O41
256 I/O
I/O55
I/O56
GND
384 I/O
I/O83
I/O84
GND
PQFP(2)
SBGA(2)
30
31
40
41
50
51
241
240
Y24
AA25
GND(1)
VCC(1)
AB25
AA24
I/O26
I/O42
VCC
VCC
I/O57
I/O58
I/O85
I/O86
I/O87
I/O88
I/O89
I/O90
GND
239
238
I/O27
I/O28
I/O43
I/O44
I/O59
I/O60
27
21
22
18
19
28
29
32
33
42
43
52
53
237
236
Y23
AC26
I/O91
I/O92
I/O93
I/O94
AD26
AC25
AA23
AB24
I/O29
I/O30
I/O45
I/O46
I/O61
I/O62
30
31
34
35
44
45
54
55
235
234
I/O31
I/O47
I/O63
I/O95
28
29
23
24
20
21
32
33
36
37
46
47
56
57
233
232
AD25
AC24
(OTS)(3)
(OTS)(3)
(OTS)(3)
(OTS)(3)
I/O32,
GCK2
I/O48,
GCK2
I/O64,
GCK2
I/O96,
GCK2
M1
GND
M0
M1
GND
M0
M1
GND
M0
M1
GND
M0
30
31
32
25
26
27
22
23
24
34
35
36
38
39
40
48
49
50
58
59
60
231
230
229
AB23
GND(1)
AD24
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
3. On-chip tri-state.
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Bottom Side (Left to Right)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
VCC
M2
192 I/O
VCC
M2
256 I/O
VCC
M2
384 I/O
VCC
M2
PQFP(2)
SBGA(2)
33
34
28
29
25
26
37
38
41
42
55
56
61
62
228
227
VCC(1)
AC23
I/O33,
GCK3
I/O49,
GCK3
I/O65,
GCK3
I/O97,
GCK3
35
36
30
31
27
28
39
40
43
44
57
58
63
64
226
225
AE24
AD23
I/O34
(HDC)
I/O50
(HDC)
I/O66
(HDC)
I/O98
(HDC)
I/O35
I/O36
I/O37
I/O51
I/O52
I/O53
I/O67
I/O68
I/O69
I/O99
I/O100
I/O101
41
42
43
45
46
47
59
60
61
65
66
67
224
223
222
AC22
AF24
AD22
32
29
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
40
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Bottom Side (Left to Right)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
PQFP(2)
SBGA(2)
I/O38
(LDC)
I/O54
(LDC)
I/O70
(LDC)
I/O102
(LDC)
37
33
30
44
48
62
68
221
AE23
GND
I/O103
I/O104
I/O105
I/O106
I/O107
I/O108
VCC
AC21
AD21
AE22
AF23
VCC(1)
GND(1)
AD20
AE21
AF21
AC19
I/O71
I/O72
VCC
220
219
GND
I/O73
I/O74
I/O75
I/O76
GND
I/O39
I/O40
I/O55
I/O56
I/O57
I/O58
I/O109
I/O110
I/O111
I/O112
I/O113
I/O114
GND
49
50
63
64
65
66
69
70
71
72
218
217
216
215
I/O77
I/O78
I/O79
I/O80
I/O115
I/O116
I/O117
I/O118
I/O119
I/O120
GND
I/O59
I/O60
73
74
214
213
212
211
210
209
208
207
206
204
203
202
AD19
AE20
AF20
AC18
GND(1)
AD18
AE19
AC17
AD17
VCC(1)
AE18
AF18
GND
I/O41
I/O42
I/O43
I/O44
GND
I/O61
I/O62
I/O63
I/O64
VCC
GND
I/O81
I/O82
I/O83
I/O84
VCC
45
46
47
48
49
51
52
53
54
55
67
68
69
70
71
75
76
77
78
79
80
81
82
I/O121
I/O122
I/O123
I/O124
VCC
38
39
34
35
31
32
I/O65
I/O66
I/O85
I/O86
I/O125
I/O126
GND
72
73
I/O127
I/O128
I/O129
I/O130
AC16
AD16
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
41
0896C–FPGA–04/02
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Bottom Side (Left to Right)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
I/O87
I/O88
GND
384 I/O
I/O131
I/O132
GND
PQFP(2)
SBGA(2)
201
200
AE17
AE16
GND(1)
VCC(1)
AF16
AC15
AD15
AE15
AF15
AD14
83
VCC
I/O89
I/O90
I/O91
I/O92
I/O93
I/O94
I/O133
I/O134
I/O135
I/O136
I/O137
I/O138
GND
199
198
197
196
195
194
I/O67
I/O68
I/O69
I/O70
84
85
86
87
I/O45
I/O46
36
37
33
34
50
51
56
57
74
75
I/O139
I/O140
I/O141
I/O142
I/O47
(D15)
I/O71
(D15)
I/O95
(D15)
I/O143
(D15)
40
41
38
39
35
36
52
53
58
59
76
77
88
89
193
192
AE14
AF14
I/O48
(INIT)
I/O72
(INIT)
I/O96
(INIT)
I/O144
(INIT)
VCC
GND
VCC
GND
VCC
GND
VCC
GND
42
43
40
41
37
38
54
55
60
61
78
79
90
91
191
190
VCC(1)
GND(1)
I/O49
(D14)
I/O73
(D14)
I/O97
(D14)
I/O145
(D14)
44
45
42
43
39
40
56
57
62
63
80
81
92
93
189
188
AE13
AC13
I/O50
(D13)
I/O74
(D13)
I/O98
(D13)
I/O146
(D13)
I/O147
I/O148
I/O149
I/O150
GND
I/O51
I/O52
I/O75
I/O76
I/O77
I/O78
I/O99
I/O100
I/O101
I/O102
I/O103
I/O104
I/O151
I/O152
I/O153
I/O154
I/O155
I/O156
VCC
44
45
41
42
58
59
64
65
82
83
84
85
94
95
96
97
187
186
185
184
183
182
AD13
AF12
AE12
AD12
AC12
AF11
VCC(1)
GND(1)
AE11
GND
GND
98
I/O105
I/O157
181
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
42
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Bottom Side (Left to Right)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
I/O158
I/O159
I/O160
I/O161
I/O162
GND
PQFP(2)
SBGA(2)
I/O106
180
AD11
AE10
AC11
I/O79
I/O80
VCC
I/O107
I/O108
VCC
I/O163
I/O164
VCC
99
179
178
177
AF9
AD10
VCC(1)
100
101
I/O53
(D12)
I/O81
(D12)
I/O109
(D12)
I/O165
(D12)
46
47
46
47
43
44
60
61
66
67
86
87
102
103
175
174
AE9
AD9
I/O54
(D11)
I/O82
(D11)
I/O110
(D11)
I/O166
(D11)
I/O55
I/O56
GND
I/O83
I/O84
GND
I/O111
I/O112
GND
I/O167
I/O168
GND
62
63
64
68
69
70
88
89
90
104
105
106
173
172
171
170
169
168
167
AC10
AF7
GND(1)
AE8
I/O113
I/O114
I/O115
I/O116
I/O169
I/O170
I/O171
I/O172
I/O173
I/O174
GND
AD8
I/O85
I/O86
107
108
AC9
AF6
I/O175
I/O176
I/O177
I/O178
I/O179
I/O180
GND
I/O87
I/O88
I/O89
I/O90
I/O117
I/O118
I/O119
I/O120
GND
91
92
93
94
109
110
111
112
166
165
164
163
AE7
AD7
I/O57
I/O58
71
72
AE6
AE5
GND(1)
VCC(1)
AD6
VCC
VCC
I/O121
I/O122
I/O181
I/O182
162
161
AC7
I/O59
(D10)
I/O91
(D10)
I/O123
(D10)
I/O183
(D10)
48
49
48
49
45
46
65
66
73
74
95
96
113
114
160
159
AF4
AF3
I/O60
(D9)
I/O92
(D9)
I/O124
(D9)
I/O184
(D9)
I/O185
I/O186
AE4
AC6
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
43
0896C–FPGA–04/02
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Bottom Side (Left to Right)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
GND
PQFP(2)
SBGA(2)
I/O187
I/O188
I/O189
I/O190
I/O61
I/O62
I/O93
I/O94
I/O125
I/O126
67
68
75
76
97
98
115
116
158
157
AD5
AE3
I/O63
(D8)
I/O95
(D8)
I/O127
(D8)
I/O191
(D8)
50
51
50
51
47
48
69
70
77
78
99
117
118
156
155
AD4
AC5
I/O64,
GCK4
I/O96,
GCK4
I/O128,
GCK4
I/O192,
GCK4
100
GND
CON
GND
CON
GND
CON
GND
CON
52
53
52
53
49
50
71
72
79
80
101
103
119
120
154
153
GND(1)
AD3
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Right Side (Bottom to Top)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
PQFP(2)
SBGA(2)
VCC
VCC
VCC
VCC
54
55
54
55
51
52
73
74
81
82
106
108
121
122
152
151
VCC(1)
AC4
RESET
RESET
RESET
RESET
I/O65
(D7)
I/O97
(D7)
I/O129
(D7)
I/O193
(D7)
56
57
56
57
53
54
75
76
83
84
109
110
123
124
150
149
AD2
AC3
I/O66,
GCK5
I/O98,
GCK5
I/O130,
GCK5
I/O194,
GCK5
I/O67
I/O68
I/O99
I/O131
I/O132
I/O133
I/O134
I/O195
I/O196
I/O197
I/O198
GND
77
78
85
86
111
112
125
126
148
147
AB4
AD1
AB3
AC2
I/O100
I/O101
I/O102
I/O135
I/O136
I/O199
I/O200
I/O201
I/O202
I/O203
I/O204
VCC
127
128
146
145
AA4
AA3
144
143
AB2
AC1
VCC
GND
VCC(1)
GND(1)
GND
I/O69
(D6)
I/O103
(D6)
I/O137
(D6)
I/O205
(D6)
58
58
55
79
87
113
129
142
Y3
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
44
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Right Side (Bottom to Top)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
I/O70
I/O71
I/O72
192 I/O
I/O104
I/O105
I/O106
256 I/O
I/O138
I/O139
I/O140
384 I/O
I/O206
I/O207
I/O208
I/O209
I/O210
GND
PQFP(2)
SBGA(2)
59
56
80
88
89
90
114
115
116
130
131
132
141
140
139
AA2
AA1
W4
I/O211
I/O212
I/O213
I/O214
I/O215
I/O216
GND
I/O107
I/O108
I/O141
I/O142
I/O143
I/O144
GND
117
118
133
134
138
137
136
135
134
133
132
W3
Y2
Y1
V4
GND
GND
I/O109
I/O110
81
91
119
135
136
137
GND(1)
V3
I/O145
I/O146
I/O217
I/O218
W2
I/O73,
FCK3
I/O111,
FCK3
I/O147,
FCK3
I/O219,
FCK3
82
83
92
93
120
121
138
131
U4
I/O74
I/O112
VCC
I/O148
VCC
I/O220
VCC
139
140
130
129
U3
VCC(1)
I/O75
(D5)
I/O113
(D5)
I/O149
(D5)
I/O221
(D5)
59
60
60
61
57
58
84
85
94
95
122
123
141
142
127
126
V2
V1
I/O76
(CS0)
I/O114
(CS0)
I/O150
(CS0)
I/O222
(CS0)
GND
I/O223
I/O224
I/O225
I/O226
I/O227
I/O228
GND
T4
T3
I/O151
I/O152
GND
125
124
U2
T2
143
GND(1)
VCC(1)
VCC
I/O229
I/O230
I/O231
I/O232
I/O233
I/O234
I/O153
I/O154
I/O155
I/O156
123
122
121
120
T1
R4
R3
R2
I/O115
I/O116
124
125
144
145
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
45
0896C–FPGA–04/02
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Right Side (Bottom to Top)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
GND
PQFP(2)
SBGA(2)
I/O77
I/O78
I/O117
I/O118
I/O157
I/O158
I/O235
I/O236
I/O237
I/O238
I/O239(D4)
I/O240
VCC
62
63
59
60
86
87
96
97
126
127
146
147
119
118
R1
P3
I/O79(D4)
I/O80
I/O119(D4)
I/O120
VCC
I/O159(D4)
I/O160
VCC
61
62
63
64
64
65
66
67
61
62
63
64
88
89
90
91
98
99
128
129
130
131
148
149
150
151
117
116
115
114
P2
P1
VCC
100
101
VCC(1)
GND(1)
GND
GND
GND
GND
I/O81
(D3)
I/O121
(D3)
I/O161
(D3)
I/O241
(D3)
65
66
68
69
65
66
92
93
102
103
132
133
152
153
113
112
N2
N4
I/O82
I/O122
I/O162
I/O242
(CHECK)
(CHECK)
(CHECK)
(CHECK)
I/O243
I/O244
I/O245
I/O246
GND
I/O83
I/O84
I/O123
I/O124
I/O163
I/O164
70
67
94
95
104
105
134
135
154
155
111
110
N3
M1
I/O125
I/O126
I/O165
I/O166
I/O167
I/O168
I/O247
I/O248
I/O249
I/O250
I/O251
I/O252
VCC
136
137
156
157
109
108
107
106
M2
M3
M4
L1
VCC(1)
GND(1)
L2
GND
I/O169
I/O170
GND
158
I/O253
I/O254
I/O255
I/O256
I/O257
I/O258
GND
105
104
L3
K2
L4
I/O85
(D2)
I/O127
(D2)
I/O171
(D2)
I/O259
(D2)
67
68
71
72
68
69
96
97
106
107
138
139
159
103
J1
I/O86
I/O128
VCC
I/O172
VCC
I/O260
VCC
160
161
162
102
101
99
K3
VCC(1)
J2
I/O87
I/O129
I/O173
I/O261
98
108
140
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
46
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Right Side (Bottom to Top)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
PQFP(2)
SBGA(2)
I/O88,
FCK4
I/O130,
FCK4
I/O174,
FCK4
I/O262,
FCK4
99
109
110
141
142
163
98
J3
I/O131
I/O132
GND
I/O175
I/O176
GND
I/O263
I/O264
GND
164
165
166
97
96
95
94
93
92
91
K4
G1
GND
100
GND(1)
H2
I/O177
I/O178
I/O179
I/O180
I/O265
I/O266
I/O267
I/O268
I/O269
I/O270
GND
H3
I/O133
I/O134
167
168
J4
F1
I/O135
I/O136
I/O137
I/O138
I/O181
I/O182
I/O183
I/O184
I/O271
I/O272
I/O273
I/O274
I/O275
I/O276
GND
143
144
145
146
169
170
171
172
90
89
88
87
G2
G3
F2
E2
I/O89
I/O90
111
112
GND
VCC
GND(1)
VCC(1)
VCC
I/O91
(D1)
I/O139
(D1)
I/O185
(D1)
I/O277
(D1)
69
70
73
74
70
71
101
102
113
114
147
148
173
174
86
85
F3
I/O92
I/O140
I/O186
I/O278
I/O279
I/O280
I/O281
I/O282
GND
G4
D1
C1
I/O187
I/O188
I/O189
I/O190
I/O283
I/O284
I/O285
I/O286
84
83
82
81
D2
F4
E3
C2
I/O93
I/O94
I/O141
I/O142
103
104
115
116
149
150
175
176
I/O95
(D0)
I/O143
(D0)
I/O191
(D0)
I/O287
(D0)
71
72
75
76
72
73
105
117
151
177
80
D3
I/O96,
GCK6
I/O144,
GCK6
I/O192,
GCK6
I/O288,
GCK6
106
118
152
178
79
E4
(CSOUT)
(CSOUT)
(CSOUT)
(CSOUT)
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
47
0896C–FPGA–04/02
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Right Side (Bottom to Top)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
CCLK
192 I/O
CCLK
256 I/O
CCLK
384 I/O
CCLK
PQFP(2)
SBGA(2)
73
74
75
77
78
79
74
75
76
107
108
109
119
120
121
153
154
159
179
180
181
78
77
76
C3
VCC(1)
D4
VCC
VCC
VCC
VCC
TSTCLK
TSTCLK
TSTCLK
TSTCLK
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Top Side (Right to Left)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
PQFP(2)
SBGA(2)
GND
GND
GND
GND
76
77
80
81
77
78
110
122
123
160
182
183
75
74
GND(1)
I/O97
(A0)
I/O145
(A0)
I/O193
(A0)
I/O289
(A0)
111
112
161
162
B3
I/O98,
GCK7
(A1)
I/O146,
GCK7
(A1)
I/O194,
GCK7
(A1)
I/O290,
GCK7
(A1)
78
82
79
124
184
73
C4
I/O99
I/O147
I/O148
I/O195
I/O196
I/O291
I/O292
I/O293
I/O294
GND
113
114
125
126
163
164
185
186
72
71
D5
A3
I/O100
I/O295
I/O296
C5
B4
I/O101
I/O149
I/O197
I/O297
79
80
83
84
80
81
115
116
127
128
165
166
187
188
70
69
D6
C6
(CS1,A2)
(CS1,A2)
(CS1,A2)
(CS1,A2)
I/O102
(A3)
I/O150
(A3)
I/O198
(A3)
I/O298
(A3)
I/O199
I/O200
VCC
I/O299
I/O300
VCC
68
67
B5
A4
VCC(1)
GND(1)
GND
GND
I/O151(3)
I/O201(3)
I/O301(3)
75(3)
NC
79(3)
NC
76(3)
NC
109(3)
NC
121(3)
NC
159(3)
NC
189(3)
NC
66(3)
NC
C7(3)
NC
I/O152
I/O153
I/O154
I/O202
I/O203
I/O204
I/O302
I/O303
I/O304
I/O305
I/O306
GND
190
191
192
65
64
63
B6
A6
D8
C8
I/O103
117
129
130
167
168
I/O104(3)
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
3. Shared with TSTCLK. No Connect.
48
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Top Side (Right to Left)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
I/O307
I/O308
I/O309
I/O310
I/O311
I/O312
GND
PQFP(2)
SBGA(2)
I/O155
I/O156
I/O205
I/O206
I/O207
I/O208
GND
169
170
193
194
195
62
61
60
59
58
57
56
55
54
52
51
50
B7
A7
D9
C9
GND
I/O105
I/O106
GND
I/O157
I/O158
I/O159
I/O160
VCC
118
119
120
131
132
133
171
172
173
196
197
198
199
200
201
GND(1)
B8
I/O209
I/O210
I/O211
I/O212
VCC
I/O313
I/O314
I/O315
I/O316
VCC
D10
C10
B9
VCC(1)
A9
I/O213
I/O214
I/O317
I/O318
GND
D11
I/O319
I/O320
I/O321
I/O322
I/O323
I/O324
GND
C11
B10
I/O215
I/O216
GND
49
48
B11
A11
GND(1)
VCC(1)
VCC
I/O107
(A4)
I/O161
(A4)
I/O217
(A4)
I/O325
(A4)
81
82
85
86
82
83
121
122
134
135
174
175
202
203
47
46
D12
C12
I/O108
(A5)
I/O162
(A5)
I/O218
(A5)
I/O326
(A5)
I/O163
I/O164
I/O165
I/O166
I/O219
I/O220
I/O221
I/O222
I/O327
I/O328
I/O329
I/O330
GND
176
177
178
179
205
206
207
208
45
44
43
42
B12
A12
C13
B13
136
137
138
I/O109
I/O110
87
88
84
85
123
124
I/O331
I/O332
I/O333
I/O334
I/O111
(A6)
I/O167
(A6)
I/O223
(A6)
I/O335
(A6)
83
89
86
125
139
180
209
41
A13
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
3. Shared with TSTCLK. No Connect.
49
0896C–FPGA–04/02
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Top Side (Right to Left)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
384 I/O
PQFP(2)
SBGA(2)
I/O112
(A7)
I/O168
(A7)
I/O224
(A7)
I/O336
(A7)
84
90
87
126
140
181
210
40
B14
GND
VCC
GND
VCC
GND
VCC
GND
VCC
1
2
91
92
88
89
127
128
141
142
182
183
211
212
39
38
GND(1)
VCC(1)
I/O113
(A8)
I/O169
(A8)
I/O225
(A8)
I/O337
(A8)
3
4
93
94
90
91
129
130
143
144
184
185
213
214
37
36
D14
C14
I/O114
(A9)
I/O170
(A9)
I/O226
(A9)
I/O338
(A9)
I/O339
I/O340
I/O341
I/O342
GND
I/O115
I/O116
I/O171
I/O172
I/O173
I/O174
I/O227
I/O228
I/O229
I/O230
I/O343
I/O344
I/O345
I/O346
95
96
92
93
131
132
145
146
186
187
188
189
215
216
217
218
35
34
33
32
A15
B15
C15
D15
I/O117
(A10)
I/O175
(A10)
I/O231
(A10)
I/O347
(A10)
5
6
97
98
94
95
133
134
147
148
190
191
220
221
31
30
A16
B16
I/O118
(A11)
I/O176
(A11)
I/O232
(A11)
I/O348
(A11)
VCC
GND
VCC(1)
GND(1)
C16
GND
I/O233
I/O234
I/O349
I/O350
I/O351
I/O352
I/O353
I/O354
GND
29
28
B17
D16
A18
I/O235
I/O236
VCC
I/O355
I/O356
VCC
27
26
25
23
22
21
20
19
18
C17
B18
VCC
I/O177
I/O178
I/O179
I/O180
GND
222
223
224
225
226
227
VCC(1)
C18
I/O237
I/O238
I/O239
I/O240
GND
I/O357
I/O358
I/O359
I/O360
GND
D17
I/O119
I/O120
GND
135
136
137
149
150
151
192
193
194
A20
B19
GND(1)
C19
I/O241
I/O361
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
3. Shared with TSTCLK. No Connect.
50
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AT40K20
AT40K05
AT40K10
AT40K40
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
Top Side (Right to Left)
84
PLCC
100
PQFP
100
TQFP
144
LQFP
160
PQFP
208
PQFP
240
PQFP
304
352
128 I/O
192 I/O
256 I/O
I/O242
I/O243
I/O244
384 I/O
I/O362
I/O363
I/O364
I/O365
I/O366
GND
PQFP(2)
SBGA(2)
17
16
15
D18
A21
B20
I/O181
I/O182
195
196
228
229
I/O367
I/O368
I/O369
I/O370
I/O121
I/O122
I/O183
I/O184
I/O245
I/O246
152
153
197
198
230
231
14
13
C20
B21
I/O123
(A12)
I/O185
(A12)
I/O247
(A12)
I/O371
(A12)
7
8
99
96
97
138
139
154
155
199
200
232
233
12
10
B22
C21
I/O124
(A13)
I/O186
(A13)
I/O248
(A13)
I/O372
(A13)
100
GND
VCC
GND
VCC
GND(1)
VCC(1)
D20
I/O249
I/O250
I/O373
I/O374
I/O375
I/O376
I/O377
I/O378
GND
9
8
A23
A24
B23
I/O187
I/O188
I/O189
I/O190
I/O251
I/O252
I/O253
I/O254
I/O379
I/O380
I/O381
I/O382
234
235
236
237
7
6
5
4
D21
C22
B24
C23
I/O125
I/O126
140
141
156
157
201
202
I/O127
(A14)
I/O191
(A14)
I/O255
(A14)
I/O383
(A14)
9
1
98
142
158
203
238
3
D22
I/O128,
GCK8
(A15)
I/O192,
GCK8
(A15)
I/O256,
GCK8
(A15)
I/O384,
GCK8
(A15)
10
11
2
3
99
143
144
159
160
204
205
239
240
2
1
C24
VCC
VCC
VCC
VCC
100
VCC(1)
Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con-
nection to any specific package pin.
2. This package has an inverted die.
3. Shared with TSTCLK. No Connect.
51
0896C–FPGA–04/02
Power and Ground Pinouts for 352 SBGA(1)
VCC Pins
A10
G23
U26
A17
H4
B2
K1
B25
K26
AC8
D7
N23
D13
P4
D19
U1
W23
AF10
Y4
AC14
AC20
AE2
AE25
AF17
GND Pins
A8
A1
A25
H26
AE1
AF19
A2
A26
A5
B1
A14
E1
A19
E26
AB1
AF8
A22
H1
B26
N1
P26
AF1
AF25
W1
W26
AF5
AB26
AF13
AE26
AF22
AF2
AF26
Note:
1. In SBGA packages, Power and Ground pins do not connect directly to die. They connect to Power and Ground planes inside
the package.
52
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
Part/Package Availability and User I/O Counts (including Dual-function Pins)
Package(1)
AT40K05/AT40K05LV
AT40K10/AT40K10LV
AT40K20/AT40K20LV
AT40K40/AT40K40LV
84 PLCC
62
78
78
114
128
128
–
62
78
78
114
130
161
–
62
77
–
100 PQFP
100 TQFP
144 LQFP
160 PQFP
208 PQFP
240 PQFP
304 PQFP
352 SBGA
–
78
–
114
130
161
193
–
114
–
161
193
256
289
–
–
–
–
–
Note:
1. Devices in same package are pin-to-pin compatible.
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100-lead, Plastic Quad Flat Package (PQFP)
100Q4
100T1
144L1
160Q1
208Q1
240Q1
304Q1
352C1
100-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
144-lead, Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP)
160-lead, Plastic Quad Flat Package (PQFP)
208-lead, Plastic Quad Flat Package (PQFP)
240-lead, Plastic Quad Flat Package (PQFP)
304-lead, Plastic Quad Flat Package (PQFP)
252-ball, Enhanced, Low-profile Square Ball Grid Array Package (SBGA)
53
0896C–FPGA–04/02
AT40K05/AT40K05LV Ordering Information
Usable Gates
Operating Voltage Speed Grade (ns)
Ordering Code
Package
Operation Range(1)
5,000 - 10,000
5.0V
5.0V
3.3V
3.3V
2
2
3
3
AT40K05-2AJC
AT40K05-2AQC
AT40K05-2RQC
AT40K05-2BQC
AT40K05-2CQC
AT40K05-2DQC
84J
Commercial
100T1
100Q4
144L1
160Q1
208Q1
(0°C to 70°C)
5,000 - 10,000
5,000 - 10,000
5,000 - 10,000
AT40K05-2AJI
AT40K05-2AQI
AT40K05-2RQI
AT40K05-2BQI
AT40K05-2CQI
AT40K05-2DQI
84J
Industrial
100T1
100Q4
144L1
160Q1
208Q1
(-40°C to 85°C)
AT40K05LV-3AJC
AT40K05LV-3AQC
AT40K05LV-3RQC
AT40K05LV-3BQC
AT40K05LV-3CQC
AT40K05LV-3DQC
84J
Commercial
100T1
100Q4
144L1
160Q1
208Q1
(0°C to 70°C)
AT40K05LV-3AJI
AT40K05LV-3AQI
AT40K05LV-3RQI
AT40K05LV-3BQI
AT40K05LV-3CQI
AT40K05LV-3DQI
84J
Industrial
100T1
100Q4
144L1
160Q1
208Q1
(-40°C to 85°C)
Note:
1. For military parts, contact Atmel at fpga@atmel.com.
54
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AT40K10/AT40K10LV Ordering Information
Usable Gates
Operating Voltage Speed Grade (ns)
Ordering Code
Package
Operation Range(1)
10,000 - 20,000
5.0V
5.0V
3.3V
3.3V
2
2
3
3
AT40K10-2AJC
AT40K10-2AQC
AT40K10-2RQC
AT40K10-2BQC
AT40K10-2CQC
AT40K10-2DQC
84J
Commercial
100T1
100Q4
144L1
160Q1
208Q1
(0°C to 70°C)
10,000 - 20,000
10,000 - 20,000
10,000 - 20,000
AT40K10-2AJI
AT40K10-2AQI
AT40K10-2RQI
AT40K10-2BQI
AT40K10-2CQI
AT40K10-2DQI
84J
Industrial
100T1
100Q4
144L1
160Q1
208Q1
(-40°C to 85°C)
AT40K10LV-3AJC
AT40K10LV-3AQC
AT40K10LV-3RQC
AT40K10LV-3BQC
AT40K10LV-3CQC
AT40K10LV-3DQC
84J
Commercial
100T1
100Q4
144L1
160Q1
208Q1
(0°C to 70°C)
AT40K10LV-3AJI
AT40K10LV-3AQI
AT40K10LV-3RQI
AT40K10LV-3BQI
AT40K10LV-3CQI
AT40K10LV-3DQI
84J
Industrial
100T1
100Q4
144L1
160Q1
208Q1
(-40°C to 85°C)
Note:
1. For military parts, contact Atmel at fpga@atmel.com.
55
0896C–FPGA–04/02
AT40K20/AT40K20LV Ordering Information
Usable Gates
Operating Voltage Speed Grade (ns)
Ordering Code
Package
Operation Range(1)
20,000 - 30,000
5.0V
5.0V
3.3V
3.3V
2
2
3
3
AT40K20-2AJC
AT40K20-2AQC
AT40K20-2RQC
AT40K20-2BQC
AT40K20-2CQC
AT40K20-2DQC
AT40K20-2EQC
84J
Commercial
100T1
100Q4
144L1
160Q1
208Q1
240Q1
(0°C to 70°C)
20,000 - 30,000
20,000 - 30,000
20,000 - 30,000
AT40K20-2AJI
AT40K20-2AQI
AT40K20-2RQI
AT40K20-2BQI
AT40K20-2CQI
AT40K20-2DQI
AT40K20-2EQI
84J
Industrial
100T1
100Q4
144L1
160Q1
208Q1
240Q1
(-40°C to 85°C)
AT40K20LV-3AJC
AT40K20LV-3AQC
AT40K20LV-3RQC
AT40K20LV-3BQC
AT40K20LV-3CQC
AT40K20LV-3DQC
AT40K20LV-2EQC
84J
Commercial
100T1
100Q4
144L1
160Q1
208Q1
240Q1
(0°C to 70°C)
AT40K20LV-3AJI
AT40K20LV-3AQI
AT40K20LV-3RQI
AT40K20LV-3BQI
AT40K20LV-3CQI
AT40K20LV-3DQI
AT40K20LV-2EQI
84J
Industrial
100T1
100Q4
144L1
160Q1
208Q1
240Q1
(-40°C to 85°C)
Note:
1. For military parts, contact Atmel at fpga@atmel.com
56
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
AT40K40/AT40K40LV Ordering Information
Usable Gates
Operating Voltage Speed Grade (ns)
Ordering Code
Package
Operation Range(1)
40,000 - 50,000
5.0V
5.0V
3.3V
3.3V
2
2
3
3
AT40K40-2BQC
AT40K40-2DQC
AT40K40-2EQC
AT40K40-2FQC
AT40K40-2BGC
144Q1
208Q1
240Q1
304Q1
352C1
Commercial
(0°C to 70°C)
40,000 - 50,000
40,000 - 50,000
40,000 - 50,000
AT40K40-2BQI
AT40K40-2DQI
AT40K40-2EQI
AT40K40-2FQI
AT40K40-2BGI
144Q1
208Q1
240Q1
304Q1
352C1
Industrial
(-40°C to 85°C)
AT40K40LV-2BQC
AT40K40LV-2DQC
AT40K40LV-2EQC
AT40K40LV-2FQC
AT40K40LV-2BGC
144Q1
208Q1
240Q1
304Q1
352C1
Commercial
(0°C to 70°C)
AT40K40LV-2BQI
AT40K40LV-2DQI
AT40K40LV-2EQI
AT40K40LV-2FQI
AT40K40LV-2BGI
144Q1
208Q1
240Q1
304Q1
352C1
Industrial
(-40°C to 85°C)
Note:
1. For military parts, contact Atmel at fpga@atmel.com.
57
0896C–FPGA–04/02
Packaging Information
84J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
30.099
29.210
30.099
29.210
–
30.353
D1
E
–
29.413 Note 2
30.353
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AF.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
29.413 Note 2
28.702
D2/E2 27.686
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
84J
B
R
58
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
100T1 – TQFP
D
D1
XX
e
E
E1
N
b
Bottom View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.05
0.95
MAX
0.15
1.05
NOM
NOTE
SYMBOL
A2
A1
6
A2
D
1.00
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
0.50 BSC
0.22
A1
D1
E
2, 3
2, 3
4, 5
L1
Side View
E1
e
b
0.17
0.27
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions, including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum
b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and
an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating place to the lowest point on the package body.
11/30/01
TITLE
100T1, 100-lead (14 x 14 x 1.0 mm Body), Thin Plastic
Quad Flat Pack (TQFP)
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
100T1
A
R
59
0896C–FPGA–04/02
100Q4 – PQFP
D1
D
E
E1
Top View
Bottom View
A2
A1
e
b
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
0.25
2.50
MAX
0.50
2.90
NOM
–
NOTE
SYMBOL
A1
A2
D
5
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-022, Variation GC-1, for additional information.
2.70
23.20 BSC
20.00 BSC
17.20 BSC
14.00 BSC
0.65 BSC
2
3
2
3
2. To be determined at seating plane.
D1
E
3. Regardless of the relative size of the upper and lower body sections,
dimensions D1 and E1 are determined at the largest feature of the body
exclusive of mold Flash and gate burrs, but including any mismatch
between the upper and lower sections of the molded body.
4. Dimension b does not include Dambar protrusion. The Dambar
protrusion(s) shall not cause the lead width to exceed b maximum by more
than 0.08 mm. Dambar cannot be located on the lower radius or the lead
foot.
E1
e
b
0.22
0.40
4
L1
1.60 REF
5. A1 is defined as the distance from the seating plane to the lowest
point of the package body.
3/29/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
100Q4, 100-lead, 14 x 20 mm Body, 3.2 Form Opt.,
Plastic Quad Flat Pack (PQFP)
100Q4
A
R
60
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
144L1 – LQFP
D1
D
XX
e
E1
E
N
b
Bottom View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.05
1.35
MAX
0.15
1.45
NOM
NOTE
SYMBOL
A1
A2
D
6
A2
1.40
22.00 BSC
20.00 BSC
22.00 BSC
20.00 BSC
0.50 BSC
0.22
A1
D1
E
2, 3
2, 3
4, 5
L1
Side View
E1
e
b
0.17
0.27
L1
1.00 REF
1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
Notes:
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum
b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and
an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating place to the lowest point on the package body.
11/30/01
TITLE
144L1, 144-lead (20 x 20 x 1.4 mm Body), Low Profile
Plastic Quad Flat Pack (LQFP)
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
144L1
A
R
61
0896C–FPGA–04/02
160Q1 – PQFP
D1
D
E
E1
Top View
Bottom View
A2
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
e
b
L1
MIN
0.25
3.20
MAX
0.50
SYMBOL
NOM
–
NOTE
Side View
A1
A2
D
5
3.40
3.60
31.20 BSC
28.00 BSC
31.20 BSC
28.00 BSC
0.65 BSC
–
2
3
2
3
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-022, Variation DD-1, for additional information.
D1
E
2. To be determined at seating plane.
3. Regardless of the relative size of the upper and lower body sections,
dimensions D1 and E1 are determined at the largest feature of the body
exclusive of mold Flash and gate burrs, but including any mismatch
between the upper and lower sections of the molded body.
4. Dimension b does not include Dambar protrusion. The Dambar
protrusion(s) shall not cause the lead width to exceed b maximum by more
than 0.08 mm. Dambar cannot be located on the lower radius or the lead
foot.
E1
e
b
0.22
0.40
4
L1
1.60 REF
5. A1 is defined as the distance from the seating plane to the lowest point of
the package body.
3/28/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
160Q1, 160-lead, 28 x 28 mm Body, 3.2 Form Opt.,
160Q1
A
R
Plastic Quad Flat Pack (PQFP)
62
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
208Q1 – TQFP
D1
A2
L1
A1
E1
Side View
e
b
Top View
D
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.25
3.20
MAX
0.50
3.60
NOM
NOTE
SYMBOL
A1
A2
D
3.40
E
30.60 BSC
28.00 BSC
30.60 BSC
28.00 BSC
0.50 BSC
D1
E
2, 3
2, 3
4
E1
e
b
0.17
0.27
L1
1.30 REF
Bottom View
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07 mm.
11/30/01
TITLE
208Q1, 208-lead (28 x 28 mm Body, 2.6 Form Opt.),
Plastic Quad Flat Pack (PQFP)
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
208Q1
A
R
63
0896C–FPGA–04/02
240Q1 – PQFP
D1
D
E1
E
Top View
Bottom View
A2
A1
e
b
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
0.25
3.20
MAX
0.50
3.60
NOM
–
NOTE
SYMBOL
A1
A2
D
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-029, Variation GA, for additional information.
3.40
34.60 BSC
32.00 BSC
34.60 BSC
32.00 BSC
0.50 BSC
–
3
2. All dimensioning and tolerancing conforms to ASME Y14.5M-1994.
3. To be determined at seating plane.
4. Dimensions D1 and E1 do not include mold protrusions. Allowable
protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size
dimensions including mold mismatch. Dimensions D1 and E1 shall be
determined at datum plane.
5. Dimension b does not include Dambar protrusion. Allowable Dambar
protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08 mm. Dambar cannot be located on the lower
radius or the foot. The minimum space between protrusion and an adjacent
lead shall not be less than 0.07 mm.
D1
E
2, 4
3
E1
e
2, 4
b
0.17
0.27
5
L1
1.30 REF
3/29/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
240Q1, 240-lead, 32 x 32 mm Body, 2.6 Form Opt.,
Plastic Quad Flat Pack (PQFP)
240Q1
A
R
64
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AT40K/AT40KLV Series FPGA
304Q1 – PQFP
D
D1
E
E1
Bottom View
Top View
A2
A1
e
b
L1
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.25
3.55
MAX
0.50
4.05
NOM
–
NOTE
SYMBOL
A1
A2
D
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-029, Variation JA, for additional information.
3.80
42.60 BSC
40.00 BSC
42.60 BSC
40.00 BSC
0.50 BSC
–
3
2. All dimensioning and tolerancing conforms to ASME Y14.5M-1994.
3. To be determined at seating plane.
4. Dimensions D1 and E1 do not include mold protrusions. Allowable
protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size
dimensions including mold mismatch. Dimensions D1 and E1 shall be
determined at Datum plane.
5. Dimension b does not include Dambar protrusion. Allowable Dambar
protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08 mm. Dambar can not be located on the lower
radius or the foot. The minimum space between protrusion and an adjacent
lead shall not be less than 0.07 mm.
D1
E
2, 4
3
E1
e
2, 4
b
0.17
0.27
5
L1
1.30 REF
3/29/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
304Q1, 304-lead, 40 x 40 mm Body, 2.6 Form Opt.,
Plastic Quad Flat Pack (PQFP)
304Q1
A
R
65
0896C–FPGA–04/02
352C1 – SBGA
A1 BALL
CORNER
A1 BALL CORNER
D
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
A
B
b∅
C
D
E
F
G
A1 BALL I.D.
H
J
K
L
M
N
E
P
R
T
e
U
V
W
Y
AA
AB
AC
AD
AE
AF
e
Top View
Bottom View
Die Side
A
A2
A1
Section View
SEATING PLANE
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
35.0 BSC
35.0 BSC
26 x 26
–
NOTE
SYMBOL
D
E
Matrix Size
A
A1
A2
b∅
e
–
1.70
–
0.35
0.25
0.60
–
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MO-192, Variation BAR-2, for additional information.
2. JEDEC variations are based on fully populated ball arrays. Arrays
can be depopulated as desired by removing balls from the fully populated
array.
–
1.10
0.90
0.75
1.27 BSC
3/29/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
352C1, 352-ball, 35 x 35, Enhanced, Low-profile
Square Ball Grid Array Package (SBGA)
352C1
A
R
66
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
TEL (41) 26-426-5555
FAX (41) 26-426-5500
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
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TEL 1(719) 576-3300
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FAX 1(719) 540-1759
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Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
Atmel Programmable SLI Hotline
e-mail
literature@atmel.com
(408) 436-4119
Atmel Programmable SLI e-mail
Web Site
http://www.atmel.com
fpga@atmel.com
FAQ
Available on web site
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL® and Cache Logic® are the registered trademarks of Atmel. FreeRAM™ and QuickChange are the
trademarks of Atmel.
Concept®, Verilog® and OrCAD® are the registered trademarks of Cadence Design Systems, Inc.; Mentor® and
Veribest® are the registered trademarks of Mentor Graphics; Exemplar™ is the trademark of Mentor Graphics;
Printed on recycled paper.
Synario™ is the trademark of Data I/O Corporation; Synopsys® is the registered trademark of Synopsis, Inc.;
Viewlogic™ is the trademark of Viewlogic Systems, Inc.; Synplicity® is the registered trademark of Synplify, Inc.
Other terms and product names may be the trademarks of others.
0896C–FPGA–04/02
xM
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