AT29C512-70TI [ATMEL]
512K (64K x 8) 5-volt Only Flash Memory; 512K （ 64K ×8 ）， 5伏只有闪存
| 型号： | AT29C512-70TI |
| 厂家： | 
ATMEL |
| 描述： | 512K (64K x 8) 5-volt Only Flash Memory |
| 文件： | 总18页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 70 ns
• 5-volt Only Reprogramming
• Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Sectors (128 Bytes/Sector)
– Internal Address and Data Latches for 128 Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Fast Sector Program Cycle Time – 10 ms
• DATA Polling for End of Program Detection
• Low Power Dissipation
512K (64K x 8)
5-volt Only
Flash Memory
– 50 mA Active Current
– 100 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles
• Single 5V 10ꢀ Supply
AT29C512
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
• Green (Pb/Halide-free) Packaging Option
1. Description
The AT29C512 is a 5-volt only in-system Flash programmable and erasable read only
memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Man-
ufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just 275 mW over the commercial tem-
perature range. When the device is deselected, the CMOS standby current is less
than 100 µA. The device endurance is such that any sector can typically be written to
in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29C512 does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from an EPROM.
Reprogramming the AT29C512 is performed on a sector basis; 128 bytes of data are
loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 128 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the sector and then program
the latched data using an internal control timer. The end of a program cycle can be
detected by DATA polling of I/O7. Once the end of a program cycle has been
detected, a new access for a read or program can begin.
0456H–FLASH–2/05
2. Pin Configurations
Pin Name
Function
A0 - A15
CE
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
WE
I/O0 - I/O7
NC
2.1
32-lead PLCC Top View
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
A2 10
A1 11
A0 12
I/O0 13
2.2
32-lead TSOP (Type 1) Top View
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
6
7
8
9
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
2
AT29C512
0456H–FLASH–2/05
AT29C512
3. Block Diagram
4. Device Operation
4.1
4.2
4.3
Read
The AT29C512 is accessed like an EPROM. When CE and OE are low and WE is high, the data
stored at the memory location determined by the address pins is asserted on the outputs. The
outputs are put in the high impedance state whenever CE or OE is high. This dual-line control
gives designers flexibility in preventing bus contention.
Byte Load
Program
Byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes
for data protection. A byte load is performed by applying a low pulse on the WE or CE input with
CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or
WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.
The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device. Any byte that is not loaded during the
programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the
device, they are simultaneously programmed during the internal programming period. After the
first data byte has been loaded into the device, successive bytes are entered in the same man-
ner. Each new byte to be programmed must have its high-to-low transition on WE (or CE) within
150 µs of the low-to-high transition of WE (or CE) of the preceding byte. If a high-to-low transi-
tion is not detected within 150 µs of the last low-to-high transition, the load period will end and
the internal programming period will start. A7 to A15 specify the sector address. The sector
address must be valid during each high-to-low transition of WE (or CE). A0 to A6 specify the
byte address within the sector. The bytes may be loaded in any order; sequential loading is not
required. Once a programming operation has been initiated, and for the duration of tWC, a read
operation will effectively be a polling operation.
3
0456H–FLASH–2/05
4.4
Software Data Protection
A software controlled data protection feature is available on the AT29C512. Once the software
protection is enabled a software algorithm must be issued to the device before a program may
be performed. The software protection feature may be enabled or disabled by the user; when
shipped from Atmel, the software data protection feature is disabled. To enable the software
data protection, a series of three program commands to specific addresses with specific data
must be performed. After the software data protection is enabled the same three program com-
mands must begin each program cycle in order for the programs to occur. All software program
commands must obey the sector program timing specifications. Once set, the software data pro-
tection feature remains active unless its disable command is issued. Power transitions will not
reset the software data protection feature; however, the software feature will guard against inad-
vertent program cycles during power transitions.
Once set, software data protection will remain active unless the disable command sequence is
issued.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
tWC, a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is performed by
applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The
address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE. The 128 bytes of data must be loaded into each sector by the
same procedure as outlined in the program section under device operation.
4.5
4.6
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT29C512 in the following ways:
(a) VCC sense – if VCC is below 3.8V (typical), the program function is inhibited; (b) VCC power on
delay – once VCC has reached the VCC sense level, the device will automatically time out 5 ms
(typical) before programming; (c) Program inhibit – holding any one of OE low, CE high or WE
high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a program cycle.
Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product. In
addition, users may wish to use the software product identification mode to identify the part (i.e.,
using the device code), and have the system software use the appropriate sector size for pro-
gram operations. In this manner, the user can have a common board design for 256K to 4-
megabit densities and, with each density’s sector size in a memory map, have the system soft-
ware apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4
AT29C512
0456H–FLASH–2/05
AT29C512
4.7
4.8
DATA Polling
Toggle Bit
The AT29C512 features DATA polling to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in the complement of the loaded data
on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the
next cycle may begin. DATA polling may begin at any time during the program cycle.
In addition to DATA polling the AT29C512 provides another method for determining the end of a
program or erase cycle. During a program or erase operation, successive attempts to read data
from the device will result in I/O6 toggling between one and zero. Once the program cycle has
completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin
at any time during a program cycle.
4.9
Optional Chip Erase Mode
The entire device can be erased by using a 6-byte software code. Please see Software Chip
Erase application note for details.
5. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
5
0456H–FLASH–2/05
6. DC and AC Operating Range
AT29C512-70
AT29C512-90
0°C - 70°C
-40°C - 85°C
5V 10%
AT29C512-12
0°C - 70°C
-40°C - 85°C
5V 10%
AT29C512-15
0°C - 70°C
-40°C - 85°C
5V 10%
Com.
Ind.
0°C - 70°C
-40°C - 85°C
5V 5%
Operating
Temperature (Case)
VCC Power Supply
Note:
Not recommended for New Designs.
7. Operating Modes
Mode
CE
VIL
VIL
VIL
VIH
X
OE
VIL
VIH
VIH
X(1)
X
WE
VIH
VIL
VIL
X
Ai
Ai
Ai
Ai
X
I/O
DOUT
DIN
Read
Program(2)
5V Chip Erase
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
High Z
VIH
X
X
VIL
VIH
X
X
High Z
A1 - A15 = VIL, A9 = VH,(3) A0 = VIL
A1-A15 = VIL, A9 = VH,(3) A0 = VIH
A0 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 1F, Device Code: 5D.
5. See details under Software Product Identification Entry/Exit.
8. DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC
VI/O = 0V to VCC
ILO
10
Com.
Ind.
100
300
3
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
ISB2
ICC
VCC Standby Current TTL
VCC Active Current
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
50
VIL
Input Low Voltage
0.8
VIH
Input High Voltage
2.0
V
VOL
VOH1
VOH2
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
IOL = 2.1 mA
0.45
V
IOH = -400 µA
2.4
4.2
V
IOH = -100 µA; VCC = 4.5V
V
6
AT29C512
0456H–FLASH–2/05
AT29C512
9. AC Read Characteristics
AT29C512-70
AT29C512-90
AT29C512-12
AT29C512-15
Symbol
Parameter
Min
Max
70
Min
Max
90
Min
Max
120
120
50
Min
Max
150
150
70
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
70
90
ns
(2)
tOE
0
0
35
0
0
40
0
0
0
0
ns
(3)(4)
tDF
10
25
30
40
ns
Output Hold from OE, CE or
Address, whichever
occurred first
tOH
0
0
0
0
ns
Note:
Not recommended for New Designs.
10. AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
7
0456H–FLASH–2/05
11. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
12. Output Test Load
70 ns
5.0V
90/120/150 ns
5.0V
1.8K
1.8K
OUTPUT
OUTPUT
PIN
PIN
30pF
100pF
1.3K
1.3K
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
8
AT29C512
0456H–FLASH–2/05
AT29C512
14. AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
50
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
90
35
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
100
ns
15. AC Byte Load Waveforms
15.1 WE Controlled
OE
t
t
OES
OEH
ADDRESS
CE
t
AS
t
AH
t
CH
t
CS
WE
t
t
WPH
t
WP
t
DH
DS
DATA IN
15.2 CE Controlled
OE
ADDRESS
WE
t
OES
t
OEH
t
t
AH
AS
t
CH
t
CS
CE
t
t
WPH
t
WP
t
DS
DH
DATA IN
9
0456H–FLASH–2/05
16. Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
tWC
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
tAS
0
tAH
50
35
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
90
ns
tBLC
tWPH
150
µs
100
ns
17. Program Cycle Waveforms(1)(2)(3)
Notes: 1. A7 through A15 must specify the sector address during each high-to-low transition of WE (or CE).
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
10
AT29C512
0456H–FLASH–2/05
AT29C512
18. Software Data Protection
Enable Algorithm(1)
19. Software Data Protection
Disable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA A0
TO
LOAD DATA 80
TO
ADDRESS 5555
WRITES ENABLED
ADDRESS 5555
LOAD DATA
TO
PAGE (128 BYTES)(4)
LOAD DATA AA
TO
ENTER DATA
PROTECT STATE(2)
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Notes: 1. Data Format: I/O7 - I/O0 (Hex);Address Format: A14
- A0 (Hex).
LOAD DATA 20
TO
2. Data Protect state will be activated at end of program
cycle.
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
3. Data Protect state will be deactivated at end of pro-
gram period.
LOAD DATA
TO
PAGE (128 BYTES)(4)
4. 128 bytes of data MUST BE loaded.
20. Software Protected Program Cycle Waveform(1)(2)(3)
OE(1)
CE
tWPH
tBLC
tWP
WE
tAS
tAH
tDH
BYTEADDRESS
A0-A6
5555
2AAA
5555
A7-A15(2)
DATA (3)
SECTORADDRESS
tDS
AA
55
A0
BYTE 0
BYTE126
BYTE127
tWC
Notes: 1. A7 through A15 must specify the page address during each high-to-low transition of WE (or CE) after the software code has
been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
11
0456H–FLASH–2/05
21. Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
22. Data Polling Waveforms
23. Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
24. Toggle Bit Waveforms(1)(2)(3)
WE
CE
t
OEH
OE
t
t
OE
DH
HIGHZ
I/O6(2)
t
WR
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
12
AT29C512
0456H–FLASH–2/05
AT29C512
25. Software Product Identification Entry(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
PAUSE 10 mS
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
26. Software Product Identification Exit(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 10 mS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex).
2. A1 - A15 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is 5D.
13
0456H–FLASH–2/05
27. Normalized ICC Graphs
NORMALIZED SUPPLY CURRENT
vs.TEMPERATURE
1.4
1.3
1.2
1.1
1.0
0.9
0.8
N
O
R
M
A
L
I
Z
E
D
I
C
C
-55
-25
5
35
65
95
125
TEMPERATURE (C)
NORMALIZED SUPPLY CURRENT
vs. ADDRESS FREQUENCY
1.1
1.0
0.9
0.8
0.7
N
O
R
M
A
L
I
Z
E
D
VCC = 5V
T = 25C
I
C
C
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
1.0
N
O
R
M
A
L
I
Z
E
D
0.8
0.6
I
C
C
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
14
AT29C512
0456H–FLASH–2/05
AT29C512
28. Ordering Information
28.1 Standard Package
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
AT29C512-70JC
AT29C512-70TC
32J
32T
Commercial
50
0.1
(0° to 70°C)
70
AT29C512-70JI
AT29C512-70TI
32J
32T
Industrial
50
50
50
50
50
50
50
0.3
0.1
0.3
0.1
0.3
0.1
0.3
(-40° to 85°C)
AT29C512-90JC
AT29C512-90TC
32J
32T
Commercial
(0° to 70°C)
90
AT29C512-90JI
AT29C512-90TI
32J
32T
Industrial
(-40° to 85°C)
AT29C512-12JC
AT29C512-12TC
32J
32T
Commercial
(0° to 70°C)
120
150
AT29C512-12JI
AT29C512-12TI
32J
32T
Industrial
(-40° to 85°C)
AT29C512-15JC
AT29C512-15TC
32J
32T
Commercial
(0° to 70°C)
AT29C512-15JI
AT29C512-15TI
32J
32T
Industrial
(-40° to 85°C)
Note:
Not recommended for New Designs.
28.2 Green Package Option (Pb/Halide-free)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
AT29C512-70JU
AT29C512-70TU
32J
32T
Industrial
70
90
50
03
(-40° to 85°C)
AT29C512-90JU
AT29C512-90TU
32J
32T
Industrial
50
0.3
(-40° to 85°C)
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32-lead, Thin Small Outline Package (TSOP)
32T
15
0456H–FLASH–2/05
29. Packaging Information
29.1 32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
16
AT29C512
0456H–FLASH–2/05
AT29C512
29.2 32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
20.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
19.80
18.30
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
20.00
18.40
8.00
D1
E
18.50 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
32T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
R
17
0456H–FLASH–2/05
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