AT28HC256-70 [ATMEL]
256 32K x 8 High Speed CMOS E2PROM; 256 32K ×8高速CMOS E2PROM
| 型号： | AT28HC256-70 |
| 厂家： | 
ATMEL |
| 描述： | 256 32K x 8 High Speed CMOS E2PROM |
| 文件： | 总12页 (文件大小：731K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT28HC256
Features
Fast Read Access Time - 70 ns
Automatic Page Write Operation
•
•
Internal Address and Data Latches for 64-Bytes
Internal Control Timer
Fast Write Cycle Times
•
Page Write Cycle Time: 3 ms or 10 ms Maximum
1 to 64-Byte Page Write Operation
Low Power Dissipation
•
80 mA Active Current
3 mA Standby Current
256 (32K x 8)
High Speed
CMOS
Hardware and Software Data Protection
DATA Polling for End of Write Detection
•
•
•
High Reliability CMOS Technology
Endurance: 104 or 105 Cycles
Data Retention: 10 Years
E2PROM
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wide Pinout
Full Military, Commercial, and Industrial Temperature Ranges
•
•
•
•
Description
The AT28HC256 is a high-performance Electrically Erasable and Programmable
Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256
offers access times to 70 ns with power dissipation of just 440 mW. When the
AT28HC256 is deselected, the standby current is less than 5 mA.
(continued)
Pin Configurations
Pin Name
A0 - A14
CE
Function
TSOP
Top View
Addresses
AT28HC256
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
WE
I/O0 - I/O7
NC
DC
Don’t Connect
CERDIP, PDIP,
FLATPACK
Top View
PGA
Top View
LCC, PLCC
Top View
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
0007F
2-279
Description (Continued)
The AT28HC256 is accessed like a Static RAM for the
read or write cycle without the need for external compo-
nents. The device contains a 64-byte page register to al-
low writing of up to 64-bytes simultaneously. During a
write cycle, the address and 1 to 64-bytes of data are in-
ternally latched, freeing the addresses and data bus for
other operations. Following the initiation of a write cycle,
the device will automatically write the latched data using
an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write
cycle has been detected a new access for a read or write
can begin.
Atmel’s 28HC256 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved
data retention characteristics. An optional software data
protection mechanism is available to guard against inad-
vertent writes. The device also includes an extra 64-bytes
2
of E PROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V + 0.6V
CC
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
2-280
AT28HC256
AT28HC256
Device Operation
READ: The AT28HC256 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention in their system.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes to any 5-volt-only nonvolatile memory may
occur during transition of the host system power supply.
Atmel has incorporated both hardware and software fea-
tures that will protect the memory against inadvertent
writes.
HARDWARE PROTECTION: Hardware features protect
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cy-
cle. The address is latched on the falling edge of CE or
WE, whichever occurs last. The data is latched by the first
rising edge of CE or WE. Once a byte write has been
started it will automatically time itself to completion. Once
a programming operation has been initiated and for the
against inadvertent writes to the AT28HC256 in the follow-
ing ways: (a) V sense - if V is below 3.8V (typical) the
CC
CC
write function is inhibited; (b) V power-on delay - once
CC
V
has reached 3.8V the device will automatically time
CC
out 5 ms typical) before allowing a write: (c) write inhibit -
holding any one of OE low, CE high or WE high inhibits
write cycles; (d) noise filter - pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a write cycle.
duration of t , a read operation will effectively be a poll-
WC
ing operation.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28HC256. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28HC256
is shipped from Atmel with SDP disabled.
PAGE WRITE: The page write operation of the
AT28HC256 allows 1 to 64-bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; the first byte written can then be followed by 1
to 63 additional bytes. Each successive byte must be writ-
SDP is enabled by the host system issuing a series of
three write commands; three specific bytes of data are
written to three specific addresses (refer to Software Data
Protection Algorithm). After writing the 3-byte command
ten within 150 µs (t
) of the previous byte. If the t
BLC
BLC
limit is exceeded the AT28C256 will cease accepting data
and commence the internal programming operation. All
bytes during a page write operation must reside on the
same page as defined by the state of the A6 - A14 inputs.
That is, for each WE high to low transition during the page
write operation, A6 - A14 must be the same.
sequence and after t
the entire AT28HC256 will be pro-
WC
tected against inadvertent write operations. It should be
noted, that once protected the host may still perform a
byte or page write to the AT28HC256. This is done by pre-
ceding the data to be written by the same 3-byte command
sequence.
The A0 to A5 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
Once set, SDP will remain active unless the disable com-
mand sequence is issued. Power transitions do not dis-
able SDP and SDP will protect the AT28HC256 during
power-up and power-down conditions. All command se-
quences must conform to the page write timing specifica-
tions. It should also be noted that the data in the enable
and disable command sequences is not written to the de-
vice and the memory addresses used in the sequence
may be written with data in either a byte or page write op-
eration.
DATA POLLING: The AT28HC256 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at anytime during the
write cycle.
After setting SDP, any attempt to write to the device with-
out the three byte command sequence will start the inter-
nal write timers. No data will be written to the device; how-
TOGGLE BIT: I n a d d i t i o n t o DATA Polling the
AT28HC256 provides another method for determining the
end of a write cycle. During the write operation, succes-
sive attempts to read data from the device will result in
I/O6 toggling between one and zero. Once the write has
completed, I/O6 will stop toggling and valid data will be
read. Testing the toggle bit may begin at any time during
the write cycle.
ever, for the duration of t , read operations will effec-
WC
tively be polling operations.
(continued)
2-281
Device Operation (Continued)
DEVICE IDENTIFICATION: An extra 64-bytes of
E PROM memory are available to the user for device
identification. By raising A9 to 12V ± 0.5V and using ad-
dress locations 7FC0H to 7FFFH the additional bytes may
be written to or read from in the same manner as the regu-
lar memory array.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased using a 6-byte software code. Please see Soft-
ware Chip Erase application note for details.
2
DC and AC Operating Range
AT28HC256-70
AT28HC256-90
0°C - 70°C
AT28HC256-12
0°C - 70°C
Com.
Ind.
0°C - 70°C
Operating
Temperature (Case)
-40°C - 85°C
-40°C - 85°C
-55°C - 125°C
5V ± 10%
-40°C - 85°C
-55°C - 125°C
5V ± 10%
Mil.
V
Power Supply
5V ± 10%
CC
Operating Modes
Mode
CE
OE
WE
I/O
Read
V
V
V
V
D
D
IL
IL
IH
OUT
IN
(2)
Write
V
V
IL
IH
IL
(1)
Standby/Write Inhibit
Write Inhibit
V
X
X
High Z
IH
X
X
V
IH
Write Inhibit
X
X
V
X
IL
Output Disable
Chip Erase
V
X
High Z
High Z
IH
(3)
V
V
V
IL
IL
H
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
µA
µA
mA
mA
µA
mA
V
I
LI
Input Load Current
Output Leakage Current
V
IN
= 0V to V + 1V
10
10
3
CC
I
V
I/O
= 0V to V
CC
LO
AT28HC256-90, -12
AT28HC256-70
I
V
Standby Current TTL
CE = 2.0V to V + 1V
CC
SB1
CC
60
300
80
0.8
I
I
V
V
Standby Current CMOS CE = -3.0V to V + 1V
AT28HC256-90, -12
SB2
CC
CC
CC
Active Current
f = 5 MHz; I
= 0 mA
CC
OUT
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
IL
2.0
2.4
V
IH
I
I
= 6.0 mA
.45
V
OL
OH
OL
= -4 mA
V
OH
2-282
AT28HC256
AT28HC256
AC Read Characteristics
AT28HC256-70
AT28C256-90
AT28HC256-12
Min
Max
70
70
35
35
Min
Max
90
90
40
40
Min
Max
120
120
50
Symbol Parameter
Units
ns
t
t
t
t
Address to Output Delay
CE to Output Delay
ACC
(1)
ns
CE
OE
DF
(2)
OE to Output Delay
0
0
0
0
0
0
ns
(3, 4)
CE or OE to Output Float
50
ns
Output Hold from OE, CE or
Address, whichever occurred
first
t
0
0
0
ns
OH
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
4. This parameter is characterized and is not 100% tested.
after an address change without impact on tACC
.
Output Test Load
Input Test Waveforms and
Measurement Level
t , t < 5 ns
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
6
Units
pF
Conditions
C
C
4
8
V
V
= 0V
IN
IN
12
pF
= 0V
OUT
OUT
Note: 1. This parameter is characterized and is not 100% tested.
2-283
AC Write Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
t
t
t
t
t
t
t
, t
Address, OE Set-up Time
Address Hold Time
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
AS OES
50
0
ns
AH
CS
CH
WP
DS
ns
0
ns
100
50
0
ns
ns
, t
Data, OE Hold Time
Time to Data Valid
ns
DH OEH
(1)
NR
DV
Note: 1. NR = No Restriction
AC Write Waveforms
WE Controlled
CE Controlled
2-284
AT28HC256
AT28HC256
Page Mode Write Characteristics
Symbol
Parameter
Min
Typ
Max
10
Units
ms
ms
ns
AT28HC256
5
2
t
Write Cycle Time
WC
AT28HC256F
3.0
t
t
t
t
t
t
t
Address Set-up Time
Address Hold Time
Data Set-up Time
0
50
50
0
AS
ns
AH
ns
DS
Data Hold Time
ns
DH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
ns
WP
BLC
WPH
150
µs
50
ns
Page Mode Write Waveforms (1, 2)
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
Chip Erase Waveforms
tS = tH = 5 µsec (min.)
tW = 10 msec (min.)
VH = 12.0V ± 0.5V
2-285
Software Data
Software Data
Protection Enable Algorithm (1)
Protection Disable Algorithm (1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED (2)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS (4)
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE (3)
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no
other data is loaded.
LOAD DATA XX
TO
ANY ADDRESS (4)
3. Write Protect state will be deactivated at end of write period
even if no other data is loaded.
4. 1 to 64-bytes of data are loaded.
LOAD LAST BYTE
TO
LAST ADDRESS
Software Protected Write Cycle Waveforms (1, 2)
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
2. OE must be high only when WE and CE are both low.
2-286
AT28HC256
AT28HC256
Data Polling Characteristics (1)
Symbol
Parameter
Min
0
Typ
Max
Units
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
ns
ns
ns
ns
DH
0
OEH
OE
(2)
Write Recovery Time
0
WR
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
t
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
OE High Pulse
DH
10
ns
OEH
OE
(2)
ns
150
0
ns
OEHP
WR
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit.
3. Any address location may be used but the
address should not vary.
2. Beginning and ending state of I/O6 will vary
2-287
2-288
AT28HC256
AT28HC256
Ordering Information (1)
t
I
(mA)
ACC
CC
Ordering Code
Package
Operation Range
Active Standby
(ns)
70
80
80
80
80
80
60
0.3
0.3
0.3
0.3
AT28HC256(E,F)-70JC
AT28HC256(E,F)-70PC
32J
28P6
Commercial
(0°C to 70°C)
AT28HC256(E,F)-70JI
AT28HC256(E,F)-70PI
32J
28P6
Industrial
(-40°C to 85°C)
90
AT28HC256(E,F)-90JC
AT28HC256(E,F)-90PC
32J
28P6
Commercial
(0°C to 70°C)
AT28HC256(E,F)-90JI
AT28HC256(E,F)-90PI
32J
28P6
Industrial
(-40°C to 85°C)
AT28HC256(E,F)-90DM/883
AT28HC256(E,F)-90FM/883
AT28HC256(E,F)-90LM/883
AT28HC256(E,F)-90UM/883
28D6
28F
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
28U
120
80
80
80
80
80
80
80
0.3
0.3
0.3
0.3
0.3
0.3
0.3
AT28HC256(E,F)-12JC
AT28HC256(E,F)-12PC
AT28HC256(E,F)-12SC
AT28HC256(E,F)-12TC
32J
Commercial
(0°C to 70°C)
28P6
28S
28T
AT28HC256(E,F)-12JI
AT28HC256(E,F)-12PI
AT28HC256(E,F)-12SI
AT28HC256(E,F)-12TI
32J
Industrial
(-40°C to 85°C)
28P6
28S
28T
AT28HC256(E,F)-12DM/883
AT28HC256(E,F)-12FM/883
AT28HC256(E,F)-12LM/883
AT28HC256(E,F)-12UM/883
28D6
28F
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
28U
90
5962-88634 03 UX
5962-88634 03 XX
5962-88634 03 YX
5962-88634 03 ZX
28U
28D6
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
28F
5962-88634 04 UX
5962-88634 04 XX
5962-88634 04 YX
5962-88634 04 ZX
28U
28D6
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
28F
120
5962-88634 01 UX
5962-88634 01 XX
5962-88634 01 YX
5962-88634 01 ZX
28U
28D6
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
28F
5962-88634 02 UX
5962-88634 02 XX
5962-88634 02 YX
5962-88634 02 ZX
28U
28D6
32L
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
28F
Note: 1. See Valid Part Number table below.
2-289
Ordering Information Note
Previous data sheets included the low power suffixes L, LE and LF on the AT28HC256 for 120 ns
and 90 ns speeds. The low power parameters are now standard; therefore, the L, LE and LF suffixes
are no longer required.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
AT28HC256
Speed
Package and Temperature Combinations
JC, JI, PC, PI
70
90
90
90
12
12
12
AT28HC256
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
AT28HC256E
AT28HC256F
AT28HC256
AT28HC256E
AT28HC256F
Package Type
28D6
28F
28 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip)
28 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
32J
32L
32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28 Lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC)
28 Lead, Plastic Thin Small Outline Package (TSOP)
28 Pin, Ceramic Pin Grid Array (PGA)
28P6
28S
28T
28U
Options
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
High Endurance Option: Endurance = 100K Write Cycles
Fast Write Option: Write Time = 3 ms
E
F
2-290
AT28HC256
相关型号：
AT28HC256-70FM/883
EEPROM, 32KX8, 70ns, Parallel, CMOS, CDFP28, BOTTOM BRAZED, CERAMIC, DFP-28
ATMEL
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