AT28C64E-12PJ [ATMEL]
EEPROM, 8KX8, 120ns, Parallel, CMOS, PDIP28, 0.600 INCH, PLASTIC, MS-011AB, DIP-28;
| 型号： | AT28C64E-12PJ |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 8KX8, 120ns, Parallel, CMOS, PDIP28, 0.600 INCH, PLASTIC, MS-011AB, DIP-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
•
•
Fast Read Access Time – 120 ns
Fast Byte Write – 200 µs
Self-timed Byte Write Cycle
– Internal Address and Data Latches
– Internal Control Timer
– Automatic Clear Before Write
Direct Microprocessor Control
– READY/BUSY Open Drain Output
– DATA Polling
•
•
•
64K (8K x 8)
Parallel
EEPROMs
Low Power
– 30 mA Active Current
– 100 µA CMOS Standby Current
High Reliability
– Endurance: 105 Cycles
– Data Retention: 10 Years
5V 10% Supply
AT28C64E
•
•
•
•
•
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-Free) Packaging Option
1. Description
The AT28C64E is a low-power, high-performance 8,192 words by 8-bit nonvolatile
electrically erasable and programmable read-only memory with popular, easy-to-use
features. The device is manufactured with Atmel’s reliable nonvolatile technology.
The AT28C64E is accessed like a Static RAM for the read or write cycles without the
need for external components. During a byte write, the address and data are latched
internally, freeing the microprocessor address and data bus for other operations. Fol-
lowing the initiation of a write cycle, the device will go to a busy state and
automatically clear and write the latched data using an internal control timer. The
device includes two methods for detecting the end of a write cycle, level detection of
RDY/BUSY (unless pin 1 is N.C.) and DATA Polling of I/O7. Once the end of a write
cycle has been detected, a new access for a read or write can begin.
The CMOS technology offers fast access times of 120 ns at low power dissipation.
When the chip is deselected, the standby current is less than 100 µA.
Atmel’s AT28C64E has additional features to ensure high quality and manufacturabil-
ity. The device utilizes error correction internally for extended endurance and for
improved data retention characteristics. An extra 32 bytes of EEPROM are available
for device identification or tracking.
0001I–PEEPR–10/06
2.2
TSOP Top View
2. Pin Configurations
Pin Name
A0 - A12
CE
Function
OE
A11
A9
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
2
Addresses
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
Chip Enable
A8
4
NC
5
OE
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy Output
No Connect
WE
VCC
6
WE
7
RDY/BUSY (or NC)
8
I/O0 - I/O7
RDY/BUSY
NC
A12
A7
A6
A5
A4
A3
9
10
11
12
13
14
A1
DC
Don’t Connect
A2
2.3
LCC, PLCC Top View
2.1
PDIP, SOIC Top View
RDY/BUSY (or NC)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A12
A7
2
3
A6
4
A8
A5
5
A9
A4
6
A11
OE
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
A3
7
A2
8
A10
CE
A1
9
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A1 10
A0 11
I/O0
I/O1
I/O2
GND
NC 12
I/O0 13
Note:
PLCC package pins 1 and 17 are DON’T CONNECT.
2
AT28C64E
0001I–PEEPR–10/06
AT28C64E
3. Block Diagram
4. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground...................................-0.6V to +13.5V
3
0001I–PEEPR–10/06
5. Device Operation
5.1
Read
The AT28C64E is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in a high impedance state whenever CE or OE is high. This dual line control
gives designers increased flexibility in preventing bus contention.
5.2
Byte Write
Writing data into the AT28C64E is similar to writing into a Static RAM. A low pulse on the WE or
CE input with OE high and CE or WE low (respectively) initiates a byte write. The address loca-
tion is latched on the falling edge of WE (or CE); the new data is latched on the rising edge.
Internally, the device performs a self-clear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated and
for the duration of tWC, a read operation will effectively be a polling operation.
5.3
5.4
Fast Byte Write
The AT28C64E offers a byte write time of 200 µs maximum. This feature allows the entire
device to be rewritten in 1.6 seconds.
READY/BUSY
Data Polling
Pin 1 is an open drain RDY/BUSY output that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle and is released at the completion of
the write. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY line.
5.5
5.6
The AT28C64E provides DATA Polling to signal the completion of a write cycle. During a
write cycle, an attempted read of the data being written results in the complement of that data for
I/O7 (the other outputs are indeterminate). When the write cycle is finished, true data appears on
all outputs.
Write Protection
Inadvertent writes to the device are protected against in the following ways: (a) VCC sense – if
V
CC is below 3.8V (typical), the write function is inhibited; (b) VCC power on delay – once VCC has
reached 3.8V, the device will automatically time out 5 ms (typical) before allowing a byte write;
and (c) write inhibit – holding any one of OE low, CE high or WE high inhibits byte write cycles.
5.7
5.8
Chip Clear
The contents of the entire memory of the AT28C64E may be set to the high state by the CHIP
CLEAR operation. By setting CE low and OE to 12 volts, the chip is cleared when a 10 msec low
pulse is applied to WE.
Device Identification
An extra 32 bytes of EEPROM memory are available to the user for device identification. By rais-
ing A9 to 12 0.5V and using address locations 1FE0H to 1FFFH the additional bytes may be
written to or read from in the same manner as the regular memory array.
4
AT28C64E
0001I–PEEPR–10/06
AT28C64E
6. DC and AC Operating Range
AT28C64E-12
-40°C - 85°C
5V 10%
Operating Temperature (Case)
V
CC Power Supply
7. Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
I/O
DOUT
DIN
Read
Write(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
High Z
VIH
X
X
VIL
VIH
X
X
High Z
High Z
(3)
Chip Erase
VIL
VH
VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V 0.5V.
8. DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
ILI
Input Load Current
VIN = 0V to VCC + 1V
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VI/O = 0V to VCC
10
µA
ISB1
CE = VCC - 0.3V to VCC + 1.0V
CE = 2.0V to VCC + 1.0V
100
3
µA
ISB2
mA
f = 5 MHz; IOUT = 0 mA
CE = VIL
ICC
VCC Active Current AC
45
mA
VIL
VIH
Input Low Voltage
Input High Voltage
0.8
V
V
2.0
2.4
I
OL = 2.1 mA
VOL
VOH
Output Low Voltage
Output High Voltage
0.45
V
V
= 4.0 mA for RDY/BUSY
IOH = -400 µA
5
0001I–PEEPR–10/06
9. AC Read Characteristics
AT28C64E-12
Symbol
Parameter
Min
Max
Units
ns
tACC
Address to Output Delay
120
120
60
(1)
tCE
CE to Output Delay
ns
(2)
tOE
OE to Output Delay
10
0
ns
(3)(4)
tDF
CE or OE High to Output Float
Output Hold from OE, CE or Address, whichever occurred first
45
ns
tOH
0
ns
10. AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
6
AT28C64E
0001I–PEEPR–10/06
AT28C64E
11. Input Test Waveforms and Measurement Level
tR, tF < 20 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
7
0001I–PEEPR–10/06
14. AC Write Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
10
50
100
50
10
0
Max
Units
ns
Address, OE Setup Time
Address Hold Time
ns
tWP
Write Pulse Width (WE or CE)
Data Setup Time
1000
ns
tDS
ns
tDH, tOEH
tCS, tCH
tDB
Data, OE Hold Time
ns
CE to WE and WE to CE Setup and Hold Time
Time to Device Busy
ns
50
ns
tWC
Write Cycle Time
200
µs
15. AC Write Waveforms
15.1 WE Controlled
15.2 CE Controlled
8
AT28C64E
0001I–PEEPR–10/06
AT28C64E
16. Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics”.
17. Data Polling Waveforms
18. Chip Erase Waveforms
tS = tH = 1 µsec (min.)
tW = 10 msec (min.)
VH = 12.0 0.5V
9
0001I–PEEPR–10/06
10
AT28C64E
0001I–PEEPR–10/06
AT28C64E
19. Ordering Information
19.1 Standard Package
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
120
45
0.1
AT28C64E-12JI
AT28C64E-12PI
AT28C64E-12SI
AT28C64E-12TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
19.2 Green Package (Pb/Halide-free)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
120
45
0.1
AT28C64E-12JU
AT28C64E-12PU
AT28C64E-12SU
AT28C64E-12TU
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
19.3 Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6
28S
28T
28-lead, 0.600" Wide, Plastic Dull Inline Package (PDIP)
28-lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC)
28-lead, Plastic Thin Small Outline Package (TSOP)
20. Valid Part Numbers
The following table lists standard Atmel® products that can be ordered.
Device Numbers
AT28C64E
Speed
Package and Temperature Combinations
JI, JU, PI, PU, SI, SU, TI, TU
12
21. Die Products
Reference Section: Parallel EEPROM Die Products
11
0001I–PEEPR–10/06
22. Packaging Information
22.1 32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
12
AT28C64E
0001I–PEEPR–10/06
AT28C64E
22.2 28P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
36.703
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
37.338 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AB.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
28P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
13
0001I–PEEPR–10/06
22.3 28S – SOIC
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
0.51(0.020)
0.33(0.013)
7.60(0.2992)
7.40(0.2914)
10.65(0.419)
10.00(0.394)
PIN 1
1.27(0.50) BSC
TOP VIEW
18.10(0.7125)
17.70(0.6969)
2.65(0.1043)
2.35(0.0926)
0.30(0.0118)
0.10(0.0040)
SIDE VIEWS
0.32(0.0125)
0.23(0.0091)
0º ~ 8º
1.27(0.050)
0.40(0.016)
8/4/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC)
JEDEC Standard MS-013
28S
B
R
14
AT28C64E
0001I–PEEPR–10/06
AT28C64E
22.4 28T – TSOP
PIN 1
0º ~ 5º
c
Pin 1 Identifier Area
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
13.60
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.90
13.20
11.70
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
13.40
11.80
8.00
D1
E
11.90 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.55 BASIC
12/06/02
DRAWING NO. REV.
28T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
C
R
15
0001I–PEEPR–10/06
Atmel Corporation
Atmel Operations
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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0001I–PEEPR–10/06
相关型号：
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