AT28C64B-25JC [ATMEL]
64K (8K x 8) Parallel EEPROM with Page Write and Software Data Protection; 64K （ 8K ×8）并行EEPROM与页写入和软件数据保护
| 型号： | AT28C64B-25JC |
| 厂家： | 
ATMEL |
| 描述： | 64K (8K x 8) Parallel EEPROM with Page Write and Software Data Protection |
| 文件： | 总13页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 150 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
• Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum
– 1 to 64-byte Page Write Operation
• Low Power Dissipation
– 40 mA Active Current
– 100 µA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling and Toggle Bit for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 100,000 Cycles
64K (8K x 8)
Parallel
– Data Retention: 10 Years
EEPROM with
Page Write and
Software Data
Protection
• Single 5V 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
• Commercial and Industrial Temperature Ranges
Description
The AT28C64B is a high-performance electrically-erasable and programmable read
only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 150 ns with power dissipation of just 220 mW. When the device is
AT28C64B
deselected, the CMOS standby current is less than 100 µA.
(continued)
Pin Configurations
PDIP, SOIC
Top View
Pin Name
A0 - A12
CE
Function
NC
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
Addresses
2
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
3
A6
4
A8
OE
A5
5
A9
A4
6
A11
OE
WE
A3
7
A2
8
A10
CE
I/O0 - I/O7
NC
A1
9
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
GND
DC
Don’t Connect
PLCC
Top View
TSOP
Top View
OE
A11
A9
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A8
4
NC
WE
VCC
NC
A12
A7
5
6
A1 10
A0 11
7
8
NC 12
I/O0 13
9
10
11
12
13
14
A6
A5
A4
A1
Rev. 0270H–12/99
A3
A2
Note:
PLCC package pins 1 and 17 are
DON’T CONNECT.
The AT28C64B is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 64-byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
addresses and 1 to 64 bytes of data are internally latched,
freeing the address and data bus for other operations. Fol-
lowing the initiation of a write cycle, the device will automat-
ically write the latched data using an internal control timer.
The end of a write cycle can be detected by DATA POLL-
ING of I/O7. Once the end of a write cycle has been
detected, a new access for a read or write can begin.
Atmel’s AT28C64B has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention characteristics. An optional software data protec-
tion mechanism is available to guard against inadvertent
writes. The device also includes an extra 64 bytes of
EEPROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground...................................-0.6V to +13.5V
AT28C64B
2
AT28C64B
Device Operation
READ: The AT28C64B is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high-
impedance state when either CE or OE is high. This dual
line control gives designers flexibility in preventing bus con-
tention in their systems.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent writes to the AT28C64B in the
following ways: (a) VCC sense – if VCC is below 3.8V (typi-
cal), the write function is inhibited; (b) VCC power-on delay
– once VCC has reached 3.8V, the device will automatically
time out 5 ms (typical) before allowing a write; (c) write
inhibit – holding any one of OE low, CE high, or WE high
inhibits write cycles; and (d) noise filter – pulses of less
than 15 ns (typical) on the WE or CE inputs will not initiate
a write cycle.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cycle.
The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising
edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the duration
of tWC, a read operation will effectively be a polling
operation.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28C64B. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C64B is
shipped from Atmel with SDP disabled.
PAGE WRITE: The page write operation of the AT28C64B
allows 1 to 64 bytes of data to be written into the device
during a single internal programming period. A page write
operation is initiated in the same manner as a byte write;
after the first byte is written, it can then be followed by 1 to
63 additional bytes. Each successive byte must be loaded
within 150 µs (tBLC) of the previous byte. If the tBLC limit is
exceeded, the AT28C64B will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A6 to A12 inputs. For
each WE high to low transition during the page write opera-
tion, A6 to A12 must be the same.
SDP is enabled by the user issuing a series of three write
commands in which three specific bytes of data are written
to three specific addresses (refer to the “Software Data
Protection Algorithm” diagram in this datasheet). After writ-
ing the 3-byte command sequence and waiting tWC, the
entire AT28C64B will be protected against inadvertent
writes. It should be noted that even after SDP is enabled,
the user may still perform a byte or page write to the
AT28C64B by preceding the data to be written by the same
3-byte command sequence used to enable SDP.
The A0 to A5 inputs specify which bytes within the page are
to be written. The bytes may be loaded in any order and
may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.
Once set, SDP remains active unless the disable command
sequence is issued. Power transitions do not disable SDP,
and SDP protects the AT28C64B during power-up and
power-down conditions. All command sequences must
conform to the page write timing specifications. The data in
the enable and disable command sequences is not actually
written into the device; their addresses may still be written
with user data in either a byte or page write operation.
DATA POLLING: The AT28C64B features DATA Polling to
indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at any time during the write
cycle.
After setting SDP, any attempt to write to the device without
the 3-byte command sequence will start the internal write
timers. No data will be written to the device. However, for
the duration of tWC, read operations will effectively be poll-
ing operations.
TOGGLE BIT: In addition to DATA Polling, the AT28C64B
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop toggling, and valid data will be read. Toggle bit
reading may begin at any time during the write cycle.
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM
memory are available to the user for device identification.
By raising A9 to 12V 0.5V and using address locations
1FC0H to 1FFFH, the additional bytes may be written to or
read from in the same manner as the regular memory
array.
3
DC and AC Operating Range
AT28C64B-15
0°C - 70°C
-40°C - 85°C
5V 10%
AT28C64B-20
0°C - 70°C
-40°C - 85°C
5V 10%
AT28C64B-25
0°C - 70°C
-40°C - 85°C
5V 10%
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
I/O
DOUT
DIN
Read
Write(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
High Z
VIH
X
X
VIL
VIH
X
X
High Z
High Z
(3)
Chip Erase
VIL
VH
VIL
Notes: 1. X can be VIL or VIH.
2. Refer to the “AC Write Waveforms” diagrams in this datasheet.
3. VH = 12.0V 0.5V.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
10
10
100
2
ILO
ISB1
ISB2
ICC
CE = VCC - 0.3V to VCC + 1V Com., Ind.
CE = 2.0V to VCC + 1V
f = 5 MHz; IOUT = 0 mA
40
0.8
VIL
VIH
Input High Voltage
2.0
2.4
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
IOH = -400 µA
0.40
V
V
AT28C64B
4
AT28C64B
AC Read Characteristics
AT28C64B-15
AT28C64B-20
AT28C64B-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
150
150
70
200
200
80
250
250
100
60
(1)
tCE
ns
(2)
tOE
0
0
0
0
0
0
ns
(3)(4)
tDF
50
55
ns
Output Hold from OE, CE or
Address, whichever occurred first
tOH
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Setup Time
tAH
tCS
tCH
tWP
tDS
50
0
ns
ns
0
ns
100
50
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
ns
AC Write Waveforms
WE Controlled
CE Controlled
AT28C64B
6
AT28C64B
Page Mode Characteristics
Symbol
Parameter
Min
Max
Units
tWC
Write Cycle Time
10
ms
Write Cycle Time (option available; contact Atmel sales office for
ordering part number)
tWC
0
2
ms
tAS
Address Setup Time
Address Hold Time
Data Setup Time
0
50
50
0
ns
ns
ns
ns
ns
µs
ns
tAH
tDS
tDH
Data Hold Time
tWP
tBLC
tWPH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
150
50
Page Mode Write Waveforms(1)(2)
Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
Chip Erase Waveforms
tS = tH = 1 µsec (min.)
t
W = 10 msec (min.)
VH = 12.0 0.5V
7
Software Data Protection
Enable Algorithm(1)
Software Data Protection
Disable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 1555
ADDRESS 1555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 0AAA
ADDRESS 0AAA
LOAD DATA A0
TO
LOAD DATA 80
TO
ADDRESS 1555
ADDRESS 1555
WRITES ENABLED(2)
LOAD DATA XX
TO
LOAD DATA AA
TO
ANY ADDRESS(4)
ADDRESS 1555
LOAD LAST BYTE
TO
LOAD DATA 55
TO
LAST ADDRESS
ADDRESS 0AAA
ENTER DATA
PROTECT STATE
LOAD DATA 20
TO
Notes for software program code:
ADDRESS 1555
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A12 - A0 (Hex).
EXIT DATA
PROTECT STATE(3)
LOAD DATA XX
TO
ANY ADDRESS(4)
2. Write Protect state will be activated at end of
write even if no other data is loaded.
3. Write Protect state will be deactivated at end of
write period even if no other data is loaded.
LOAD LAST BYTE
TO
4. 1 to 64 bytes of data are loaded.
LAST ADDRESS
Software Protected Write Cycle Waveforms(1)(2)
Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
2. OE must be high only when WE and CE are both low.
AT28C64B
8
AT28C64B
Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
0
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics”.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics”.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
AT28C64B
10
AT28C64B
Ordering Information(1)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
150
200
250
40
0.1
AT28C64B-15JC
AT28C64B-15PC
AT28C64B-15SC
AT28C64B-15TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28C64B-15JI
AT28C64B-15PI
AT28C64B-15SI
AT28C64B-15TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
40
0.1
AT28C64B-20JC
AT28C64B-20PC
AT28C64B-20SC
AT28C64B-20TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28C64B-20JI
AT28C64B-20PI
AT28C64B-20SI
AT28C64B-20TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
40
0.1
AT28C64B-25JC
AT28C64B-25PC
AT28C64B-25SC
AT28C64B-25TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28C64B-25JI
AT28C64B-25PI
AT28C64B-25SI
AT28C64B-25TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
Note:
1. See “Valid Part Numbers” table below.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
AT28C64B
Speed
15
Package and Temperature Combinations
JC, JI, PC, PI, SC, SI, TC, TI
JC, JI, PC, PI, SC, SI, TC, TI
JC, JI, PC, PI, SC, SI, TC, TI
W
AT28C64B
20
AT28C64B
25
AT28C64B
–
Die Products
Reference Section: Parallel EEPROM Die Products
Package Type
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
28P6
28S
28T
W
28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28-lead, Plastic Thin Small Outline Package (TSOP)
Die
11
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6, 28-lead, 0.600" Wide, Plastic Dual Inline
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB
1.47(37.3)
1.44(36.6)
PIN
1
.025(.635) X 30˚ - 45˚
.045(1.14) X 45˚ PIN NO. 1
.012(.305)
.008(.203)
IDENTIFY
.566(14.4)
.530(13.5)
.530(13.5)
.553(14.0)
.490(12.4)
.547(13.9)
.032(.813)
.021(.533)
.013(.330)
.595(15.1)
.026(.660)
.090(2.29)
MAX
.585(14.9)
1.300(33.02) REF
.220(5.59)
MAX
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.005(.127)
MIN
.050(1.27) TYP
.300(7.62) REF
.430(10.9)
.390(9.90)
SEATING
PLANE
AT CONTACT
POINTS
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.022(.559) X 45˚ MAX (3X)
.630(16.0)
.590(15.0)
.453(11.5)
.447(11.4)
0
15
REF
.495(12.6)
.485(12.3)
.012(.305)
.008(.203)
.690(17.5)
.610(15.5)
28S, 28-lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
28T, 28-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Inches and (Millimeters)
Dimensions in Millimeters and (Inches)*
INDEX
MARK
AREA
13.7 (0.539)
13.1 (0.516)
11.9 (0.469)
11.7 (0.461)
0.27 (0.011)
0.18 (0.007)
0.55 (0.022)
BSC
7.15 (0.281)
REF
8.10 (0.319)
7.90 (0.311)
1.25 (0.049)
1.05 (0.041)
0.20 (0.008)
0.10 (0.004)
0
REF
5
0.20 (0.008)
0.15 (0.006)
0.70 (0.028)
0.30 (0.012)
AT28C64B
12
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© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
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®
™
Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.
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Printed on recycled paper.
0270H–12/99/xM
相关型号：
AT28C64B-25PL
EEPROM, 8KX8, 250ns, Parallel, CMOS, PDIP28, 0.600 INCH, PLASTIC, MS-011AB, DIP-28
ATMEL
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