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AT28C256-20PL [ATMEL]

EEPROM, 32KX8, 200ns, Parallel, CMOS, PDIP28, 0.600 INCH, PLASTIC, MS-011AB, DIP-28;
AT28C256-20PL
型号： AT28C256-20PL
厂家： ATMEL    ATMEL
描述：

EEPROM, 32KX8, 200ns, Parallel, CMOS, PDIP28, 0.600 INCH, PLASTIC, MS-011AB, DIP-28

可编程只读存储器
文件： 总14页 (文件大小：765K)
中文：  中文翻译
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AT28C256  
Features  
Fast Read Access Time - 150 ns  
Automatic Page Write Operation  
•
•
Internal Address and Data Latches for 64-Bytes  
Internal Control Timer  
Fast Write Cycle Times  
•
Page Write Cycle Time: 3 ms or 10 ms Maximum  
1 to 64-Byte Page Write Operation  
Low Power Dissipation  
•
50 mA Active Current  
256K (32K x 8)  
Paged  
200 µA CMOS Standby Current  
Hardware and Software Data Protection  
DATA Polling for End of Write Detection  
•
•
•
High Reliability CMOS Technology  
Endurance: 104 or 105 Cycles  
Data Retention: 10 Years  
CMOS  
E2PROM  
Single 5V ± 10% Supply  
CMOS and TTL Compatible Inputs and Outputs  
JEDEC Approved Byte-Wide Pinout  
Full Military, Commercial, and Industrial Temperature Ranges  
•
•
•
•
Description  
The AT28C256 is a high-performance Electrically Erasable and Programmable Read  
Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-  
tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access  
times to 150 ns with power dissipation of just 440 mW. When the device is deselected,  
the CMOS standby current is less than 200 µA.  
(continued)  
Pin Configurations  
TSOP  
Top View  
Pin Name  
A0 - A14  
CE  
Function  
AT28C256  
Addresses  
Chip Enable  
Output Enable  
Write Enable  
Data Inputs/Outputs  
No Connect  
OE  
WE  
I/O0 - I/O7  
NC  
DC  
Don’t Connect  
CERDIP, PDIP,  
FLATPACK, SOIC  
Top View  
LCC, PLCC  
Top View  
PGA  
Top View  
Note: PLCC package pins 1 and  
17 are DON’T CONNECT.  
0006F  
2-217  
Description (Continued)  
The AT28C256 is accessed like a Static RAM for the read  
or write cycle without the need for external components.  
The device contains a 64-byte page register to allow writ-  
ing of up to 64-bytes simultaneously. During a write cycle,  
the addresses and 1 to 64-bytes of data are internally  
latched, freeing the address and data bus for other opera-  
tions. Following the initiation of a write cycle, the device  
will automatically write the latched data using an internal  
control timer. The end of a write cycle can be detected by  
DATA POLLING of I/O7. Once the end of a write cycle has  
been detected a new access for a read or write can begin.  
Atmel’s 28C256 has additional features to ensure high  
quality and manufacturability. The device utilizes internal  
error correction for extended endurance and improved  
data retention characteristics. An optional software data  
protection mechanism is available to guard against inad-  
vertent writes. The device also includes an extra 64-bytes  
2
of E PROM for device identification or tracking.  
Block Diagram  
Absolute Maximum Ratings*  
*NOTICE: Stresses beyond those listed under “Absolute Maxi-  
mum Ratings” may cause permanent damage to the device.  
This is a stress rating only and functional operation of the  
device at these or any other conditions beyond those indi-  
cated in the operational sections of this specification is not  
implied. Exposure to absolute maximum rating conditions  
for extended periods may affect device reliability.  
Temperature Under Bias................. -55°C to +125°C  
Storage Temperature...................... -65°C to +150°C  
All Input Voltages  
(including NC Pins)  
with Respect to Ground ................... -0.6V to +6.25V  
All Output Voltages  
with Respect to Ground .............-0.6V to V + 0.6V  
CC  
Voltage on OE and A9  
with Respect to Ground ................... -0.6V to +13.5V  
2-218  
AT28C256  
AT28C256  
Device Operation  
READ: The AT28C256 is accessed like a Static RAM.  
When CE and OE are low and WE is high, the data stored  
at the memory location determined by the address pins is  
asserted on the outputs. The outputs are put in the high  
impedance state when either CE or OE is high. This dual-  
line control gives designers flexibility in preventing bus  
contention in their system.  
DATA PROTECTION: If precautions are not taken, inad-  
vertent writes may occur during transitions of the host sys-  
tem power supply. Atmel has incorporated both hardware  
and software features that will protect the memory against  
inadvertent writes.  
HARDWARE PROTECTION: Hardware features protect  
against inadvertent writes to the AT28C256 in the follow-  
BYTE WRITE: A low pulse on the WE or CE input with CE  
or WE low (respectively) and OE high initiates a write cy-  
cle. The address is latched on the falling edge of CE or  
WE, whichever occurs last. The data is latched by the first  
rising edge of CE or WE. Once a byte write has been  
started it will automatically time itself to completion. Once  
a programming operation has been initiated and for the  
ing ways: (a) V sense - if V is below 3.8V (typical) the  
CC CC  
write function is inhibited; (b) V power-on delay - once  
CC  
V
has reached 3.8V the device will automatically time  
CC  
out 5 ms (typical) before allowing a write: (c) write inhibit -  
holding any one of OE low, CE high or WE high inhibits  
write cycles; (d) noise filter - pulses of less than 15 ns (typi-  
cal) on the WE or CE inputs will not initiate a write cycle.  
duration of t , a read operation will effectively be a poll-  
ing operation.  
WC  
SOFTWARE DATA PROTECTION: A software controlled  
data protection feature has been implemented on the  
AT28C256. When enabled, the software data protection  
(SDP), will prevent inadvertent writes. The SDP feature  
may be enabled or disabled by the user; the AT28C256 is  
shipped from Atmel with SDP disabled.  
PAGE WRITE: The page write operation of the AT28C256  
allows 1 to 64-bytes of data to be written into the device  
during a single internal programming period. A page write  
operation is initiated in the same manner as a byte write;  
the first byte written can then be followed by 1 to 63 addi-  
tional bytes. Each successive byte must be written within  
SDP is enabled by the host system issuing a series of  
three write commands; three specific bytes of data are  
written to three specific addresses (refer to Software Data  
Protection Algorithm). After writing the 3-byte command  
150 µs (t  
) of the previous byte. If the t  
limit is ex-  
BLC  
BLC  
ceeded the AT28C256 will cease accepting data and com-  
mence the internal programming operation. All bytes dur-  
ing a page write operation must reside on the same page  
as defined by the state of the A6 - A14 inputs. For each  
WE high to low transition during the page write operation,  
A6 - A14 must be the same.  
sequence and after t  
the entire AT28C256 will be pro-  
WC  
tected against inadvertent write operations. It should be  
noted, that once protected the host may still perform a  
byte or page write to the AT28C256. This is done by pre-  
ceding the data to be written by the same 3-byte command  
sequence used to enable SDP.  
The A0 to A5 inputs are used to specify which bytes within  
the page are to be written. The bytes may be loaded in any  
order and may be altered within the same load period.  
Only bytes which are specified for writing will be written;  
unnecessary cycling of other bytes within the page does  
not occur.  
Once set, SDP will remain active unless the disable com-  
mand sequence is issued. Power transitions do not dis-  
able SDP and SDP will protect the AT28C256 during  
power-up and power-down conditions. All command se-  
quences must conform to the page write timing specifica-  
tions. The data in the enable and disable command se-  
quences is not written to the device and the memory ad-  
dresses used in the sequence may be written with data in  
either a byte or page write operation.  
DATA POLLING: The AT28C256 features DATA Polling  
to indicate the end of a write cycle. During a byte or page  
write cycle an attempted read of the last byte written will  
result in the complement of the written data to be pre-  
sented on I/O7. Once the write cycle has been completed,  
true data is valid on all outputs, and the next write cycle  
may begin. DATA Polling may begin at anytime during the  
write cycle.  
After setting SDP, any attempt to write to the device with-  
out the 3-byte command sequence will start the internal  
write timers. No data will be written to the device; however,  
for the duration of t , read operations will effectively be  
WC  
polling operations.  
TOGGLE BIT: In addition to DATA Polling the AT28C256  
provides another method for determining the end of a write  
cycle. During the write operation, successive attempts to  
read data from the device will result in I/O6 toggling be-  
tween one and zero. Once the write has completed, I/O6  
will stop toggling and valid data will be read. Reading the  
toggle bit may begin at any time during the write cycle.  
(continued)  
2-219  
Device Operation (Continued)  
DEVICE IDENTIFICATION: An extra 64-bytes of  
E PROM memory are available to the user for device  
identification. By raising A9 to 12V ± 0.5V and using ad-  
dress locations 7FC0H to 7FFFH the additional bytes may  
be written to or read from in the same manner as the regu-  
lar memory array.  
OPTIONAL CHIP ERASE MODE: The entire device can  
be erased using a 6-byte software code. Please see Soft-  
ware Chip Erase application note for details.  
2
DC and AC Operating Range  
AT28C256-15  
AT28C256-20  
0°C - 70°C  
AT28C256-25  
0°C - 70°C  
AT28C256-35  
Com.  
Ind.  
0°C - 70°C  
-40°C - 85°C  
-55°C - 125°C  
5V ± 10%  
Operating  
Temperature (Case)  
-40°C - 85°C  
-55°C - 125°C  
5V ± 10%  
-40°C - 85°C  
-55°C - 125°C  
5V ± 10%  
Mil.  
-55°C - 125°C  
V
Power Supply  
5V ± 10%  
CC  
Operating Modes  
Mode  
CE  
OE  
WE  
I/O  
Read  
V
V
V
V
D
D
IL  
IL  
IH  
IL  
IH  
OUT  
IN  
(2)  
Write  
V
V
IH  
IL  
(1)  
Standby/Write Inhibit  
Write Inhibit  
V
X
X
High Z  
X
X
V
IH  
Write Inhibit  
X
X
V
X
IL  
Output Disable  
Chip Erase  
V
X
High Z  
High Z  
IH  
(3)  
V
V
V
IL  
IL  
H
Notes: 1. X can be VIL or VIH.  
3. VH = 12.0V ± 0.5V.  
2. Refer to AC Programming Waveforms.  
DC Characteristics  
Symbol  
Parameter  
Condition  
Min  
Max  
10  
Units  
µA  
µA  
µA  
µA  
mA  
mA  
V
I
I
Input Load Current  
Output Leakage Current  
V
V
= 0V to V + 1V  
CC  
LI  
IN  
= 0V to V  
CC  
10  
LO  
I/O  
Com., Ind.  
Mil.  
200  
300  
3
I
V
Standby Current CMOS  
CE = V - 0.3V to V + 1V  
CC CC  
SB1  
CC  
I
I
V
V
Standby Current TTL  
Active Current  
CE = 2.0V to V + 1V  
CC  
SB2  
CC  
CC  
f = 5 MHz; I  
= 0 mA  
50  
CC  
OUT  
V
V
V
V
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
0.8  
IL  
2.0  
2.4  
V
IH  
I
I
= 2.1 mA  
.45  
V
OL  
OH  
OL  
= -400 µA  
V
OH  
2-220  
AT28C256  
AT28C256  
AC Read Characteristics  
AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35  
Min  
Max  
150  
150  
70  
Min  
Max  
200  
200  
80  
Min  
Max  
250  
250  
100  
60  
Min  
Max  
350  
350  
100  
70  
Symbol  
Parameter  
Units  
ns  
t
t
t
t
Address to Output Delay  
CE to Output Delay  
OE to Output Delay  
CE or OE to Output Float  
ACC  
(1)  
ns  
CE  
OE  
DF  
(2)  
0
0
0
0
0
0
0
0
ns  
(3, 4)  
50  
55  
ns  
Output Hold from OE, CE or  
Address, whichever  
occurred first  
t
0
0
0
0
ns  
OH  
AC Read Waveforms (1, 2, 3, 4)  
3. tDF is specified from OE or CE whichever occurs first  
(CL = 5 pF).  
Notes: 1. CE may be delayed up to tACC - tCE after the address  
transition without impact on tACC  
.
4. This parameter is characterized and is not 100% tested.  
2. OE may be delayed up to tCE - tOE after the falling  
edge of CE without impact on tCE or by tACC - tOE  
after an address change without impact on tACC  
.
Input Test Waveforms and  
Measurement Level  
Output Test Load  
t , t < 5ns  
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)  
Typ  
Max  
6
Units  
pF  
Conditions  
C
C
4
8
V
V
= 0V  
IN  
IN  
12  
pF  
= 0V  
OUT  
OUT  
Note: 1. This parameter is characterized and is not 100% tested.  
2-221  
AC Write Characteristics  
Symbol  
Parameter  
Min  
0
Max  
Units  
ns  
t
t
t
t
t
t
t
t
, t  
Address, OE Set-up Time  
Address Hold Time  
Chip Select Set-up Time  
Chip Select Hold Time  
Write Pulse Width (WE or CE)  
Data Set-up Time  
AS OES  
50  
0
ns  
AH  
CS  
CH  
WP  
DS  
ns  
0
ns  
100  
50  
0
ns  
ns  
, t  
Data, OE Hold Time  
Time to Data Valid  
ns  
DH OEH  
(1)  
NR  
DV  
Note: 1. NR = No Restriction  
AC Write Waveforms  
WE Controlled  
CE Controlled  
2-222  
AT28C256  
AT28C256  
Page Mode Characteristics  
Symbol  
Parameter  
Min  
Max  
10  
Units  
ms  
ms  
ns  
AT28C256  
t
Write Cycle Time  
WC  
AT28C256F  
3.0  
t
t
t
t
t
t
t
Address Set-up Time  
Address Hold Time  
Data Set-up Time  
0
50  
50  
0
AS  
ns  
AH  
ns  
DS  
Data Hold Time  
ns  
DH  
Write Pulse Width  
Byte Load Cycle Time  
Write Pulse Width High  
100  
ns  
WP  
BLC  
WPH  
150  
µs  
50  
ns  
Page Mode Write Waveforms (1, 2)  
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE).  
2. OE must be high only when WE and CE are both low.  
Chip Erase Waveforms  
tS = tH = 5 µsec (min.)  
tW = 10 msec (min.)  
VH = 12.0V ± 0.5V  
2-223  
Software Data  
Software Data  
Protection Enable Algorithm (1)  
Protection Disable Algorithm (1)  
LOAD DATA AA  
TO  
LOAD DATA AA  
TO  
ADDRESS 5555  
ADDRESS 5555  
LOAD DATA 55  
TO  
LOAD DATA 55  
TO  
ADDRESS 2AAA  
ADDRESS 2AAA  
LOAD DATA 80  
TO  
ADDRESS 5555  
LOAD DATA A0  
TO  
ADDRESS 5555  
WRITES ENABLED (2)  
LOAD DATA AA  
TO  
ADDRESS 5555  
LOAD DATA XX  
TO  
ANY ADDRESS (4)  
LOAD DATA 55  
TO  
ADDRESS 2AAA  
LOAD LAST BYTE  
TO  
LAST ADDRESS  
ENTER DATA  
PROTECT STATE  
LOAD DATA 20  
TO  
ADDRESS 5555  
EXIT DATA  
PROTECT STATE (3)  
Notes for software program code:  
1. Data Format: I/O7 - I/O0 (Hex);  
Address Format: A14 - A0 (Hex).  
2. Write Protect state will be activated at end of write even if no  
other data is loaded.  
LOAD DATA XX  
TO  
ANY ADDRESS (4)  
3. Write Protect state will be deactivated at end of write period  
even if no other data is loaded.  
4. 1 to 64-bytes of data are loaded.  
LOAD LAST BYTE  
TO  
LAST ADDRESS  
Software Protected Write Cycle Waveforms (1, 2)  
Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after  
the software code has been entered.  
2. OE must be high only when WE and CE are both low.  
2-224  
AT28C256  
AT28C256  
Data Polling Characteristics (1)  
Symbol  
Parameter  
Min  
0
Typ  
Max  
Units  
ns  
t
t
t
t
Data Hold Time  
OE Hold Time  
OE to Output Delay  
DH  
0
ns  
OEH  
OE  
(2)  
ns  
Write Recovery Time  
0
ns  
WR  
Notes: 1. These parameters are characterized and not 100% tested.  
2. See AC Read Characteristics.  
Data Polling Waveforms  
Toggle Bit Characteristics (1)  
Symbol  
Parameter  
Min  
10  
Typ  
Max  
Units  
ns  
t
t
t
t
t
Data Hold Time  
OE Hold Time  
OE to Output Delay  
OE High Pulse  
DH  
10  
ns  
OEH  
OE  
(2)  
ns  
150  
0
ns  
OEHP  
WR  
Write Recovery Time  
ns  
2. See AC Read Characteristics.  
Notes: 1. These parameters are characterized and not 100% tested.  
Toggle Bit Waveforms (1, 2, 3)  
3. Any address location may be used but the address  
should not vary.  
Notes: 1. Toggling either OE or CE or both OE and CE will  
operate toggle bit.  
2. Beginning and ending state of I/O6 will vary.  
2-225  
2-226  
AT28C256  
AT28C256  
Ordering Information (2)  
t
I
(mA)  
ACC  
CC  
Ordering Code  
Package  
Operation Range  
Active Standby  
(ns)  
150  
50  
0.2  
AT28C256(E,F)-15JC  
AT28C256(E,F)-15PC  
AT28C256(E,F)-15SC  
AT28C256(E,F)-15TC  
32J  
Commercial  
(0°C to 70°C)  
28P6  
28S  
28T  
AT28C256(E,F)-15JI  
AT28C256(E,F)-15PI  
AT28C256(E,F)-15SI  
AT28C256(E,F)-15TI  
32J  
Industrial  
(-40°C to 85°C)  
28P6  
28S  
28T  
50  
50  
0.3  
0.2  
AT28C256(E,F)-15DM/883  
AT28C256(E,F)-15FM/883  
AT28C256(E,F)-15LM/883  
AT28C256(E,F)-15UM/883  
28D6  
28F  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28U  
200  
AT28C256(E,F)-20JC  
AT28C256(E,F)-20PC  
AT28C256(E,F)-20SC  
AT28C256(E,F)-20TC  
32J  
Commercial  
(0°C to 70°C)  
28P6  
28S  
28T  
AT28C256(E,F)-20JI  
AT28C256(E,F)-20PI  
AT28C256(E,F)-20SI  
AT28C256(E,F)-20TI  
32J  
Industrial  
(-40°C to 85°C)  
28P6  
28S  
28T  
50  
50  
0.3  
0.2  
AT28C256(E,F)-20DM/883  
AT28C256(E,F)-20FM/883  
AT28C256(E,F)-20LM/883  
AT28C256(E,F)-20UM/883  
28D6  
28F  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28U  
250  
AT28C256(E,F)-25JC  
AT28C256(E,F)-25PC  
AT28C256-W  
32J  
28P6  
DIE  
Commercial  
(0°C to 70°C)  
AT28C256(E,F)-25JI  
AT28C256(E,F)-25PI  
32J  
28P6  
Industrial  
(-40°C to 85°C)  
50  
50  
0.3  
0.2  
AT28C256(E,F)-25DM/883  
AT28C256(E,F)-25FM/883  
AT28C256(E,F)-25LM/883  
AT28C256(E,F)-25UM/883  
AT28C256(E,F)-35UM/883  
28D6  
28F  
32L  
28U  
28U  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
AT28C256-W  
DIE  
Commercial  
(0°C to 70°C)  
(continued)  
2-227  
Ordering Information (Continued)  
t
I
(mA)  
ACC  
CC  
Ordering Code  
Package  
Operation Range  
Active Standby  
50 0.35  
(ns)  
(3)  
150  
5962-88525 16 UX  
5962-88525 16 XX  
5962-88525 16 YX  
5962-88525 16 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
5962-88525 15 UX  
5962-88525 15 XX  
5962-88525 15 YX  
5962-88525 15 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
5962-88525 14 UX  
5962-88525 14 XX  
5962-88525 14 YX  
5962-88525 14 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
50  
0.35  
5962-88525 08 UX  
5962-88525 08 XX  
5962-88525 08 YX  
5962-88525 08 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
5962-88525 07 UX  
5962-88525 07 XX  
5962-88525 07 YX  
5962-88525 07 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
5962-88525 06 UX  
5962-88525 06 XX  
5962-88525 06 YX  
5962-88525 06 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
(3)  
200  
50  
50  
50  
0.35  
0.35  
0.35  
5962-88525 12 UX  
5962-88525 12 XX  
5962-88525 12 YX  
5962-88525 12 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
5962-88525 04 UX  
5962-88525 04 XX  
5962-88525 04 YX  
5962-88525 04 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
(3)  
250  
5962-88525 13 UX  
5962-88525 13 XX  
5962-88525 13 YX  
5962-88525 13 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
5962-88525 11 UX  
5962-88525 11 XX  
5962-88525 11 YX  
5962-88525 11 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
(continued)  
2-228  
AT28C256  
AT28C256  
Ordering Information (Continued)  
t
I
(mA)  
ACC  
CC  
Ordering Code  
Package  
Operation Range  
Active Standby  
(ns)  
250  
50  
0.35  
5962-88525 05 UX  
5962-88525 05 XX  
5962-88525 05 YX  
5962-88525 05 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
5962-88525 03 UX  
5962-88525 03 XX  
5962-88525 03 YX  
5962-88525 03 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
300  
50  
50  
50  
50  
0.35  
0.35  
0.35  
0.35  
5962-88525 10 UX  
5962-88525 10 XX  
5962-88525 10 YX  
5962-88525 10 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
5962-88525 02 UX  
5962-88525 02 XX  
5962-88525 02 YX  
5962-88525 02 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
350  
5962-88525 09 UX  
5962-88525 09 XX  
5962-88525 09 YX  
5962-88525 09 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
5962-88525 01 UX  
5962-88525 01 XX  
5962-88525 01 YX  
5962-88525 01 ZX  
28U  
28D6  
32L  
Military/883C  
Class B, Fully Compliant  
(-55°C to 125°C)  
28F  
Notes: 1. Electrical specifications for these speeds are defined by Standard Microcircuit Drawing 5962-88525.  
2. See Valid Part Number table below.  
3. SMD specifies Software Data Protection feature for device type, although Atmel product supplied to every device type  
in the SMD is 100% tested for this feature.  
Valid Part Numbers  
The following table lists standard Atmel products that can be ordered.  
Device Numbers  
AT28C256  
Speed  
Package and Temperature Combinations  
JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883  
JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883  
JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883  
JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883  
JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883  
JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883  
JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883  
JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883  
JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883  
W
15  
15  
15  
20  
20  
20  
25  
25  
25  
-
AT28C256E  
AT28C256F  
AT28C256  
AT28C256E  
AT28C256F  
AT28C256  
AT28C256E  
AT28C256F  
AT28C256  
2-229  
Package Type  
28D6  
28F  
32J  
32L  
28P6  
28S  
28T  
28U  
W
28 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip)  
28 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)  
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)  
32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)  
28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)  
28 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)  
28 Lead, Plastic Thin Small Outline Package (TSOP)  
28 Pin, Ceramic Pin Grid Array (PGA)  
Die  
Options  
Blank  
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms  
High Endurance Option: Endurance = 100K Write Cycles  
Fast Write Option: Write Time = 3 ms  
E
F
2-230  
AT28C256  

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