AT27BV512-70JI [ATMEL]
512K (64K x 8) Unregulated Battery-Voltage High-Speed OTP EPROM; 512K （ 64K ×8 ）非稳压电池电压高速OTP EPROM
| 型号： | AT27BV512-70JI |
| 厂家： | 
ATMEL |
| 描述： | 512K (64K x 8) Unregulated Battery-Voltage High-Speed OTP EPROM |
| 文件： | 总15页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 70 ns
• Dual Voltage Range Operation
– Unregulated Battery Power Supply Range, 2.7V to 3.6V
or Standard 5V 10% Supply Range
• Pin Compatible with JEDEC Standard AT27C512R
• Low Power CMOS Operation
– 20 µA Max (Less than 1 µA Typical) Standby for VCC = 3.6V
– 29 mW Max Active at 5 MHz for VCC = 3.6V
• JEDEC Standard Surface Mount Packages
– 32-lead PLCC
512K (64K x 8)
Unregulated
Battery-Voltage
High-Speed
– 28-lead SOIC
– 28-lead TSOP
• High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Rapid Programming Algorithm – 100 µs/Byte (Typical)
• CMOS and TTL Compatible Inputs and Outputs
– JEDEC Standard for LVTTL and LVBO
• Integrated Product Identification Code
• Industrial Temperature Range
OTP EPROM
AT27BV512
• Green (Pb/Halide-free) Packaging Option
1. Description
The AT27BV512 is a high-performance, low-power, low-voltage 524,288-bit one-time
programmable read-only memory (OTP EPROM) organized as 64K by 8 bits. It
requires only one supply in the range of 2.7 to 3.6V in normal read mode operation,
making it ideal for fast, portable systems using either regulated or unregulated battery
power.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while
keeping the low power consumption of a 3V supply. At VCC = 2.7V, any byte can be
accessed in less than 70 ns. With a typical power consumption of only 18 mW at
5 MHz and VCC = 3V, the AT27BV512 consumes less than one fifth the power of a
standard 5V EPROM.
Standby mode supply current is typically less than 1 µA at 3V. The AT27BV512 simpli-
fies system design and stretches battery lifetime even further by eliminating the need
for power supply regulation.
The AT27BV512 is available in industry-standard JEDEC-approved one-time
programmable (OTP) plastic PLCC, SOIC, and TSOP packages. All devices feature
two-line control (CE, OE) to give designers the flexibility to prevent bus contention.
The AT27BV512 operating with VCC at 3.0V produces TTL level outputs that are com-
patible with standard TTL logic devices operating at VCC = 5.0V. At VCC = 2.7V, the
part is compatible with JEDEC approved low voltage battery operation (LVBO) inter-
face specifications. The device is also capable of standard 5-volt operation making it
ideally suited for dual supply range systems or card products that are pluggable in
both 3-volt and 5-volt hosts.
0602E–EPROM–12/07
Atmel’s AT27BV512 has additional features to ensure high quality and efficient production use.
The Rapid Programming Algorithm reduces the time required to program the part and guaran-
tees reliable programming. Programming time is typically only 100 µs/byte. The Integrated
Product Identification Code electronically identifies the device and manufacturer. This feature
is used by industry-standard programming equipment to select the proper programming algo-
rithms and voltages. The AT27BV512 programs exactly the same way as a standard 5V
AT27C512R and uses the same programming equipment.
2. Pin Configurations
Pin Name
Function
A0 - A15
O0 - O7
CE
Addresses
Outputs
Chip Enable
OE/VPP
NC
Output Enable/Program Supply
No Connect
2.3
28-lead TSOP ( Type 1) Top View
2.1
28-lead SOIC Top View
OE/VPP
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
A15
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A13
A8
2
3
A8
A6
4
A13
A14
VCC
A15
A12
A7
A5
5
A9
A4
6
A11
OE/VPP
A10
CE
A3
7
2
A2
8
3
A1
9
A6
4
A0
10
11
12
13
14
O7
A5
5
O0
O1
O2
GND
O6
A4
6
A1
O5
A3
7
8
A2
O4
O3
2.2
32-lead PLCC Top View
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
28 A9
27 A11
26 NC
25 OE/VPP
24 A10
23 CE
22 O7
21 O6
A1 10
A0 11
NC 12
O0 13
Note:
PLCC package pins 1 and 17 are Don’t Connect.
2
AT27BV512
0602E–EPROM–12/07
AT27BV512
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce tran-
sient voltage excursions. Unless accommodated by the system design, these transients may
exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high
frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the VCC and Ground terminals of the device, as close
to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again
connected between the VCC and Ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +125°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V(1)
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Notes: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V DC which may be exceeded if certain precautions are observed (consult application notes) and which may
overshoot to +7.0V for pulses of less than 20 ns.
3
0602E–EPROM–12/07
6. Operating Modes
Mode \ Pin
CE
VIL
VIL
VIH
VIL
VIL
VIH
OE/VPP
VIL
Ai
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Outputs
DOUT
Read(2)
Ai
Output Disable(2)
Standby(2)
VIH
X(1)
High Z
High Z
DIN
X
X
Rapid Program(3)
PGM Verify(3)
PGM Inhibit(3)
VPP
VIL
Ai
Ai
DOUT
VPP
X
High Z
(4)
A9 = VH
Product Identification(3)(5)
VIL
VIL
A0 = VIH or VIL
A1 - A15 = VIL
VCC
Identification Code
Notes: 1. X can be VIL or VIH.
2. Read, output disable, and standby modes require, 2.7V ≤VCC ≤3.6V, or 4.5V ≤VCC ≤5.5V.
3. Refer to Programming Characteristics. Programming modes require VCC = 6.5V.
4. VH = 12.0 0.5V.
5. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
7. DC and AC Operating Conditions for Read Operation
AT27BV512-70
Operating Temperature (Case)
CC Power Supply
-40°C - 85°C
2.7V to 3.6V
5V 10%
V
4
AT27BV512
0602E–EPROM–12/07
AT27BV512
8. DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
Min
Max
Units
VCC = 2.7V to 3.6V
ILI
Input Load Current
VIN = 0V to VCC
1
µA
µA
µA
µA
µA
mA
V
ILO
Output Leakage Current
VOUT = 0V to VCC
5
10
(2)
IPP1
VPP(1) Read/Standby Current VPP = VCC
I
I
SB1 (CMOS), CE = VCC 0.3V
SB2 (TTL), CE = 2.0 to VCC + 0.5V
20
ISB
ICC
VIL
VCC(1) Standby Current
VCC Active Current
Input Low Voltage
100
f = 5 MHz, IOUT = 0 mA, CE = VIL, VCC = 3.6V
8
VCC = 3.0 to 3.6V
VCC = 2.7 to 3.6V
VCC = 3.0 to 3.6V
-0.6
-0.6
0.8
0.2 x VCC
VCC + 0.5
VCC + 0.5
0.4
V
2.0
V
VIH
Input High Voltage
Output Low Voltage
VCC = 2.7 to 3.6V
OL = 2.0 mA
0.7 x VCC
V
I
V
VOL
IOL = 100 µA
IOL = 20 µA
0.2
V
0.1
V
I
OH = -2.0 mA
2.4
V
VOH
Output High Voltage
IOH = -100 µA
IOH = -20 µA
VCC - 0.2
VCC - 0.1
V
V
VCC = 4.5V to 5.5V
ILI
Input Load Current
VIN = 0V to VCC
1
µA
µA
µA
µA
mA
mA
V
ILO
Output Leakage Current
VOUT = 0V to VCC
5
10
(2)
IPP1
VPP(1) Read/Standby Current VPP = VCC
I
SB1 (CMOS), CE = VCC 0.3V
100
1
ISB
VCC(1) Standby Current
ISB2 (TTL), CE = 2.0 to VCC + 0.5V
f = 5 MHz, IOUT = 0 mA, CE = VIL
ICC
VIL
VIH
VOL
VCC Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
20
-0.6
2.0
0.8
VCC + 0.5
0.4
V
IOL = 2.1 mA
IOH = -400 µA
V
VOH
2.4
V
Notes: 1. VCC must be applied simultaneously with or before OE/VPP, and removed simultaneously with or after OE/VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
5
0602E–EPROM–12/07
9. AC Characteristics for Read Operation
VCC = 2.7V to 3.6V and 4.5V to 5.5V
AT27BV512-70
Min Max
Symbol
Parameter
Condition
Units
ns
(3)
tACC
Address to Output Delay
CE to Output Delay
OE/VPP to Output Delay
CE = OE/VPP = VIL
OE/VPP = VIL
CE = VIL
70
70
50
(2)
tCE
ns
(2)(3)
tOE
ns
OE/VPP or CE High to Output Float,
Whichever Occurred First
(4)(5)
tDF
40
ns
ns
Output Hold from Address, CE or
OE/VPP, Whichever Occurred First
tOH
0
10. AC Waveforms for Read Operation(1)
Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE/VPP may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE
3. OE/VPP may be delayed up to tACC - tOE after the address is valid without impact on tACC
.
.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
6. When reading a AT27BV256, a 0.1 µF capacitor is required across VCC and ground to suppress spurious voltage transients.
6
AT27BV512
0602E–EPROM–12/07
AT27BV512
11. Input Test Waveform and Measurement Level
tR, tF < 20 ns (10% to 90%)
12. Output Test Load
Note: CL = 100 pF
including jig capacitance.
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
7
0602E–EPROM–12/07
14. Programming Waveforms(1)
Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27BV512, a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage
transients.
8
AT27BV512
0602E–EPROM–12/07
AT27BV512
15. DC Programming Characteristics
TA = 25 5°C, VCC = 6.5 0.25V, OE/VPP = 13.0 0.25V
Limits
Symbol
ILI
Parameter
Test Conditions
Min
Max
10
Units
µA
V
Input Load Current
VIN = VIL, VIH
VIL
Input Low Level
-0.6
2.0
0.8
VIH
Input High Level
VCC + 0.5
0.4
V
VOL
VOH
ICC2
IPP2
VID
Output Low Voltage
Output High Voltage
VCC Supply Current (Program and Verify)
OE/VPP Current
IOL = 2.1 mA
V
IOH = -400 µA
2.4
V
25
25
mA
mA
V
CE = VIL
A9 Product Identification Voltage
11.5
12.5
16. AC Programming Characteristics
TA = 25 5°C, VCC = 6.5 0.25V, OE/VPP = 13.0 0.25V
Limits
Symbol
tAS
Parameter
Test Conditions(1)
Min
2
Max
Units
µs
Address Setup Time
OE/VPP Setup Time
OE/VPP Hold Time
Data Setup Time
tOES
tOEH
tDS
2
µs
Input Rise and Fall Times:
2
µs
(10% to 90) 20 ns
2
µs
tAH
Address Hold Time
0
µs
Input Pulse Levels:
tDH
Data Hold Time
2
µs
0.45V to 2.4V
tDFP
tVCS
tPW
CE High to Output Float Delay(2)
VCC Setup Time
0
130
ns
Input Timing Reference Level:
0.8V to 2.0V
2
µs
CE Program Pulse Width(3)
Data Valid from CE(2)
OE/VPP Recovery Time
95
105
1
µs
Output Timing Reference Level:
0.8V to 2.0V
tDV
µs
tVR
2
µs
OE/VPP Pulse Rise Time During
Programming
tPRT
50
ns
Notes: 1. VCC must be applied simultaneously or before OE/VPP and removed simultaneously or after OE/VPP.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 100 µsec 5%.
17. Atmel’s AT27BV512 Integrated Product Identification Code(1)
Pins
Hex
Codes
A0
0
O7
0
O6
0
O5
0
O4
1
O3
1
O2
1
O1
1
O0
0
Data
Manufacturer
Device Type
1E
1
0
0
0
0
1
1
0
1
0D
Note:
1. The AT27BV512 has the same Product Identification Code as the AT27C512R. Both are programming compatible.
9
0602E–EPROM–12/07
18. RapidProgramming Algorithm
A 100 µs CE pulse width is used to program. The address is set to the first location. VCC is
raised to 6.5V and OE/VPP is raised to 13.0V. Each address is first programmed with one
100 µs CE pulse without verification. Then a verification/reprogramming loop is executed for
each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses
are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have
been applied, the part is considered failed. After the byte verifies properly, the next address is
selected until all have been checked. OE/VPP is then lowered to VIL and VCC to 5.0V. All bytes
are read again and compared with the original data to determine if the device passes or fails.
10
AT27BV512
0602E–EPROM–12/07
AT27BV512
19. Ordering Information
19.1 Standard Package
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
8
0.02
AT27BV512-70JI
AT27BV512-70RI
AT27BV512-70TI
32J
Industrial
28R(1)
(-40°C to 85°C)
28T
Note:
Not recommended for new designs. Use Green package option.
19.2 Green Package Option (Pb/Halide-free)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
8
0.02
AT27BV512-70JU
AT27BV512-70RU
AT27BV512-70TU
32J
Industrial
28R(1)
(-40°C to 85°C)
28T
Note:
1. The 28-pin SOIC package is not recommended for new designs.
Package Type
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
28R
28T
28-lead, 0.330" Wide, Plastic Gull Wing Small Package (SOIC)
28-lead, Plastic Thin Small Outline Package (TSOP)
11
0602E–EPROM–12/07
20. Packaging Information
20.1 32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
12
AT27BV512
0602E–EPROM–12/07
AT27BV512
20.2 28R – SOIC
B
E
E
1
PIN 1
e
D
A
A
1
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
2.39
MAX
2.79
NOM
NOTE
SYMBOL
0º ~ 8º
A
–
C
A1
D
E
0.050
18.00
11.70
8.59
–
0.356
18.50
12.50
8.79
–
Note 1
Note 1
L
–
E1
B
–
0.356
0.203
0.94
–
0.508
0.305
1.27
C
L
–
–
Note: 1. Dimensions D and E1 do not include mold Flash
or protrusion. Mold Flash or protrusion shall not exceed
0.25 mm (0.010").
e
1.27 TYP
5/18/2004
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
28R, 28-lead, 0.330" Body Width,
Plastic Gull Wing Small Outline (SOIC)
28R
R
C
13
0602E–EPROM–12/07
20.3 28T – TSOP
PIN 1
0º ~ 5º
c
Pin 1 Identifier Area
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
13.60
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.90
13.20
11.70
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
13.40
11.80
8.00
D1
E
11.90 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.55 BASIC
12/06/02
DRAWING NO. REV.
28T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
C
R
14
AT27BV512
0602E–EPROM–12/07
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International
Atmel Corporation
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0602E–EPROM–12/07
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