AT25FS040Y7-YH27-T [ATMEL]
High Speed Small Sectored SPI Flash Memory 4M (524,288 x 8); 高速小扇形的SPI快闪记忆体4M （ 524288 ×8 ）
| 型号： | AT25FS040Y7-YH27-T |
| 厂家： | 
ATMEL |
| 描述： | High Speed Small Sectored SPI Flash Memory 4M (524,288 x 8) |
| 文件： | 总25页 (文件大小：658K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet describes Mode 0 Operation
• 50 MHz Clock Rate
• Byte Mode and Page Mode Program (1 to 256 Bytes) Operations
• Sector/Block/Page Architecture
– Sixteen 256 byte Pages per Sector
– Sixteen 4 Kbyte Sectors per Block
High Speed
Small Sectored
SPI Flash
Memory
4M (524,288 x 8)
– Eight uniform 64 Kbyte Blocks
• Self-timed Sector, Block and Chip Erase
• Product Identification Mode with JEDEC Standard
• Low-voltage Operation
– 2.7V (VCC = 2.7V to 3.6V)
• Hardware and Software Write Protection
– Device protection with Write Protect (WP) Pin
– Write Enable and Write Disable Instructions
– Software Write Protection:
• Upper 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or Entire Array
• Flexible Op Codes for Maximum Compatibility
• Self-timed Program Cycle
AT25FS040
– 30 µs/Byte Typical
• Single Cycle Reprogramming (Erase and Program) for Status Register
• High Reliability
– Endurance: 10,000 Write Cycles Typical
• 8-lead JEDEC 150mil SOIC and 8-lead Ultra Thin Small Array Package (SAP)
• Die Sales: Waffer Form, Tape and Reel, and Bumped Wafers
Description
The AT25FS040 provides 4,194,304 bits of serial reprogrammable Flash memory
organized as 524,288 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25FS040 is available in a space-saving 8-lead JEDEC SOIC and
8-lead Ultra Thin SAP packages.
Table 0-1.
Pin Name
CS
Pin Configuration
Function
8-lead JEDEC SOIC
Chip Select
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
SCK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
WP
SI
GND
SO
8-lead SAP
GND
VCC
___
VCC 8
1 CS
Power Supply
Write Protect
_____
HOLD 7
2 SO
___
WP
SCK 6
SI 5
3 WP
Suspends Serial
Input
4 GND
HOLD
Bottom View
5107E–SFLSH–8/07
The AT25FS040 is enabled through the Chip Select pin (CS) and accessed via a 3-wire inter-
face consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All
write cycles are completely self-timed.
BLOCK WRITE protection for upper 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or the entire memory array is
enabled by programming the status register. Separate write enable and write disable instruc-
tions are provided for additional data protection. Hardware data protection is provided via the
WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
1. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature....................................–40°C to +85°C
Storage Temperature.....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground....................................–1.0V to +5.0V
Maximum Operating Voltage ............................................ 4.2V
DC Output Current........................................................ 5.0 mA
Figure 1-1. Block Diagram
524,288x8
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AT25FS040
5107E–SFLSH–8/07
AT25FS040
Table 1-1.
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +3.6V (unless otherwise noted)
Pin Capacitance(1)
Symbol
COUT
CIN
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 1-2.
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +2.7V to +3.6V,
AC = 0°C to +70°C, VCC = +2.7V to +3.6V (unless otherwise noted)
DC Characteristics (Preliminary – Subject to Change)
T
Symbol
VCC
ICC1
ICC2
ISB
Parameter
Test Condition
Min
Typ
Max
3.6
Units
V
Supply Voltage
Supply Current
Supply Current
Standby Current
Input Leakage
2.7
VCC = 3.6V at 20 MHz, SO = Open Read
VCC = 3.6V at 20 MHz, SO = Open Write
VCC = 2.7V, CS = VCC
10.0
15.0
2.0
17.0
mA
mA
µA
µA
µA
V
45.0
10.0
IIL
VIN = 0V to VCC
-3.0
-3.0
3.0
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(1)
VIL
-0.6
VCC x 0.3
VCC + 0.5
0.2
(1)
VIH
VCC x 0.7
V
VOL
I
OL = 0.15 mA
V
2.7V ≤ VCC ≤ 3.6V
VOH
IOH = -100 µA
VCC - 0.2
V
Note:
1. VIL and VIH max are reference only and are not tested.
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5107E–SFLSH–8/07
Table 1-3.
AC Characteristics (Preliminary – Subject to Change)
Applicable over recommended operating range from TA = –40°C to +85°C, VCC = +2.7V to +3.6V
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Min
Typ
Max
50
5
Units
fSCK
tRI
SCK Clock Frequency
Input Rise Time
0
MHz
ns
tFI
Input Fall Time
5
ns
tWH
tWL
SCK High Time
9
9
ns
SCK Low Time
ns
tCS
CS High Time
100
5
ns
tCSS
tCSH
tSU
CS Setup Time
ns
CS Hold Time
5
ns
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
5
ns
tH
5
ns
tHD
5
ns
tCD
5
ns
tV
Output Valid
9
ns
tHO
Output Hold Time
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
Sector Erase Time
Block Erase Time
Chip Erase Time
Status Register Write Cycle Time
Byte Program Cycle Time(1)
0
ns
tLZ
9
9
ns
tHZ
ns
tDIS
tSE
9
ns
50
200
1.6
200
500
4
ms
tBE
ms
tCE
s
tSR
60
50
ms
tBPC
Endurance(2)
30
µs
10K
Write Cycles(3)
Notes: 1. The programming time for n bytes will be equal to n x tBPC
.
2. This parameter is characterized at 3.0V.
3. One write cycle consists of erasing a sector, followed by programming the same sector.
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AT25FS040
5107E–SFLSH–8/07
AT25FS040
2. Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25FS040 always oper-
ates as a slave.
TRANSMITTER/RECEIVER: The AT25FS040 has separate pins designated for data transmis-
sion (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25FS040, and the serial output pin (SO) will remain in a high impedance state until the falling
edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25FS040 is selected when the CS pin is low. When the device is not
selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a
high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25FS040. When
the device is selected and a serial sequence is underway, HOLD can be used to pause the serial
communication with the master device without resetting the serial sequence. To pause, the
HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the
HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to
the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The AT25FS040 has a write lockout feature that can be activated by assert-
ing the write protect pin (WP). When the lockout feature is activated, locked-out sectors will be
READ only. The write protect pin will allow normal read/write operations when held high. When
the WP is brought low and WPEN bit is “1”, all write operations to the status register are inhib-
ited. WP going low while CS is still low will interrupt a write to the status register. If the internal
status register write cycle has already been initiated, WP going low will have no effect on any
write operation to the status register. The WP pin function is blocked when the WPEN bit in the
status register is “0”. This will allow the user to install the AT25FS040 in a system with the WP
pin tied to ground and still be able to write to the status register. All WP pin functions are enabled
when the WPEN bit is set to “1”.
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5107E–SFLSH–8/07
3. Operating Features
3.1
Recommended Power-up
When the power supply is turned on, the Vcc to the device rises monotonically from ground to
the full operating Vcc. During this time, the Chip Select (CS) signal is not allowed to float and
must follow Vcc. For this reason, it is recommended to use a suitable pull-up resistor connected
between CS and Vcc. The device is ready for communication once a stable Vcc is reached
within the specified operating voltage range.
3.2
Recommended Power-down
The device must be deselected and in standby and write disabled mode prior to Vcc power down
sequence. This means there should be no write operation/internal write cycle or read operation
in progress during power down. The Vcc decay should be monotonic from Vcc to ground and the
Chip Select (CS) line must be allowed to follow Vcc during power down. After power down, it is
recommended Vcc should be held at ground level for at least 0.5 seconds before power up
again.
3.3
Power On Reset Protection
In order to prevent data corruption and inadvertent write operations during device power-up and
power down, a Power On Reset (POR) circuit is enabled. At Power-up (continuous rise of Vcc
from 0v), the device will not respond to any instruction and will be held in reset (which puts the
device in standby mode) until the Vcc has reached the Power On Reset threshold voltage. This
threshold is lower than the minimum specified Vcc operating voltage.
At power down (continuous fall of Vcc), when Vcc drops from the operating voltage below the
POR threshold, all operations are disabled and the device will not respond to any command. A
stable and valid Vcc must be applied before executing any communication. Please note: The
POR threshold trip point is ~1.8V for Serial Flash products and is ensured by design to have a
reset during power-up and power down and is not 100% tested.
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AT25FS040
5107E–SFLSH–8/07
AT25FS040
Figure 3-1. SPI Serial Interface
MASTER:
MICROCONTROLLER
SLAVE:
AT25FS040
SI
DATA OUT (MOSI)
SO
DATA IN (MISO)
SERIAL CLOCK (SPI CK)
SCK
CS
SS0
SS1
SS2
SS3
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
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5107E–SFLSH–8/07
4. Functional Description
The AT25FS040 is designed to interface directly with the synchronous serial peripheral interface
(SPI) of the 6800 type series of microcontrollers.
The AT25FS040 utilizes an 8-bit instruction register. The list of instructions and their operation
codes are contained in Table 4-1. All instructions, addresses, and data are transferred with the
MSB first and start with a high-to-low transition.
Write is defined as program and/or erase in this specification. The following commands, PRO-
GRAM, SECTOR ERASE, BLOCK ERASE, CHIP ERASE, and WRSR are write instructions for
AT25FS040.
Table 4-1.
Instruction Set for the AT25FS040
Instruction Name
One Byte OpCode
Operation
Binary
Hex
WREN
WRDI
RDSR
WRSR
READ
0000 X110
0000 X100
0000 X101
0000 X001
0000 0011
06
04
05
01
03
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Read Data from Memory Array (with
dummy cycles)
FAST READ
PROGRAM
0000 1011
0B
0000 X010
0010 0000
02
20
Program Data Into Memory Array
Erase One 4kbyte Sector in Memory Array
SECTOR ERASE
(1)
1101 0111
D7
0101 0010
1101 1000
0110 0000
1100 0111
1001 1111
1010 1011
52
Erase One 64kbyte Block in Memory Array
Erase All Memory Array
BLOCK ERASE(1)
CHIP ERASE(1)
RDID(1)
D8
60
C7
9F
AB
Read Manufacturer and Product ID
Note:
1. Either one of the OP CODES will execute the instruction.
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is
applied. All write instructions must therefore be preceded by the WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruc-
tion disables all write commands. The WRDI instruction is independent of the status of the WP
pin.
READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the status regis-
ter. The READY/BUSY and write enable status of the device can be determined by the RDSR
instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed.
8
AT25FS040
5107E–SFLSH–8/07
AT25FS040
These bits are set by using the WRSR instruction. During internal write cycles, all other com-
mands will be ignored except the RDSR instruction.
Table 4-2.
Bit 7
Status Register Format
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
BP4
BP3
BP2
BP1
BP0
WEN
RDY
Table 4-3.
Bit
Read Status Register Bit Definition
Definition
Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the
write cycle is in progress.
Bit 0 (RDY)
Bit 1 (WEN)
Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates
the device is WRITE ENABLED.
Bit 2 (BP0)
Bit 3 (BP1)
Bit 4 (BP2)
Bit 5 (BP3)
Bit 6 (BP4)
Bit 7 (WPEN)
See Table 4-5.
See Table 4-5.
See Table 4-5.
See Table 4-5.
See Table 4-5.
See Table 4-6.
Bits 0-7 are 1s during an internal write cycle.
READ PRODUCT ID (RDID): The RDID instruction allows the user to read the manufacturer ID
byte followed by two device ID bytes. The manufacturer ID is assigned by JEDEC and is 1Fh for
Atmel (see Table 4-4). The first device ID byte indicates the memory type (66h=AT25FS040) fol-
lowed by the device memory capacity byte (04h). For maximum compatibility and flexibility, two
RDID opcodes (9Fh and ABh) are supported and will perform the same operation.
Table 4-4.
Read Product ID (RDID)
Manufacturer ID
Device ID
Memory Type
66h
Memory Capacity
04h
1Fh
The device is first selected by driving Chip Select (CS) low then the RDID opcode is shifted in on
Serial In (SI) during rising edge of clock. The 24-bit Manufacturer and Device Identification
Codes stored in memory are clocked out on Serial Output (SO) starting on the falling edge of
clock (see Figure 5-13). If CS stays low after the last bit of second device ID byte is shifted out,
the manufacturer ID and 2 byte device ID will continue to be clocked out until CS goes high. The
RDID sequence is terminated any time CS is driven high and the device will go into standby
mode.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
eight levels of protection for the AT25FS040. The AT25FS040 is divided into eight blocks where
the top 1/64, 1/32, 1/16, 1/8, top quarter (1/4), top half (1/2), or all of the memory blocks can be
protected (locked out) from write. Any of the locked-out blocks will therefore be READ only. The
locked-out sector/block and the corresponding status register control bits are shown in Table 4-5
on page 10.
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5107E–SFLSH–8/07
The six bits, BP0, BP1, BP2, BP3, BP4 and WPEN, are nonvolatile cells that have the same
properties and functions as the regular memory cells.
Table 4-5.
Level
Sector/Block Write Protect Bits
Status Register Bits
BP3 BP2 BP1
AT25FS040
BP4
BP0
Array Address
Locked-out
Blocks
locked Out
0(none)
1(1/64)
2(1/32)
3(1/16)
4(1/8)
0
0
1
1
x
x
x
x
0
1
0
1
x
x
x
x
0
0
0
0
0
0
1
0
1
x
None
None
0
0
0
0
0
0
1
0
0
0
0
1
1
x
07E000H - 07FFFFH
07C000H - 07FFFFH
078000H - 07FFFFH
070000H - 07FFFFH
060000H - 07FFFFH
040000H - 07FFFFH
000000H - 07FFFFH
Sector 15-16 of Block 8
Sector 13-16 of Block 8
Sector 9-16 of Block 8
All sectors of Block 8
5(1/4)
All Sectors of Block 7,8
All Sectors of Block 5,6,7,8
All Sectors of All Blocks (1-8)
6(1/2)
7(ALL)
Note:
1. x = don’t care
The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0.” When the device is hardware write protected,
writes to the Status Register, including the Block Protect bits and the WPEN bit, and the locked-
out sectors in the memory array are disabled. Write is only allowed to sectors of the memory
which are not locked out. The WRSR instruction is self-timed to automatically erase and pro-
gram BP0, BP1, BP2, BP3, BP4 and WPEN bits. In order to write the status register, two
separate instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then, CS must be low and the WRSR instruction and data for the six bits are
entered. The WRSR write cycle will begin once CS goes high. During the internal write cycle, all
instructions will be ignored except RDSR instructions. The AT25FS040 will automatically return
to write disable state at the completion of the WRSR cycle. The status register is factory pro-
grammed to all 0’s.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the
WP pin is held low.
Table 4-6.
WPEN Operation
WPEN
WP
WEN
ProtectedBlocks
UnprotectedBlocks
Protected
Status Register
Protected
Writable
0
0
1
1
X
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
X
Writable
Low
Low
High
High
Protected
Protected
Protected
Protected
Writable
Writable
Protected
Writable
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AT25FS040
5107E–SFLSH–8/07
AT25FS040
READ (READ): The READ instruction sequence reads the memory array up to the maximum
speed of 50MHz. Reading the AT25FS040 via the SO (Serial Output) pin requires the following
sequence. After the CS line is pulled low to select the device, the READ instruction is clocked in
on the SI line, followed by the byte address to be read. Upon completion, any data on the SI line
will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line
(see Figure 5-6). If only one byte is to be read, the CS line should be driven high after the least
significant data bit. To continue read operation and sequentially read subsequent byte
addresses from the device by simply keeping CS low and provide a clock signal. The device
incorporates an internal address counter that automatically increments to the next byte address
during sequential read operation. The READ instruction can be continued since the byte
address is automatically incremented and data will continue to be shifted out of the AT25FS040
until the highest byte address is reached. When the last bit of the memory has been read, the
device will continue reading back at the beginning of the array (000000h) without delay. The
data is always output from the device with the most significant bit (MSB) of a byte first. The
READ sequence is terminated any time CS is driven high and the device will go into standby
mode.
FAST READ (FAST READ): The FAST READ instruction sequence reads the memory array up
to the maximum speed of 50MHz (same as standard READ sequence). The FAST READ is an
alternate command for the READ and allows for FAST READ instruction compatibility support.
The difference between the two is FAST READ requires a “dummy byte” and READ does not.
Reading the AT25FS040 via the SO (Serial Output) pin requires the following sequence. After
the CS line is pulled low to select the device, the FAST READ instruction is clocked in on the SI
line, followed by the byte address to be read and the dummy byte (the SO line output will be high
Z state). Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the spec-
ified address is then shifted out onto the SO line (see Figure 5-7). If only one byte is to be read,
the CS line should be driven high after the least significant data bit. To continue read operation
and sequentially read subsequent byte addresses from the device by simply keeping CS low
and provide a clock signal. The device incorporates an internal address counter that automati-
cally increments to the next byte address during sequential read operation. The FAST READ
instruction can be continued since the byte address is automatically incremented and data will
continue to be shifted out of the AT25FS040 until the highest address is reached. When the last
bit of the memory has been read, the device will continue reading back at the beginning of the
array (000000h) without delay. The data is always output from the device with the most signifi-
cant bit (MSB) of a byte first. The FAST READ sequence is terminated any time CS is driven
high and the device will go into standby mode.
PROGRAM (PROGRAM): The PROGRAM instruction allows up to 256 data bytes to be written
to each page in the memory in one-operation changing data bits from a logic 1 to 0 state. The
AT25FS040 memory array contains 524,288 programmable data bytes internally organized into
256 bytes per page with a total of 2048 pages in the memory.
In order to program the AT25FS040, two separate instructions must be executed. First, the
device must be write enabled via the WREN instruction. Then the PROGRAM instruction can be
executed and requires the following sequence. After the CS line is pulled low to select the
device, the PROGRAM instruction is clocked in via the SI line followed by the byte address (see
Figure 5-8) and the data byte(s) to be programmed. Programming will start after CS pin is
brought high. Please note: The low to high transition of the CS pin must occur during the SCK
low time immediately after clocking in the D0 (LSB) data bit to initiate programming cycle. Also, a
WREN instruction must precede each and every PROGRAM instruction. The Ready/Busy status
of the device can be determined by initiating a RDSR instruction. If bit 0=1, the program cycle is
11
5107E–SFLSH–8/07
still in progress. If Bit 0=0, the programming cycle has ended. Only the RDSR instruction is
enabled during the programming cycle and all other opcode instructions are ignored until pro-
gramming cycle has completed.
A single PROGRAM instruction programs 1 to 256 consecutive bytes within a page if it is not
write protected. The starting byte address can be anywhere within the page. When the end of
the page is reached, the address will wrap around to the beginning of the same page. If the data
to be programmed is less than a full page, the data of all other bytes on the same page will
remain unchanged meaning that the unwritten address locations within the page will not be
changed. If more than 256 bytes of data are provided, the address counter will roll over on the
same page and the previous data provided will be replaced. The same byte cannot be repro-
grammed without erasing the whole sector or block first. The AT25FS040 will automatically
return to the write disable state at the completion of the programming cycle.
Note:
If the device is not write enabled (WREN), the device will ignore the Write instruction and will
return to the standby state when CS is brought high. A new CS falling edge is required to re-ini-
tiate the serial communication.
Table 4-7.
Address Key
Address
AT25FS040
A18 - A0
AN
Don’t Care Bits
A23 - A19
ERASE OPERATION: The AT25FS040 memory array is internally organized into uniform
4K byte sectors or uniform 64K byte uniform blocks (see Table 4-8). Before data can be
reprogrammed, the sector or block that contains the data must be erased first. In order to
erase the AT25FS040, there are three flexible erase instructions that can be executed as
follows: SECTOR ERASE, BLOCK ERASE and CHIP ERASE instructions. A SECTOR
ERASE instruction allows erasing any individual 4K sector without changing data in rest
of memory. The BLOCK ERASE instruction allows erasing any individual block and CHIP
ERASE allows erasing the entire memory array.
SECTOR ERASE (SECTOR ERASE): The SECTOR ERASE instruction sets all 4K bytes in the
selected sector to logic 1 or erased state. In order to sector erase the AT25FS040, two separate
instructions must be executed. First, the device must be write enabled via the WREN instruction.
Then the SECTOR ERASE instruction can be executed and will erase every byte in the selected
sector if the sector is not locked out. The sector address is automatically determined if any
address within the sector is selected (see Figure 5-10). The SECTOR ERASE instruction is
internally controlled and self timed to completion. During this time, all commands will be ignored
except RDSR instruction. The progress or completion of the erase operation can be determined
by reading ready/busy bit (bit 0) through RDSR instruction. If Bit 0=1, sector erase cycle is in
progress. If Bit 0=0, the erase operation has been completed. The AT25FS040 will automatically
return to the write disable state at the completion of the SECTOR ERASE cycle.
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AT25FS040
5107E–SFLSH–8/07
AT25FS040
Table 4-8.
Sector and Block Address
07FFFFH
Sector 16
Sector 15
Sector 14
Sector 13
Sector 12
Sector 11
Sector 10
Sector 9
Sector 8
Sector 7
Sector 6
Sector 5
Sector 4
Sector 3
Sector 2
Sector 1
Block 8
07F000H
07EFFFH
07E000H
07DFFFH
07D000H
07CFFFH
07C000H
07BFFFH
07B000H
07AFFFH
07A000H
079FFFH
079000H
078FFFH
078000H
077FFFH
077000H
076FFFH
076000H
075FFFH
075000H
074FFFH
074000H
073FFFH
073000H
072FFFH
072000H
071FFFH
071000H
070FFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
1/64
1/32
1/16
1/8
Block 7
Block 6
13
5107E–SFLSH–8/07
Table 4-8.
Sector and Block Address (Continued)
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
000000H
Block 5
Block 4
Block 3
Block 2
Block 1
BLOCK ERASE (BLOCK ERASE): The BLOCK ERASE instruction sets all 64K bytes in the
selected block to logic 1 or erased state. In order to block erase the AT25FS040, two sep-
arate instructions must be executed. First, the device must be write enabled via the
WREN instruction. Then the BLOCK ERASE instruction can be executed and will erase
every byte in the selected block if the block is not locked out. The block address is auto-
matically determined if any address within the block is selected (see Figure 5-11). The
BLOCK ERASE instruction is internally controlled and self timed to completion. During
this time, all commands will be ignored except RDSR instruction. The progress or com-
pletion of the erase operation can be determined by reading ready/busy bit (bit 0) through
RDSR instruction. If Bit 0=1, block erase cycle is in progress. If Bit0=0, the erase opera-
tion has been completed. The AT25FS040 will automatically return to the write disable
state at the completion of the BLOCK ERASE cycle.
CHIP ERASE (CHIP ERASE): As an alternative to the SECTOR ERASE/BLOCK ERASE, the
CHIP ERASE instruction will erase every byte in all sectors that are not locked out. First, the
device must be write enabled via the WREN instruction. Then the CHIP ERASE instruction can
be executed. The CHIP ERASE instruction is internally controlled; it will automatically be timed
to completion. The CHIP ERASE cycle time typically is 4 seconds. During the internal erase
cycle, all instructions will be ignored except RDSR. The AT25FS040 will automatically return to
the write disable state at the completion of the CHIP ERASE cycle.
14
AT25FS040
5107E–SFLSH–8/07
AT25FS040
5. Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 5-1. Synchronous Data Timing
tCS
V
IH
CS
V
IL
tCSH
t
CSS
V
IH
tWH
tH
tWL
SCK
SI
V
IL
tSU
V
IH
VALID IN
V
IL
tHO
tDIS
tV
VOH
VOL
HI-Z
HI-Z
SO
Figure 5-2. WREN Timing
CS
0
1
2
3
4
5
6
7
SCK
WREN OP-CODE
HI-Z
SI
SO
Figure 5-3. WRDI Timing
CS
0
1
2
3
4
5
6
7
SCK
WRDI OP-CODE
HI-Z
SI
SO
15
5107E–SFLSH–8/07
Figure 5-4. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
RDSR OP-CODE
SI
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
Figure 5-5. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
SCK
DATA IN
7
6
5
4
3
2
1
0
WRSR OP-CODE
SI
HIGH IMPEDANCE
SO
Figure 5-6. READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 29 30 31 32 33 34 35 36 37 38 39 40
...
SCK
OPCODE
ADDRESS BITS A23 - A0
...
A
A
A
1
1
A
A
A
A
A
A
0
0
0
0
0
0
SI
MSB
MSB
HIGH IMPEDANCE
SO
D
D
D
D
D
D
D
D
D
D
MSB
MSB
16
AT25FS040
5107E–SFLSH–8/07
AT25FS040
Figure 5-7. FAST READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
...
SCK
SI
ADDRESS BITS A23 - A0
...
OPCODE
DON’T CARE
A
A
A
X
X X X X X X X
1
0
1
A
A
A
A A A
0
0
0
0
0
MSB
MSB
MSB
DATA BYTE 1
HIGH IMPEDANCE
D
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
Figure 5-8. PROGRAM Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 28 29 30 31 32 33 34
SCK
SI
256th BYTE DATA-IN
1st BYTE DATA-IN
3-BYTE ADDRESS
PROGRAM OP-CODE
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 5-9. HOLD Timing
CS
tCD
tCD
SCK
HOLD
SO
tHD
tHD
tHZ
tLZ
17
5107E–SFLSH–8/07
Figure 5-10. SECTOR ERASE Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11 28 29 30
31
SCK
3-BYTE ADDRESS
22 21
SECTOR ERASE OP-CODE
23
3
2
1
0
SI
HIGH IMPEDANCE
SO
Figure 5-11. BLOCK ERASE Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11
28 29 30
31
SCK
3-BYTE ADDRESS
BLOCK ERASE OP-CODE
23
22 21
3
2
1
0
SI
HIGH IMPEDANCE
SO
Figure 5-12. CHIP ERASE Timing
CS
0
1
2
3
4
5
6
7
SCK
CHIP ERASE OP-CODE
SI
HIGH IMPEDANCE
SO
18
AT25FS040
5107E–SFLSH–8/07
AT25FS040
Figure 5-13. RDID Timing
CS
4
8
1
2
3
5
6
9 10
11 12 13 14 15 16 17 18
0
7
29 30 31
28
SCK
SI
RDID OP-CODE
DATA OUT
3
HIGH IMPEDANCE
SO
Manufacturer Code (Atmel = 1F)
14
0
15
2
1
66 04
19
5107E–SFLSH–8/07
Ordering Information
Ordering Code
AT25FS040N-SH27-B(1)
AT25FS040N-SH27-T(2)
Volltage
2.7
Package
8S1
Operation Range
Lead-Free/Halogen-Free/
NiPdAu Lead Finish
Industrial Temperature
2.7
8S1
AT25FS040Y7-YH27-T(2)
2.7
8Y7
(–40°C to 85°C)
Notes: 1. “-B” denotes bulk.
2. “-T” denotes tape and reel, SOIC = 4K per reel and SAP = 3K per reel.
Package Type
8S1
8Y7
8-lead, 0.150” Wide, Plastic Gull Wing Small outline (JEDEC SOIC)
8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
–2.7
Low Voltage (2.7V to 3.6V)
20
AT25FS040
5107E–SFLSH–8/07
AT25FS040
6. Part Marking Scheme
6.1
8-SOIC
TOP MARK
Seal Year
Y = SEAL YEAR
WW = SEAL WEEK
|
Seal Week
6: 2006
0: 2010
02 = Week 2
|
|
|
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
04 = Week 4
:: : :::: :
:: : :::: ::
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
50 = Week 50
52 = Week 52
S
4
3
|---|---|---|---|---|---|---|---|
Lot Number
*
Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
|
BOTTOM MARK
Pin 1 Indicator (Dot)
No Bottom Mark
6.2
8-Ultra Thin SAP
TOP MARK
Seal Year
|
|
Seal Week
Y = SEAL YEAR
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
52 = Week 52
|
|
6: 2006
7: 2007
8: 2008
9: 2009
0: 2010
|---|---|---|---|---|---|---|---|
1: 2011
2: 2012
3: 2013
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
S
4
3
|---|---|---|---|---|---|---|---|
Lot Number
|---|---|---|---|---|---|---|---|
*
|
BOTTOM MARK
Pin 1 Indicator (Dot)
No Bottom Mark
21
5107E–SFLSH–8/07
7. Package Information
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0°
–
–
1.27
∅
8°
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
22
AT25FS040
5107E–SFLSH–8/07
AT25FS040
8Y7 – UT SAP
PIN 1 INDEX AREA
A
PIN 1 ID
D
E1
L
A1
E
b
e
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
MAX
0.60
0.05
6.20
5.10
3.50
4.10
0.45
NOM
–
NOTE
A
A1
D
0.00
5.80
4.70
3.30
3.90
0.35
–
6.00
E
4.90
D1
E1
b
3.40
4.00
0.40
e
1.27 TYP
3.81 REF
0.60
e1
L
0.50
0.70
10/13/05
TITLE
DRAWING NO.
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array
Package (UTSAP) Y7
8Y7
B
R
23
5107E–SFLSH–8/07
8. Revision History
Doc. Rev.
Date
Comments
Added Die Sales Info to Features
Modified Order Code Table
Updated to new template
5107E
5107D
8/2007
9/2006
Added Parts Marking tables
Implemented Revision History.
24
AT25FS040
5107E–SFLSH–8/07
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International
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www.atmel.com
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www.atmel.com/contacts
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www.atmel.com/literature
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5107E–SFLSH–8/07
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