AT25160B-SSHL-T [ATMEL]
EEPROM, 2KX8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, PLASTIC, MS-012AA, SOIC-8;
| 型号： | AT25160B-SSHL-T |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 2KX8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, PLASTIC, MS-012AA, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总26页 (文件大小：1279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes Mode 0 Operation
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• 20MHz Clock Rate (5V)
• 32-byte Page Mode
• Block Write Protection
SPI Serial
EEPROMs
8K (1024 x 8)
16K (2048 x 8)
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
• Self-timed Write Cycle (5ms max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• Green (Pb/Halide-free/RoHS Compliant) Packaging Options
• Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
Atmel AT25080B
Atmel AT25160B
Description
The Atmel® AT25080B/160B provides 8192/16384 bits of serial electrically-erasable
programmable read-only memory (EEPROM) organized as 1024/2048 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The AT25080B/160B is
available in space-saving 8-lead JEDEC SOIC, 8-lead UDFN, 8-lead TSSOP, 8-lead
XDFN, and 8-ball VFBGA packages.
The AT25080B/160B is enabled through the Chip Select pin (CS) and accessed via a
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate erase cycle is required before write.
Figure 1.
Pin Configuration
8-lead SOIC
8-lead TSSOP
Pin Name Function
CS
SO
VCC
CS
SO
1
2
3
4
8
7
6
5
VCC
1
2
3
4
8
7
6
5
HOLD
SCK
SI
HOLD
SCK
SI
CS
Chip Select
WP
WP
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
GND
GND
8-lead UDFN
8-lead XDFN
SO
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
VCC
CS
SO
VCC
CS
GND
VCC
WP
HOLD
HOLD
SCK
SI
HOLD
SCK
SI
SO
WP
WP
GND
Power Supply
Write Protect
GND
Bottom View
Bottom View
Suspends Serial Input
8-ball VFBGA
VCC
8
7
6
5
1
2
3
4
CS
SO
HOLD
SCK
SI
WP
GND
5228E–SEEPR–3/12
Bottom View
Block write protection is enabled by programming the status register with one of four blocks of write protection.
Separate program enable and program disable instructions are provided for additional data protection. Hardware
data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The
HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
2.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under
“Absolute Maximum Ratings” may cause
permanent damage to the device. This is a
stress rating only and functional operation
of the device at these or any other
Operating Temperature...........................–55C to +125C
Storage Temperature ..............................–65C to +150C
Voltage on Any Pin
with Respect to Ground..............................–1.0V to +7.0V
conditions beyond those indicated in the
operational sections of this specification is
not implied. Exposure to absolute maximum
rating conditions for extended periods may
affect device reliability.
Maximum Operating Voltage.................................... 6.25V
DC Output Current .................................................. 5.0mA
Figure 2-1. Block Diagram
2
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
Table 2-1.
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = +5.0V (unless otherwise noted)
Pin Capacitance(1)
Symbol
COUT
CIN
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested
Table 2-2.
DC Characteristics
Applicable over recommended operating range from: TAI = –40C to +85C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
VCC1
Parameter
Test Condition
Min
1.8
2.5
4.5
Typ
Max
5.5
Units
V
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
VCC2
5.5
V
VCC3
5.5
V
ICC1
VCC = 5.0V at 20MHz, SO = Open, Read
7.5
4.0
10.0
mA
VCC = 5.0V at 20MHz, SO = Open, Read,
Write
ICC2
ICC3
Supply Current
Supply Current
10.0
mA
mA
VCC = 5.0V at 5MHz, SO = Open,
Read, Write
4.0
6.0
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V, CS = VCC
VCC = 2.5V, CS = VCC
VCC = 5.0V, CS = VCC
VIN = 0V to VCC
< 0.1
0.3
6.0(2)
7.0(2)
µA
µA
µA
µA
µA
V
2.0
10.0(2)
–3.0
–3.0
3.0
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(1)
VIL
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
Output Low-voltage
Output High-voltage
–0.6
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
VCC x 0.7
V
VOL1
VOH1
VOL2
VOH2
IOL = 3.0mA
3.6V VCC 5.5V
V
IOH = 1.6mA
VCC - 0.8
VCC - 0.2
V
IOL = 0.15mA
1.8V VCC 3.6V
0.2
V
IOH = 100µA
V
Notes: 1. VIL min and VIH max are reference only and are not tested
2. Worst case measured at 85C
3
5228E–SEEPR–3/12
Table 2-3.
AC Characteristics
Applicable over recommended operating range from TAI = –40C to +85C, VCC = As Specified,
CL = 1 TTL Gate and 30pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
20
10
5
fSCK
SCK Clock Frequency
MHz
4.5–5.5
2.5–5.5
1.8–5.5
2
2
2
tRI
Input Rise Time
Input Fall Time
SCK High Time
µs
µs
ns
4.5–5.5
2.5–5.5
1.8–5.5
2
2
2
tFI
20
40
4.5–5.5
2.5–5.5
1.8–5.5
tWH
80
20
40
4.5–5.5
2.5–5.5
1.8–5.5
tWL
tCS
tCSS
tCSH
tSU
tH
SCK Low Time
CS High Time
ns
ns
ns
ns
ns
ns
80
4.5–5.5
2.5–5.5
1.8–5.5
25
50
100
4.5–5.5
2.5–5.5
1.8–5.5
25
50
100
CS Setup Time
CS Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
25
50
100
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
Data In Setup Time
Data In Hold Time
HOLD Setup Time
HOLD Hold Time
Output Valid
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
tHD
tCD
tV
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
ns
ns
20
40
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
80
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
tHO
Output Hold Time
4
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
Table 2-3.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = –40C to +85C, VCC = As Specified,
CL = 1 TTL Gate and 30pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
25
50
100
tLZ
HOLD to Output Low Z
ns
4.5–5.5
2.5–5.5
1.8–5.5
40
80
200
tHZ
HOLD to Output High Z
Output Disable Time
ns
ns
4.5–5.5
2.5–5.5
1.8–5.5
40
80
200
tDIS
4.5–5.5
2.5–5.5
1.8–5.5
5
5
5
tWC
Write Cycle Time
ms
Endurance(1)
3.3V, 25°C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested
3.
Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080B/160B always operates as a slave.
TRANSMITTER/RECEIVER: The AT25080B/160B has separate pins designated for data transmission (SO) and
reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte con-
tains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25080B/160B, and the
serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will
reinitialize the serial communication.
CHIP SELECT: The AT25080B/160B is selected when the CS pin is low. When the device is not selected, data will
not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25080B/160B. When the device is
selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the mas-
ter device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is
low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle
during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low
while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated,
WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when
the WPEN bit in the status register is “0”. This will allow the user to install the AT25080B/160B in a system with the
WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the
WPEN bit is set to “1”.
5
5228E–SEEPR–3/12
Figure 3-1. SPI Serial Interface
AT25080B/160B
6
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
4.
Functional Description
The AT25080B/160B is designed to interface directly with the synchronous serial peripheral interface (SPI) of the
6805 and 68HC11 series of microcontrollers.
The AT25080B/160B utilizes an 8-bit instruction register. The list of instructions and their operation codes are con-
tained in Table 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-
low CS transition.
Table 4-1.
Instruction Set for the AT25080B/160B
Instruction Name
WREN
Instruction Format
0000 X110
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRDI
0000 X100
RDSR
0000 X101
WRSR
0000 X001
READ
0000 X011
WRITE
0000 X010
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All program-
ming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly,
the Block Write Protection Bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 4-2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 4-3.
Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle is in progress
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the device is write enabled
See Table 3-4 on page 8
See Table 3-4 on page 8
Bits 4–6 are “0”s when device is not in an internal write cycle
Bit 7 (WPEN) See Table 3-5 on page 8
Bits 0–7 are “1”s during an internal write cycle
7
5228E–SEEPR–3/12
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protec-
tion. The AT25080B/160B is divided into four array segments. One-quarter, one-half, or all of the memory
segments can be protected. Any of the data within any selected segment will therefore be read only. The block
write protection levels and corresponding status register control bits are shown in Table 3-4.
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regu-
lar memory cells (e.g., WREN, tWC, RDSR).
Table 4-4.
Block Write Protect Bits
Status Register Bits
Array Addresses Protected
AT25080B AT25160B
None None
Level
0
BP1
BP0
0
0
1
1
0
1
0
1
1(1/4)
2(1/2)
3(All)
030003FF
020003FF
000003FF
060007FF
040007FF
000007FF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit
is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device
is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the
block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory that
are not block-protected.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to “0” as long as the WP pin is held low.
Table 4-5.
WPEN Operation
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
X
WEN
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writeable
Protected
Writeable
Protected
Writeable
Protected
Writeable
Protected
Protected
Protected
Writeable
X
Low
Low
High
High
READ SEQUENCE (READ): Reading the AT25080B/160B via the Serial Output (SO) pin requires the following
sequence. After the CS line is pulled low to select a device, the read op-code is transmitted via the SI line followed
by the byte address to be read (A15–A0, see Table 3-6). Upon completion, any data on the SI line will be ignored.
The data (D7–D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The read sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highest address is reached, the
address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read
cycle.
8
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
WRITE SEQUENCE (WRITE): In order to program the AT25080B/160B, two separate instructions must be exe-
cuted. First, the device must be write enabled via the WREN instruction. Then a write (WRITE) instruction may be
executed. Also, the address of the memory location(s) to be programmed must be outside the protected address
field location selected by the block write protection level. During an internal write cycle, all commands will be
ignored except the RDSR instruction.
A write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE
op-code is transmitted via the SI line followed by the byte address (A15–A0) and the data (D7–D0) to be pro-
grammed (see Table 3-6). Programming will start after the CS pin is brought high. The low-to-high transition of the
CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a read status register
(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the
RDSR instruction is enabled during the write programming cycle.
The AT25080B/160B is capable of a 32-byte page write operation. After each byte of data is received, the five low-
order address bits are internally incremented by one; the high-order bits of the address will remain constant. If
more than 32 bytes of data are transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25080B/160B is automatically returned to the write disable state at the completion of a write
cycle.
Note:
If the device is not write-enabled (WREN), the device will ignore the write instruction and will return to the standby
state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication.
Table 4-6.
Address Key
Address
AN
Don’t Care Bits
AT25080B
A9–A0
AT25160B
A10–A0
A15–A10
A15–A11
9
5228E–SEEPR–3/12
5.
Timing Diagrams
Figure 5-1. Synchronous Data Timing (for Mode 0)
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
tWL
SCK
VIL
tSU
tH
VIH
VIL
VALID IN
SI
tHO
tDIS
tV
VOH
VOL
HI-Z
HI-Z
SO
Figure 5-2. WREN Timing
CS
SCK
SI
WREN OP-CODE
HI-Z
SO
Figure 5-3. WRDI Timing
CS
SCK
SI
WRDI OP-CODE
HI-Z
SO
10
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
Figure 5-4. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
Figure 5-5. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
DATA IN
INSTRUCTION
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 5-6. READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30
SCK
SI
BYTE ADDRESS
...
INSTRUCTION
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
11
5228E–SEEPR–3/12
Figure 5-7. WRITE Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
BYTE ADDRESS
DATA IN
...
INSTRUCTION
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 5-8. HOLD Timing
CS
tCD
tCD
SCK
HOLD
SO
tHD
tHD
tHZ
tLZ
12
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
6.
Ordering Code Detail
A T 2 5 0 8 0 B - S S H L - B
Atmel Designator
Product Family
Device Density
Shipping Carrier Option
B or blank = Bulk (tubes)
Tape and reel
T
=
Operating Voltage
L
=
1.8V to 5.5V
080 = 8-kilobit
160 = 16-kilobit
Packaged Device Grade or
Wafer/Die Thickness
Device Revision
H
=
=
=
Green, NiPdAu lead finish
Temperature range -40°C to +85°C
Green, matte Sn lead finish
Temperature range -40°C to +85°C
11 mil wafer thickness
U
11
Package Option
SS
X
MA
ME
C
=
=
=
=
=
JEDEC SOIC
TSSOP
UDFN
XDFN
VFBGA
WWU = Wafer unsawn
WDT = Die in Tape and Reel
13
5228E–SEEPR–3/12
7.
Part Markings
AT25080B
7.1
AT25080B-SSHL
Top Mark
Seal Year
| Seal Week
| | |
@ = Country of Ass’y
Y = SEAL YEAR
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
52 = Week 52
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
6:2006
7:2007
8:2008
9:2009
0: 2010
1: 2011
2: 2012
3: 2013
5 8 B
L
@
|---|---|---|---|---|---|---|---|
* LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
AT25080B-XHL
Top Mark
PIN 1 INDICATOR (DOT)
@ = Country of Ass’y
Y = SEAL YEAR
|
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
52 = Week 52
* |---|---|---|---|---|---|
A T H Y W W
|---|---|---|---|---|---|
8:2008
9:2009
0:2010
1:2011
2: 2012
3: 2013
4: 2014
5: 2015
5 8 B L
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
AT25080B-MAHL
Top Mark
Y = YEAR OF ASSEMBLY
@ = Country of Ass’y
|---|---|---|
5 8 B
|---|---|---|
H L @
|---|---|---|
Y X X
|---|---|---|
*
XX= ATMEL LOT NUMBER TO COORESPOND
WITH TRACE CODE LOG BOOK
(e.g. XX = AA, AB, AC,... AX, AY AZ)
Y = SEAL YEAR
6:2006
7:2007
8:2008
9:2009
0: 2010
1: 2011
2: 2012
3: 2013
|
PIN 1 INDICATOR (DOT)
14
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
AT25080B-MEHL
Top Mark
Y = YEAR OF ASSEMBLY
|---|---|---|
XX= ATMEL LOT NUMBER TO COORESPOND
WITH TRACE CODE LOG BOOK
5 8 B
|---|---|---|
(e.g. XX = AA, AB, AC,... AX, AY AZ)
Y = SEAL YEAR
Y X X
|---|---|---|
6:2006
7:2007
8:2008
9:2009
0: 2010
1: 2011
2: 2012
3: 2013
*
|
PIN 1 INDICATOR (DOT)
AT25080B-CUL
Top Mark
|---|---|---|---|
5 8 B U
B = Country of Origin
Y = One Digit Year Code
M = One Digit Month Code
|---|---|---|---|
B Y M X X
|---|---|---|---|---|
* <-- PIN 1 INDICATOR
XX= TRACE CODE (ATMEL LOT NUMBER TO
COORESPOND WITH TRACE CODE LOG BOOK)
(e.g. XX = AA, AB, AC,... YZ, ZZ)
M = SEAL MONTH
(USE ALPHA DESIGNATOR A-L)
Y = ONE DIGIT YEAR CODE
4:2004
5:2005
6:2006
7: 2007
8: 2008
9: 2009
A = JANUARY
B = FEBRUARY
" " """"""""
J = OCTOBER
K = NOVEMBER
L = DECEMBER
15
5228E–SEEPR–3/12
7.2
AT25160B
AT25160B-SSHL
Top Mark
Seal Year
| Seal Week
| | |
@ = Country of Ass’y
Y = SEAL YEAR
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
52 = Week 52
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
6:2006
7:2007
8:2008
9:2009
0: 2010
1: 2011
2: 2012
3: 2013
5 A B
L
@
|---|---|---|---|---|---|---|---|
* LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
AT25160B-XHL
Top Mark
PIN 1 INDICATOR (DOT)
@ = Country of Ass’y
Y = SEAL YEAR
|
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
52 = Week 52
* |---|---|---|---|---|---|
A T H Y W W
|---|---|---|---|---|---|
8:2008
9:2009
0:2010
1:2011
2: 2012
3: 2013
4: 2014
5: 2015
5 A B L
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
AT25160B-MAHL
Top Mark
Y = YEAR OF ASSEMBLY
@ = Country of Ass’y
|---|---|---|
5 A B
|---|---|---|
H L @
|---|---|---|
Y X X
|---|---|---|
*
XX= ATMEL LOT NUMBER TO COORESPOND
WITH TRACE CODE LOG BOOK
(e.g. XX = AA, AB, AC,... AX, AY AZ)
Y = SEAL YEAR
6:2006
7:2007
8:2008
9:2009
0: 2010
1: 2011
2: 2012
3: 2013
|
PIN 1 INDICATOR (DOT)
16
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
AT25160B-MEHL
Top Mark
Y = YEAR OF ASSEMBLY
|---|---|---|
XX= ATMEL LOT NUMBER TO COORESPOND
WITH TRACE CODE LOG BOOK
5 A B
|---|---|---|
(e.g. XX = AA, AB, AC,... AX, AY AZ)
Y = SEAL YEAR
Y X X
|---|---|---|
6:2006
7:2007
8:2008
9:2009
0: 2010
1: 2011
2: 2012
3: 2013
*
|
PIN 1 INDICATOR (DOT)
AT25160B-CUL
Top Mark
|---|---|---|---|
5 A B U
B = Country of Origin
Y = One Digit Year Code
M = One Digit Month Code
|---|---|---|---|
B Y M X X
|---|---|---|---|---|
* <-- PIN 1 INDICATOR
XX= TRACE CODE (ATMEL LOT NUMBER TO
COORESPOND WITH TRACE CODE LOG BOOK)
(e.g. XX = AA, AB, AC,... YZ, ZZ)
M = SEAL MONTH
(USE ALPHA DESIGNATOR A-L)
Y = ONE DIGIT YEAR CODE
4:2004
5:2005
6:2006
7: 2007
8: 2008
9: 2009
A = JANUARY
B = FEBRUARY
" " """"""""
J = OCTOBER
K = NOVEMBER
L = DECEMBER
17
5228E–SEEPR–3/12
8.
Ordering Codes
AT25080B Ordering Information
Ordering Code
Voltage
Package
Operation Range
AT25080B-SSHL-B(1) (NiPdAu Lead Finish)
AT25080B-SSHL-T(2) (NiPdAu Lead Finish)
AT25080B-XHL-B(1) (NiPdAu Lead Finish)
AT25080B-XHL-T(2) (NiPdAu Lead Finish)
AT25080B-MAHL-T(2) (NiPdAu Lead Finish)
AT25080B-MEHL-T(2) (NiPdAu Lead Finish)
AT25080B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8X
Lead-free/Halogen-free/
Industrial Temperature
8X
(40 to 85C)
8MA2
8ME1
8U3-1
Industrial Temperature
AT25080B-WWU11L(3)
1.8V to 5.5V
Die Sale
(40 to 85C)
Note:
1. Bulk delivery in tubes (SOIC and TSSOP 100/tube)
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel)
3. Contact Atmel Sales for Wafer sales
Package Type
8S1
8X
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin, Dual No Lead Package (UDFN)
8-lead (1.80 mm x 2.20 mm Body) Extra Thin DFN (XDFN)
8ME1
8U3-1
8-ball, die Ball Grid Array Package (VFBGA)
18
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
AT25160B Ordering Information
Ordering Code
Voltage
Package
Operation Range
AT25160B-SSHL-B(1) (NiPdAu Lead Finish)
AT25160B-SSHL-T(2) (NiPdAu Lead Finish)
AT25160B-XHL-B(1) (NiPdAu Lead Finish)
AT25160B-XHL-T(2) (NiPdAu Lead Finish)
AT25160B-MAHL-T(2) (NiPdAu Lead Finish)
AT25160B-MEHL-T(2) (NiPdAu Lead Finish)
AT25160B-CUL-T(2) (SnAgCu Ball Finish)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
8S1
8S1
8X
Lead-free/Halogen-free/
Industrial Temperature
8X
(40 to 85C)
8MA2
8ME1
8U3-1
Industrial Temperature
AT25160B-WWU11L(3)
1.8V to 5.5V
Die Sale
(40 to 85C)
Note:
1. Bulk delivery in tubes (SOIC and TSSOP 100/tube)
2. Tape and reel delivery (SOIC 4k/reel. TSSOP, UDFN, XDFN and VFBGA 5k/reel)
3. Contact Atmel Sales for Wafer sales
Package Type
8S1
8X
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin, Dual No Lead Package (UDFN)
8-lead (1.80 mm x 2.20 mm Body) Extra Thin DFN (XDFN)
8ME1
8U3-1
8-ball, die Ball Grid Array Package (VFBGA)
19
5228E–SEEPR–3/12
9.
Packaging Information
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
–
–
NOTE
SYMBOL
A1
A
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
C
D
E1
E
e
–
–
D
–
–
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
1.27 BSC
L
0.40
0°
–
–
1.27
8°
Ø
6/22/11
DRAWING NO. REV.
8S1
TITLE
GPC
SWB
Package Drawing Contact:
packagedrawings@atmel.com
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC)
G
20
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
8X – TSSOP
C
Pin 1 indicator
this corner
E1
E
L1
H
L
Top View
End View
A
b
A1
COMMON DIMENSIONS
(Unit of Measure = mm)
e
A2
MIN
-
MAX
1.20
0.15
1.05
3.10
NOM
NOTE
2, 5
SYMBOL
D
A
-
Side View
A1
A2
D
0.05
0.80
2.90
-
1.00
Notes: 1. This drawing is for general information only. Refer to JEDEC
Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
3.00
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
E
6.40 BSC
4.40
E1
b
4.30
0.19
4.50
0.30
3, 5
4
–
e
0.65 BSC
0.60
4. Dimension b does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08 mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
L
0.45
0.09
0.75
0.20
L1
C
1.00 REF
-
5. Dimension D and E1 to be determined at Datum Plane H.
12/8/11
REV.
TITLE
GPC
TNR
DRAWING NO.
8X
Package Drawing Contact:
packagedrawings@atmel.com
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
E
21
5228E–SEEPR–3/12
8MA2 - UDFN
E
1
2
3
4
8
7
6
5
Pin 1 ID
D
C
A2
A1
A
E2
COMMON DIMENSIONS
(Unit of Measure = mm)
b (8x)
MIN
MAX
NOM
2.00 BSC
3.00 BSC
1.50
NOTE
SYMBOL
8
7
6
1
2
3
4
D
E
D2
E2
A
1.40
1.20
0.50
0.0
1.60
1.40
0.60
0.05
0.55
Pin#1 ID
D2
1.30
0.55
A1
A2
C
0.02
5
–
–
e (6x)
0.152 REF
0.35
L (8x)
K
L
0.30
0.40
e
0.50 BSC
0.25
b
0.18
0.20
0.30
–
3
K
–
7/15/11
GPC
YNZ
DRAWING NO.
TITLE
REV.
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
Package Drawing Contact:
packagedrawings@atmel.com
8MA2
B
22
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
8ME1 - XDFN
D
e1
b
7
5
6
8
L
E
PIN #1 ID
0.10
0.15
PIN #1 ID
A1
2
4
1
3
b
e
A
BOTTOM VIEW
SIDE VIEW
TOP VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
NOTE
SYMBOL
A
-
-
0.40
A1
D
E
0.00
1.70
2.10
0.15
-
0.05
1.90
2.30
0.25
1.80
2.20
b
0.20
e
0.40 TYP
1.20 REF
0.30
e1
L
0.26
0.35
8/3/09
GPC
DTP
DRAWING NO.
TITLE
REV.
8ME1, 8-lead (1.80x2.20mm Body) Extra Thin
Package Drawing Contact:
packagedrawings@atmel.com
8ME1
A
DFN (XDFN)
23
5228E–SEEPR–3/12
8U3-1 - VFBGA
E
D
5.
b
1
A
PIN 1 BALL PAD CORNER
2
A
A
TOP VIEW
SIDE VIEW
PIN 1 BALL PAD CORNER
2
4
1
3
d
(d1)
6
5
8
7
COMMON DIMENSIONS
(Unit of Measure - mm)
e
(e1)
SYMBOL
NOM
MIN
MAX
NOTE
A
0.73
0.09
0.40
0.20
0.79
0.85
0.19
0.50
0.30
BOTTOM VIEW
8 SOLDER BALLS
A1
A2
b
0.14
0.45
Notes:
0.25
2
1. This drawing is for general information only.
D
1.50 BSC
2.0 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
E
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
e
e1
d
d1
07/14/10
TITLE
GPC
DRAWING NO.
REV.
Package Drawing Contact:
packagedrawings@atmel.com
8U3-1, 8-ball, 1.50 x 2.00 mm Body,
0.50 pitch, VFBGA Package (dBGA2)
GXU
8U3-1
D
24
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
10. Revision History
Doc. Rev.
5228E
Date
Comments
03/2012
04/2010
Update 8A2 to 8X and 8S1, 8MA2, 8U3-1 package drawings
Update Ordering Code Detail and Ordering Information
5228D
Change Catalog Scheme
Add Marking Details
5228C
08/2009
5228B
5228A
07/2008
09/2007
Change ‘Endurance’ parameter on page 6
Initial document release
25
5228E–SEEPR–3/12
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Atmel Japan G.K.
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www.atmel.com
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Fax: (+852) 2722-1369
© 2012 Atmel Corporation. All rights reserved. / Rev.: 5228E–SEEPR–3/12
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities™, and others are registered trademarks or trademarks of Atmel Corporation or its
subsidiaries. Other terms and product names may be trademarks of others.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this
document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES
NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF
INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
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