AT25128A-10PU-2.7 [ATMEL]
SPI Serial EEPROMs; SPI串行EEPROM
| 型号： | AT25128A-10PU-2.7 |
| 厂家： | 
ATMEL |
| 描述： | SPI Serial EEPROMs |
| 文件： | 总21页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Data Sheet Describes Mode 0 Operation
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• 20 MHz Clock Rate (5V)
• 64-byte Page Mode and Byte Write Operation
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
• Self-timed Write Cycle (5 ms Max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
• Automotive Grade, Extended Temperature and Lead-free/Halogen-free
Devices Available
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and
8-lead SAP Packages
• Die Sales: Wafer Form, Waffle Pack, and Bumped Die
AT25128A
AT25256A
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable
programmable read only memory (EEPROM) organized as 16,384/32,768 words of
8 bits each. The device is optimized for use in many industrial and commercial appli-
cations where low-power and low-voltage operation are essential. The devices are
available in space saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-
lead TSSOP, 8-ball dBGA2 and 8-lead SAP packages. In addition, the entire family is
available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via
a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate Erase cycle is required before Write.
8-lead SOIC
8-lead PDIP
Table 1. Pin Configurations
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Pin Name
CS
Function
WP
WP
GND
GND
Chip Select
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
8-lead SAP
8-lead TSSOP
VCC
8
7
6
5
1
2
3
4
CS
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
HOLD
SCK
SI
SO
SO
WP
GND
WP
GND
VCC
WP
GND
Bottom View
8-ball dBGA2
Power Supply
Write Protect
Suspends Serial Input
No Connect
8
7
6
5
1
2
3
4
CS
VCC
SO
HOLD
SCK
WP
GND
HOLD
NC
SI
Bottom View
3368H–SEEPR–8/05
Block Write protection is enabled by programming the status register with top ¼, top ½
or entire array of write protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware data protection is pro-
vided via the WP pin to protect against inadvertent write attempts to the status register.
The HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
16384/32768x8
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
COUT
CIN
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
2
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
Table 3. DC Characteristics
Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +5.5V,
AE = −40°C to +125°C, VCC = +1.8V to +5.5V(unless otherwise noted)
T
Symbol
VCC1
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
5.5
5.5
Units
Supply Voltage
Supply Voltage
Supply Voltage
V
V
V
VCC2
VCC3
5.5
V
Read
CC = 5.0V at 20 MHz, SO = Open,
ICC1
ICC2
ICC3
Supply Current
Supply Current
Supply Current
9.0
5.0
2.2
10.0
7.0
mA
mA
mA
VCC = 5.0V at 10 MHz,
SO = Open, Read, Write
VCC = 5.0V at 1 MHz,
SO = Open, Read, Write
3.5
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V, CS = VCC
VCC = 2.7V, CS = VCC
VCC = 5.0V, CS = VCC
VIN = 0V to VCC
0.2
0.5
2.0
3.0
3.0
µA
µA
µA
µA
µA
V
5.0
−3.0
−3.0
3.0
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(1)
VIL
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
Output Low-voltage
Output High-voltage
−1.0
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
VCC x 0.7
V
VOL1
VOH1
VOL2
VOH2
I
OL = 3.0 mA
V
3.6 ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 3.6V
IOH = −1.6 mA
IOL = 0.15 mA
IOH = −100 µA
VCC −0.8
VCC −0.2
V
0.2
V
V
Note:
1. VIL and VIH max are reference only and are not tested.
Table 4. AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, TAE = −40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
4.5−5.5
2.7−5.5
1.8−5.5
0
0
0
20
10
5
fSCK
SCK Clock Frequency
MHz
4.5−5.5
2.7−5.5
1.8−5.5
2
2
2
tRI
Input Rise Time
Input Fall Time
SCK High Time
µs
µs
ns
4.5−5.5
2.7−5.5
1.8−5.5
2
2
2
tFI
4.5−5.5
2.7−5.5
1.8−5.5
20
40
80
tWH
3
3368H–SEEPR–8/05
Table 4. AC Characteristics (Continued)
Applicable over recommended operating range from TAI = −40°C to + 85°C, TAE = −40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
4.5−5.5
2.7−5.5
1.8−5.5
20
40
80
tWL
SCK Low Time
ns
4.5−5.5
2.7−5.5
1.8−5.5
100
100
200
tCS
tCSS
tCSH
tSU
tH
CS High Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5−5.5
2.7−5.5
1.8−5.5
100
100
200
CS Setup Time
4.5−5.5
2.7−5.5
1.8−5.5
100
100
200
CS Hold Time
4.5−5.5
2.7−5.5
1.8−5.5
5
10
20
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
4.5−5.5
2.7−5.5
1.8−5.5
5
10
20
4.5−5.5
2.7−5.5
1.8−5.5
5
10
20
tHD
tCD
tV
4.5−5.5
2.7−5.5
1.8−5.5
5
10
20
4.5−5.5
2.7−5.5
1.8−5.5
0
0
0
20
40
80
Output Valid
4.5−5.5
2.7−5.5
1.8−5.5
0
0
0
tHO
Output Hold Time
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
4.5−5.5
2.7−5.5
1.8−5.5
0
0
0
25
50
100
tLZ
4.5−5.5
2.7−5.5
1.8−5.5
25
50
100
tHZ
4.5−5.5
2.7−5.5
1.8−5.5
25
50
100
tDIS
4.5−5.5
2.7−5.5
1.8−5.5
5
5
5
tWC
Write Cycle Time
ms
Endurance(1)
5.0V, 25°C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
4
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128A/256A
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will
be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25128A/256A, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25128A/256A is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25128A/256A. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25128A/256A in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
5
3368H–SEEPR–8/05
Figure 2. SPI Serial Interface
AT25128A/256A
6
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
Functional
Description
The AT25128A/256A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6800 type series of microcontrollers.
The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in see Table 5. All instructions, addresses, and data
are transferred with the MSB first and start with a high-to-low CS transition.
Table 5. Instruction Set for the AT25128A/256A
Instruction Name
WREN
Instruction Format
0000 X110
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRDI
0000 X100
RDSR
0000 X101
WRSR
0000 X001
READ
0000 X011
WRITE
0000 X010
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The Ready/Busy and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 7. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates the device is not write enabled. Bit 1 = “1” indicates
the device is write enabled.
Bit 2 (BP0)
See Table 8 on page 8.
See Table 8 on page 8.
Bit 3 (BP1)
Bits 4 − 6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 9 on page 8.
Bits 0 − 7 are “1”s during an internal write cycle.
7
3368H–SEEPR–8/05
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25128A/256A is divided into four array segments.
Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of
the data within any selected segment will therefore be read only. The block write protec-
tion levels and corresponding status register control bits are shown in Table 8.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g. WREN, tWC, RDSR).
Table 8. Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
0
BP1
BP0
AT25128A
None
AT25256A
None
0
0
1
1
0
1
0
1
1(1/4)
2(1/2)
3(All)
3000 – 3FFF
2000 – 3FFF
0000 – 3FFF
6000 – 7FFF
4000 – 7FFF
0000 – 7FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hard-
ware write protected, writes to the Status Register, including the Block Protect bits and
the WPEN bit, and the block-protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0”, as long as the WP pin is held low.
Table 9. WPEN Operation
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
X
WEN
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
READ SEQUENCE (READ): Reading the AT25128A/256A via the SO pin requires the
following sequence. After the CS line is pulled low to select a device, the Read op-code
is transmitted via the SI line followed by the byte address to be read (see Table 10 on
page 9). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at
the specified address is then shifted out onto the SO line. If only one byte is to be read,
the CS line should be driven high after the data comes out. The read sequence can be
continued since the byte address is automatically incremented and data will continue to
be shifted out. When the highest address is reached, the address counter will roll over to
the lowest address allowing the entire memory to be read in one continuous read cycle.
8
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
WRITE SEQUENCE (WRITE): In order to program the AT25128A/256A, two separate
instructions must be executed. First, the device must be write enabled via the Write
Enable (WREN) Instruction. Then a Write instruction may be executed. Also, the
address of the memory location(s) to be programmed must be outside the protected
address field location selected by the Block Write Protection Level. During an internal
write cycle, all commands will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to
select the device, the Write op-code is transmitted via the SI line followed by the byte
address and the data (D7 - D0) to be programmed (see Table 10). Programming will
start after the CS pin is brought high. (The Low-to-High transition of the CS pin must
occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status
Register (RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0,
the Write cycle has ended. Only the Read Status Register instruction is enabled during
the Write programming cycle.
The AT25128A/256A is capable of a 64-byte Page Write operation. After each byte of
data is received, the six low order address bits are internally incremented by one; the
high order bits of the address will remain constant. If more than 64 bytes of data are
transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25128A/256A is automatically returned to the write disable state at
the completion of a Write cycle.
NOTE: If the device is not write enabled (WREN), the device will ignore the Write
instruction and will return to the standby state, when CS is brought high. A new CS fall-
ing edge is required to re-initiate the serial communication.
Table 10. Address Key
Address
AN
AT25128A
A13 − A0
AT25256A
A14 − A0
A15
Don’t Care Bits
A15 − A14
9
3368H–SEEPR–8/05
Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 3. Synchronous Data Timing
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
tWL
SCK
VIL
tSU
tH
VIH
VIL
SI
VALID IN
tHO
tDIS
tV
VOH
VOL
HI-Z
HI-Z
SO
Figure 4. WREN Timing
Figure 5. WRDI Timing
10
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
Figure 6. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
Figure 7. WRSR Timing
Figure 8. READ Timing
11
3368H–SEEPR–8/05
Figure 9. WRITE Timing
Figure 10. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
SO
tLZ
12
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
AT25128A Ordering Information(1)
Ordering Code
Package
Operation Range
AT25128A-10PI-2.7
AT25128AN-10SI-2.7
AT25128AW-10SI-2.7
AT25128A-10TI-2.7
8P3
8S1
8S2
8A2
Industrial Temperature
(−40°C to 85°C)
AT25128A-10PI-1.8
AT25128AN-10SI-1.8
AT25128AW-10SI-1.8
AT25128A-10TI-1.8
8P3
8S1
8S2
8A2
Industrial Temperature
(−40°C to 85°C)
AT25128A-10PU-2.7(2)
AT25128A-10PU-1.8(2)
AT25128AN-10SU-2.7(2)
AT25128AN-10SU-1.8(2)
AT25128AW-10SU-2.7(2)
AT25128AW-10SU-1.8(2)
AT25128A-10TU-2.7(2)
AT25128A-10TU-1.8(2)
AT25128AU2-10UU-1.8(2)
AT25128AY4-10YU-1.8(2)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U2-1
8Y4
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT25128A-W2.7-11(3)
AT25128A-W1.8-11(3)
Die Sale
Die Sale
Industrial Temperature
(−40°C to 85°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
2. “U” designates Green package + RoHS compliant.
3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please Contact
Serial EEPROM Marketing.
Package Type
8P3
8S1
8S2
8U2-1
8A2
8Y4
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8-ball, die Ball Grid Array Package (dBGA2)
8-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP)
8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
−2.7
−1.8
Low-voltage (2.7V to 5.5V)
Low-voltage (1.8V to 5.5V)
13
3368H–SEEPR–8/05
AT25256A Ordering Information(1)
Ordering Code
Package
Operation Range
AT25256A-10PI-2.7
AT25256AN-10SI-2.7
AT25256AW-10SI-2.7
AT25256A-10TI-2.7
8P3
8S1
8S2
8A2
Industrial Temperature
(−40°C to 85°C)
AT25256A-10PI-1.8
AT25256AN-10SI-1.8
AT25256AW-10SI-1.8
AT25256A-10TI-1.8
8P3
8S1
8S2
8A2
Industrial Temperature
(−40°C to 85°C)
AT25256A-10PU-2.7(2)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
AT25256A-10PU-1.8(2)
AT25256AN-10SU-2.7(2)
AT25256AN-10SU-1.8(2)
AT25256AW-10SU-2.7(2)
AT25256AW-10SU-1.8(2)
AT25256A-10TU-2.7(2)
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT25256A-10TU-1.8(2)
8A2
8U2-1
AT25256AU2-10UU-1.8(2)
AT25256AY4-10YU-1.8(2)
8Y4
AT25256A-W2.7-11(3)
Die Sale
Die Sale
Industrial Temperature
(−40°C to 85°C)
AT25256A-W1.8-11(3)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
2. “U” designates Green package + RoHS compliant.
3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact
Serial EEPROM Marketing.
Package Type
8P3
8S1
8S2
8U2-1
8A2
8Y4
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8-ball, die Ball Grid Array Package (dBGA2)
8-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP)
8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
−2.7
−1.8
Low-voltage (2.7V to 5.5V)
Low-voltage (1.8V to 5.5V)
14
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
15
3368H–SEEPR–8/05
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
∅
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
16
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
8S2 – EIAJ SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0°
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8°
NOM
NOTE
SYMBOL
A1
A
A1
b
5
5
C
D
E1
E
D
2, 3
Side View
L
∅
e
1.27 BSC
4
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
TITLE
REV.
DRAWING NO.
2325 Orchard Parkway
San Jose, CA 95131
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
8S2
C
R
17
3368H–SEEPR–8/05
8U2-1 – dBGA2
D
A1 BALL PAD CORNER
1.
b
E
A1
A
A2
Top View
A1 BALL PAD CORNER
Side View
2
1
A
B
C
D
e
(e1)
d
(d1)
COMMON DIMENSIONS
(Unit of Measure = mm)
Bottom View
8 Solder Balls
SYMBOL
MAX
1.00
0.25
0.50
0.35
MIN
0.81
0.15
0.40
0.25
NOM
0.91
NOTE
A
A1
A2
b
0.20
0.45
0.30
1
D
2.35 BSC
3.73 BSC
0.75 BSC
0.74 REF
0.75 BSC
0.80 REF
1. Dimension 'b' is measured at the maximum solder ball diameter.
This drawing is for general information only.
E
e
e1
d
d1
6/24/03
TITLE
REV.
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
R
PO8U2-1
A
18
AT25128A/256A
3368H–SEEPR–8/05
AT25128A/256A
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
19
3368H–SEEPR–8/05
8Y4 – SAP
PIN 1 INDEX AREA
A
PIN 1 ID
D
E1
L
A1
E
e
b
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
MAX
0.90
0.05
6.20
5.10
3.15
3.15
0.45
NOM
–
NOTE
A
A1
D
0.00
5.80
4.70
2.85
2.85
0.35
–
6.00
E
4.90
D1
E1
b
3.00
3.00
0.40
e
1.27 TYP
3.81 REF
0.60
e1
L
0.50
0.70
5/24/04
DRAWING NO.
REV.
TITLE
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package
(SAP) Y4
8Y4
A
R
20
AT25128A/256A
3368H–SEEPR–8/05
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Microcontrollers
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Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Europe
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Fax: (33) 2-40-18-19-60
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Room 1219
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Tel: (852) 2721-9778
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Tel: (33) 4-42-53-60-00
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Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
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Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
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Printed on recycled paper.
3368H–SEEPR–8/05
相关型号：
AT25128A-10TU-2.7SL735
EEPROM, 16KX8, Serial, CMOS, PDSO8, 4.40 MM, GREEN, PLASTIC, MO-153AA, TSSOP-8
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