AT25128-10SI [ATMEL]
SPI Serial E2PROMs; SPI串行串行E2PROM
| 型号： | AT25128-10SI |
| 厂家： | 
ATMEL |
| 描述： | SPI Serial E2PROMs |
| 文件： | 总12页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Low Voltage and Standard Voltage Operation
•
•
•
5.0 (VCC = 4.5V to 5.5V)
2.7 (VCC = 2.7V to 5.5V)
1.8 (VCC = 1.8V to 3.6V)
2.1 MHz Clock Rate
32-Byte Page Mode
Block Write Protection
•
•
•
Protect 1/4, 1/2, or Entire Array
SPI Serial
E2PROMs
128K (16384 x 8)
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-Timed Write Cycle (5 ms Typical)
High Reliability
•
•
•
Endurance: 100,000 Cycles
Data Retention: 100 Years
Automotive Grade and Extended Temperature Devices Available
8-Pin PDIP, 14-pin, 16-pin JEDEC SOIC, and 20-Pin TSSOP Packages
•
•
AT25128
Preliminary
Description
The AT25128 provides 131,072 bits of serial electrically erasable programmable read
only memory (EEPROM) organized as 16,384 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT25128 is available in space saving
8-pin PDIP, JEDEC SOIC, and 14-pin and 20-pin TSSOP packages.
(continued)
Pin Configurations
Pin Name
Function
CS
Chip Select
8-Pin PDIP
14-Pin SOIC
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
CS
SO
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
HOLD
NC
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
NC
SO
NC
NC
WP
NC
NC
GND
VCC
GND
WP
GND
SCK
SI
Power Supply
Write Protect
Suspends Serial Input
No Connect
8
WP
HOLD
NC
DC
Don’t Connect
20-Lead TSSOP*
16-Lead SOIC
NC
CS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
VCC
HOLD
HOLD
NC
CS
SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
SO
HOLD
NC
SO
NC
NC
NC
NC
NC
NC
NC
NC
WP
GND
DC
SCK
SI
NC
NC
WP
GND
SCK
SI
DC
NC
NC
* Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility.
Description (Continued)
The AT25128 is enabled through the Chip Select pin (CS)
and accessed via a 3-wire interface consisting of Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK). All programming cycles are completely self-timed,
and no separate ERASE cycle is required before WRITE.
tions are provided for additional data protection. Hardware
data protection is provided via the WP pin to protect
against inadvertent write attempts to the status register.
The HOLD pin may be used to suspend any serial commu-
nication without resetting the serial sequence.
BLOCK WRITE protection is enabled by programming the
status register with one of four blocks of write protection.
Separate program enable and program disable instruc-
Absolute Maximum Ratings*
Operating Temperature................... -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Voltage on Any Pin
with Respect to Ground ..................... -1.0V to +7.0V
Maximum Operating Voltage ........................... 6.25V
DC Output Current......................................... 5.0 mA
Block Diagram
2
AT25128
AT25128
Pin Capacitance (1)
Applicable over recommended operating range from T = 25°C, f = 1.0 MHz, V = +5.0V (unless otherwise noted).
A
CC
Test Conditions
Max
8
Units
pF
Conditions
C
C
Output Capacitance (SO)
V
V
= 0V
OUT
OUT
IN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
= 0V
IN
Note: 1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: T = -40°C to +85°C, V = +1.8V to +5.5V,
AI
CC
T
= 0°C to +70°C, V = +1.8V to +5.5V (unless otherwise noted).
CC
AC
Symbol
Parameter
Test Condition
Min
Typ
Max
3.6
Units
V
CC1
V
CC2
V
CC3
Supply Voltage
Supply Voltage
Supply Voltage
1.8
2.7
4.5
V
V
V
5.5
5.5
V
= 5.0V at 1 MHz,
CC
I
I
Supply Current
Supply Current
3.0
5.0
mA
mA
CC1
SO = Open
V
CC
= 5.0V at 2 MHz,
CC2
SO = Open
I
I
I
I
Standby Current
Standby Current
Standby Current
Input Leakage
V
V
V
V
V
= 1.8V
= 2.7V
= 5.0V
CS = V
CS = V
CS = V
0.1
0.5
2.0
3.0
µA
µA
µA
µA
SB1
SB2
SB3
IL
CC
CC
CC
CC
CC
CC
0.2
0.5
= 0V to V
-3.0
-3.0
IN
CC
CC
= 0V to V
= 0°C to 70°C
,
IN
I
OL
Output Leakage
3.0
µA
T
AC
(1)
(1)
V
V
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
-1.0
V
x 0.3
+ 0.5
0.4
V
V
V
V
V
V
IL
CC
V
x 0.7
V
CC
IH
CC
I
= 3.0 mA
= -1.6 mA
= 0.15 mA
= -100 µA
OL1
OH1
OL2
OH2
OL
4.5V ≤ V ≤ 5.5V
CC
I
V
V
- 0.8
- 0.2
OH
CC
I
OL
0.2
1.8V ≤ V ≤ 3.6V
CC
I
OH
CC
Note: 1. VIL min and VIH max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from T = -40°C to +85°C, V = As Specified,
A
CC
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter
Voltage
Min
Max
Units
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
2.1
2.1
0.5
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCK Clock Frequency
Input Rise Time
Input Fall Time
MHz
SCK
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
2
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RI
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
2
FI
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
300
800
SCK High Time
SCK Low Time
CS High Time
WH
WL
CS
CSS
CSH
SU
H
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
200
800
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
CS Setup Time
CS Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
50
100
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
50
100
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100
400
HD
CD
V
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100
400
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
200
200
800
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
Output Hold Time
Hold to Output Low Z
HO
LZ
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
100
100
100
(continued)
4
AT25128
AT25128
AC Characteristics (Continued)
Symbol Parameter
Voltage
Min
Max
Units
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100
100
t
t
t
Hold to Output High Z
Output Disable Time
Write Cycle Time
ns
HZ
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
ns
DIS
WC
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
5
10
20
ms
5
Serial Interface Description
MASTER: The device that generates the serial clock.
SPI Serial Interface
SLAVE: Because the Serial Clock pin (SCK) is always
an input, the AT25128 always operates as a slave.
TRANSMITTER/RECEIVER: T h e A T 2 5 1 2 8 h a s
separate pins designated for data transmission (SO) and
reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit
transmitted and received.
SERIAL OP-CODE: After the device is selected with CS
going low, the first byte will be received. This byte contains
the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received,
no data will be shifted into the AT25128, and the serial
output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitial-
ize the serial communication.
CHIP SELECT: The AT25128 is selected when the CS
pin is low. When the device is not selected, data will not be
accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with theCS
pin to select the AT25128. When the device is selected
and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device
without resetting the serial sequence. To pause, the
HOLD pin must be brought low while the SCK pin is low.
To resume serial communication, the HOLD pin is brought
high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO
pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow
normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is “1", all write opera-
tions to the status register are inhibited. WP going low
while CS is still low will interrupt a write to the status reg-
ister. If the internal write cycle has already been initiated,
WP going low will have no effect on any write operation to
the status register. The WP pin function is blocked when
the WPEN bit in the status register is ”0". This will allow the
user to install the AT25128 in a system with the WP pin
tied to ground and still be able to write to the status regis-
ter. All WP pin functions are enabled when the WPEN bit
is set to “1".
6
AT25128
AT25128
Table 2b. Read Status Register Bit Definition
Functional Description
The AT25128 is designed to interface directly with the syn-
chronous serial peripheral interface (SPI) of the 6805 and
68HC11 series of microcontrollers.
Bit
Definition
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write cycle is
in progress.
Bit 0 (RDY)
The AT25128 utilizes an 8 bit instruction register. The list
of instructions and their operation codes are contained in
Table 1. All instructions, addresses, and data are trans-
ferred with the MSB first.
Bit 1= 0 indicates the device is not WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
See Table 3.
See Table 3.
Table 1. Instruction Set for the AT25128
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 4.
Instruction Instruction
Bits 0-7 are 1s during an internal write cycle.
Name
WREN
WRDI
Format
Operation
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRITE STATUS REGISTER (WRSR): The WRSR in-
struction allows the user to select one of four levels of pro-
tection. The AT25128 is divided into four array segments.
One quarter (1/4), one half (1/2), or all of the memory seg-
ments can be protected. Any of the data within any se-
lected segment will therefore be READ only. The block
write protection levels and corresponding status register
control bits are shown in Table 3.
RDSR
WRSR
READ
WRITE
WRITE ENABLE (WREN): The device will power up in
the write disable state when V is applied. All program-
ming instructions must therefore be preceded by a Write
Enable instruction.
CC
The three bits, BP0, BP1, and WPEN are nonvolatile cells
that have the same properties and functions as the regular
memory cells (e.g. WREN, t , RDSR).
WC
WRITE DISABLE (WRDI): To protect the device
against inadvertent writes, the Write Disable instruction
disables all programming modes. The WRDI instruction is
independent of the status of the WP pin.
Table 3. Block Write Protect Bits
Status
Register
Bits
Array Addresses Protected
Level
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
BP1 BP0
AT25128
None
0
0
0
1
1
0
1
0
1
1(1/4)
2(1/2)
3(All)
3000 - 3FFF
2000 - 3FFF
0000 - 3FFF
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is enabled when the WP pin is low and the WPEN bit
is “1.” Hardware write protection is disabled when either
the WP pin is high or the WPEN bit is “0.” When the device
is hardware write protected, writes to the Status Register,
including the Block Protect bits and the WPEN bit, and the
block-protected sections in the memory array are dis-
abled. Writes are only allowed to sections of the memory
which are not block-protected.
Table 2a. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN
X
X
X
BP1
BP0 WEN RDY
NOTE: When the WPEN bit is hardware write protected, it
cannot be changed back to “0,” as long as the WP pin is
held low.
(continued)
7
Functional Description (Continued)
Table 4. WPEN Operation
The READY/BUSY status of the device can be deter-
mined by initiating a READ STATUS REGISTER (RDSR)
Instruction. If Bit 0 = 1, the WRITE cycle is still in progress.
If Bit 0 = 0, the WRITE cycle has ended. Only the READ
STATUS REGISTER instruction is enabled during the
WRITE programming cycle.
Protected Unprotected Status
WPEN WP WEN Blocks
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Register
Protected
Writable
0
0
1
1
X
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
X
The AT25128 is capable of a 32-byte PAGE WRITE op-
eration. After each byte of data is received, the five low
order address bits are internally incremented by one; the
high order bits of the address will remain constant. If more
than 32-bytes of data are transmitted, the address counter
will roll over and the previously written data will be over-
written. The AT25128 is automatically returned to the write
disable state at the completion of a WRITE cycle.
Low
Low
High
High
Protected
Protected
Protected
Writable
READ SEQUENCE (READ): Reading the AT25128 via
the SO (Serial Output) pin requires the following se-
quence. After the CS line is pulled low to select a device,
the READ op-code is transmitted via the SI line followed
by the byte address to be read (A15-A0, Refer to Table 5).
Upon completion, any data on the SI line will be ignored.
The data (D7-D0) at the specified address is then shifted
out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The
READ sequence can be continued since the byte address
is automatically incremented and data will continue to be
shifted out. When the highest address is reached, the ad-
dress counter will roll over to the lowest address allowing
the entire memory to be read in one continuous READ cy-
cle.
NOTE: If the device is not Write enabled (WREN), the de-
vice will ignore the Write instruction and will return to the
standby state, when CS is brought high. A new CS falling
edge is required to re-initiate the serial communication.
Table 5. Address Key
Address
AN
AT25128
A13 - A0
Don’t Care Bits
A15 - A14
WRITE SEQUENCE (WRITE): In order to program the
AT25128, two separate instructions must be executed.
First, the device must be write enabled via the Write En-
able (WREN) Instruction. Then a Write (WRITE) Instruc-
tion may be executed. Also, the address of the memory
location(s) to be programmed must be outside the pro-
tected address field location selected by the Block Write
Protection Level. During an internal write cycle, all com-
mands will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After
the CS line is pulled low to select the device, the WRITE
op-code is transmitted via the SI line followed by the byte
address (A15-A0) and the data (D7-D0) to be pro-
grammed (Refer to Table 5). Programming will start after
the CS pin is brought high. (The LOW to High transition of
the CS pin must occur during the SCK low time immedi-
ately after clocking in the D0 (LSB) data bit.
8
AT25128
AT25128
Timing Diagrams (for SPI Mode 0 (0,0))
Synchronous Data Timing
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
tWL
SCK
VIL
tSU
tH
VIH
VIL
SI
VALID IN
tHO
tDIS
tV
VOH
HI-Z
HI-Z
SO
VOL
WREN Timing
WRDI Timing
9
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
WRSR Timing
READ Timing
10
AT25128
AT25128
WRITE Timing
HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
SO
tHZ
tLZ
11
Ordering Information
t
(max)
I
(max)
I
(max)
f
MAX
WC
CC
SB
Ordering Code
Package
Operation Range
(ms)
(µA)
(µA)
(kHz)
5
5000
3000
3000
2.0
2100
AT25128-10PC
AT25128-10SC
AT25128N1-10SC
AT25640T2-10TC
8P3
14S
16S1
20T
Commercial
(0°C to 70°C)
10
20
0.5
0.2
2100
500
AT25128-10PC-2.7
AT25128-10SC-2.7
AT25128N1-10SC-2.7
AT25128T2-10TC-2.7
8P3
14S
16S1
20T
Commercial
(0°C to 70°C)
AT25128-10PC-1.8
AT25128-10SC-1.8
AT25128N1-10SC-1.8
AT25128T2-10TC-1.8
8P3
14S
16S1
20T
Commercial
(0°C to 70°C)
5
5000
3000
3000
2.0
0.5
0.2
2100
2100
500
AT25128-10PI
AT25128-10SI
AT25128N1-10SI
AT25128T2-10TI
8P3
14S
16S1
20T
Industrial
(-40°C to 85°C)
10
20
AT25128-10PI-2.7
AT25128-10SI-2.7
AT25128N1-10SI-2.7
AT25128T2-10TI-2.7
8P3
14S
16S1
20T
Industrial
(-40°C to 85°C)
AT25128-10PI-1.8
AT25128-10SI-1.8
AT25128N1-10SI-1.8
AT25128T2-10TI-1.8
8P3
14S
16S1
20T
Industrial
(-40°C to 85°C)
Package Type
8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8P3
14S
14-Lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
16-Lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
20-Lead, 0.170" Wide, Thin Super Small Outline Package (TSSOP)
Options
16S1
20T
Blank
-2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 3.6V)
-1.8
12
AT25128
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