AT25020N-10SE-2.7 [ATMEL]
EEPROM, 256X8, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8;
| 型号： | AT25020N-10SE-2.7 |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 256X8, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总19页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• 3.0 MHz Clock Rate (5V)
• 8-byte Page Mode
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade, Extended Temperature and Lead-Free Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TAP Packages
SPI Serial
EEPROMs
1K (128 x 8)
2K (256 x 8)
Description
4K (512 x 8)
The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable
programmable read only memory (EEPROM) organized as 128/256/512 words of 8
bits each. The device is optimized for use in many industrial and commercial applica-
tions where low-power and low voltage operation are essential. The AT25010/020/040
is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead
TAP packages.
AT25010
AT25020
AT25040
The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable instruc-
tions are provided for additional data protection. Hardware data protection is provided
via the WP pin to protect against inadvertent write attempts. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
8-lead PDIP
Pin Configurations
Pin Name Function
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
Chip Select
WP
GND
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
8-lead SOIC
SO
CS
SO
WP
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
GND
VCC
WP
GND
Power Supply
Write Protect
8-lead MAP/TAP
HOLD
Suspends Serial Input
VCC 8
HOLD 7
1 CS
2 SO
3 WP
4 GND
SCK 6
SI 5
Rev. 0606K–SEEPR–01/03
Bottom View
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature................................. -55°C to + 125°C
Storage Temperature .................................... -65°C to + 150°C
Voltage on Any Pin
with Respect to Ground ....................................-1.0V to + 7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
2
AT25010/020/040
0606K–SEEPR–01/03
AT25010/020/040
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +5.5V, TAE = -40°C to +125°C,
CC = +2.7V to +5.5V (unless otherwise noted).
V
Symbol
Parameter
Test Condition
Min
2.7
4.5
Max
5.5
Units
V
VCC1
VCC2
ICC1
Supply Voltage
Supply Voltage
Supply Current
5.5
V
VCC = 5.0V at 1 MHz, SO = Open, Read
3.0
mA
VCC = 5.0V at 2 MHz, SO = Open,
Read, Write
ICC2
Supply Current
6.0
mA
ISB1
ISB2
IIL
Standby Current
Standby Current
Input Leakage
VCC = 2.7V
CS = VCC
CS = VCC
5
10
µA
µA
µA
µA
V
VCC = 5.0V
VIN = 0V to VCC
-0.6
-0.6
3.0
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(2)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
-0.6
VCC x 0.3
VCC + 0.5
0.4
(2)
VIH
VCC x 0.7
V
VOL1
VOH1
VOL2
IOL = 2.0 mA
4.5V ≤ VCC ≤ 5.5V
V
IOH = -1.0 mA
VCC - 0.8
VCC - 0.2
V
I
OL = 0.15 mA
0.2
V
2.7V ≤ VCC ≤ 5.5V
VOH2
IOH = -100 µA
V
Note:
1. This parameter is preliminary and Atmel may change the specifications upon further characterization.
2. VIL min and VIH max are reference only and are not tested.
3
0606K–SEEPR–01/03
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, TAE = -40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
4.5 - 5.5
2.7 - 5.5
0
0
3.0
2.1
fSCK
SCK Clock Frequency
MHz
4.5 - 5.5
2.7 - 5.5
2
2
tRI
Input Rise Time
Input Fall Time
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 - 5.5
2.7 - 5.5
2
2
tFI
4.5 - 5.5
2.7 - 5.5
133
200
tWH
tWL
tCS
tCSS
tCSH
tSU
tH
SCK High Time
SCK Low Time
4.5 - 5.5
2.7 - 5.5
133
200
4.5 - 5.5
2.7 - 5.5
250
250
CS High Time
4.5 - 5.5
2.7 - 5.5
250
250
CS Setup Time
CS Hold Time
4.5 - 5.5
2.7 - 5.5
250
250
4.5 - 5.5
2.7 - 5.5
50
50
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
4.5 - 5.5
2.7 - 5.5
50
100
4.5 - 5.5
2.7 - 5.5
100
100
tHD
tCD
tV
4.5 - 5.5
2.7 - 5.5
200
200
4.5 - 5.5
2.7 - 5.5
0
0
133
200
4.5 - 5.5
2.7 - 5.5
0
0
tHO
tLZ
Output Hold Time
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
4.5 - 5.5
2.7 - 5.5
0
0
100
100
4.5 - 5.5
2.7 - 5.5
100
100
tHZ
4.5 - 5.5
2.7 - 5.5
250
500
tDIS
4.5 - 5.5
2.7 - 5.5
5
10
tWC
Write Cycle Time
ms
Endurance(1)
5.0V, 25°C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
4
AT25010/020/040
0606K–SEEPR–01/03
AT25010/020/040
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25010/020/040
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25010/020/040 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
The op-code also contains address bit A8 in both the READ and WRITE instructions.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25010/020/040, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25010/020/040 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25010/020/040. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low, all write operations are inhibited.
WP going low while CS is still low will interrupt a write to the AT25010/020/040. If the
internal write cycle has already been initiated, WP going low will have no effect on any
write operation.
5
0606K–SEEPR–01/03
SPI Serial Interface
Functional
Description
The AT25010/020/040 is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25010/020/040 utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.
Table 1. Instruction Set for the AT25010/020/040
Instruction Name
WREN
Instruction Format
0000 X110
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRDI
0000 X100
RDSR
0000 X101
WRSR
0000 X001
READ
0000 A011
WRITE
0000 A010
Note:
“A” represents MSB address bit A8.
6
AT25010/020/040
0606K–SEEPR–01/03
AT25010/020/040
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction. The WP pin must be held high during a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 2. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
BP1
BP0
WEN
RDY
Table 3. Read Status Register Bit Definition
Bit
Definition
Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the
write cycle is in progress.
Bit 0 (RDY)
Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates
the device is WRITE ENABLED.
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
See Table 4.
See Table 4.
Bits 4-7 are 0s when device is not in an internal write cycle.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25010/020/040 is divided into four array seg-
ments. Top quarter (1/4), Top half (1/2), or all of the memory segments can be
protected. Any of the data within any selected segment will therefore be READ only. The
block write protection levels and corresponding status register control bits are shown in
Table 4.
The two bits, BP1 and BP0 are nonvolatile cells that have the same properties and func-
tions as the regular memory cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
0
BP1
BP0
AT25010
None
AT25020
None
AT25040
None
0
0
1
1
0
1
0
1
1 (1/4)
2 (1/2)
3 (All)
60-7F
40-7F
00-7F
C0-FF
80-FF
00-FF
180-1FF
100-1FF
000-1FF
7
0606K–SEEPR–01/03
READ SEQUENCE (READ): Reading the AT25010/020/040 via the SO (Serial Output)
pin requires the following sequence. After the CS line is pulled low to select a device,
the READ op-code (including A8) is transmitted via the SI line followed by the byte
address to be read (A7-A0). Upon completion, any data on the SI line will be ignored.
The data (D7-D0) at the specified address is then shifted out onto the SO line. If only
one byte is to be read, the CS line should be driven high after the data comes out. The
READ sequence can be continued since the byte address is automatically incremented
and data will continue to be shifted out. When the highest address is reached, the
address counter will roll over to the lowest address allowing the entire memory to be
read in one continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25010/020/040, the Write
Protect pin (WP) must be held high and two separate instructions must be executed.
First, the device must be write enabled via the Write Enable (WREN) Instruction. Then
a Write (WRITE) Instruction may be executed. Also, the address of the memory loca-
tion(s) to be programmed must be outside the protected address field location selected
by the Block Write Protection Level. During an internal write cycle, all commands will be
ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to
select the device, the WRITE op-code (including A8) is transmitted via the SI line fol-
lowed by the byte address (A7-A0) and the data (D7-D0) to be programmed.
Programming will start after the CS pin is brought high. (The LOW to High transition of
the CS pin must occur during the SCK low time immediately after clocking in the D0
(LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a READ STA-
TUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If
Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction
is enabled during the WRITE programming cycle.
The AT25010/020/040 is capable of an 8-byte PAGE WRITE operation. After each byte
of data is received, the three low order address bits are internally incremented by one;
the six high order bits of the address will remain constant. If more than 8 bytes of data
are transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25010/020/040 is automatically returned to the write disable state at
the completion of a WRITE cycle.
NOTE: If the WP pin is brought low or if the device is not Write enabled (WREN), the
device will ignore the Write instruction and will return to the standby state, when CS is
brought high. A new CS falling edge is required to re-initiate the serial communication.
8
AT25010/020/040
0606K–SEEPR–01/03
AT25010/020/040
Timing Diagrams
Synchronous Data Timing (for mode 0)
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
tWL
SCK
VIL
tSU
VIH
tH
SI
VALID IN
VIL
tHO
tDIS
tV
VOH
VOL
HI-Z
HI-Z
SO
WREN Timing
WRDI Timing
9
0606K–SEEPR–01/03
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
WRSR Timing
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14
15
0
SCK
INSTRUCTION
DATA IN
5
4
3
2
1
SI
HIGH IMPEDANCE
SO
READ Timing
10
AT25010/020/040
0606K–SEEPR–01/03
AT25010/020/040
WRITE Timing
CS
0
1
2
3
4
5
6
7
8
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
INSTRUCTION
8
BYTE ADDRESS
DATA IN
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
9TH BIT OF ADDRESS
HIGH IMPEDANCE
SO
HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
SO
tHZ
tLZ
11
0606K–SEEPR–01/03
AT25010 Ordering Information
Ordering Code
Package
Operation Range
AT25010-10PI-2.7
AT25010N-10SI-2.7
AT25010Y1-10YI-2.7
AT25010Y2-10YI-2.7
8P3
8S1
8Y1
8Y2
Industrial
(-40°C to 85°C)
AT25010N-10SJ-2.7
8S1
Lead-Free/Industrial Temperature
(-40°C to 85°C)
AT25010N-10SE-2.7
8S1
High Grade/Extended Temperature
(-40°C to 125°C)
Note:
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
Package Type
8P3
8S1
8Y1
8Y2
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 4.90 x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 6.40 x 3.00 mm Body, Dual Footprint, Non-leaded, Thin Array Package (TAP)
Options
-2.7
Low Voltage (2.7V to 5.5V)
12
AT25010/020/040
0606K–SEEPR–01/03
AT25010/020/040
AT25020 Ordering Information
Ordering Code
Package
Operation Range
AT25020-10PI-2.7
AT25020N-10SI-2.7
AT25020Y1-10YI-2.7
AT25020Y2-10YI-2.7
8P3
8S1
8Y1
8Y2
Industrial
(-40°C to 85°C)
AT25020N-10SJ-2.7
8S1
Lead-Free/Industrial Temperature
(-40°C to 85°C)
AT25020N-10SE-2.7
8S1
High Grade/Extended Temperature
(-40°C to 125°C)
Note:
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 4.90 x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 6.40 x 3.00 mm Body, Dual Footprint, Non-leaded, Thin Array Package (TAP)
Options
8P3
8S1
8Y1
8Y2
-2.7
Low Voltage (2.7V to 5.5V)
13
0606K–SEEPR–01/03
AT25040 Ordering Information
Ordering Code
Package
Operation Range
AT25040-10PI-2.7
AT25040N-10SI-2.7
AT25040Y1-10YI-2.7
AT25040Y2-10YI-2.7
8P3
8S1
8Y1
8Y2
Industrial
(-40°C to 85°C)
AT25040N-10SJ-2.7
8S1
Lead-Free/Industrial Temperature
(-40°C to 85°C)
AT25040N-10SE-2.7
8S1
High Grade/Extended Temperature
(-40°C to 125°C)
Note:
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
Package Type
8P3
8S1
8Y1
8Y2
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 4.90 x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 6.40 x 3.00 mm Body, Dual Footprint, Non-leaded, Thin Array Package (TAP)
Options
-2.7
Low Voltage (2.7V to 5.5V)
14
AT25010/020/040
0606K–SEEPR–01/03
AT25010/020/040
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
15
0606K–SEEPR–01/03
8S1 – JEDEC SOIC
1
3
2
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.75
0.51
0.25
5.00
4.00
NOM
NOTE
SYMBOL
A
B
C
D
E
e
–
A2
L
–
–
–
–
–
–
–
–
1.27 BSC
E
H
L
–
–
–
–
6.20
1.27
End View
Note:
This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
A
R
Small Outline (JEDEC SOIC)
16
AT25010/020/040
0606K–SEEPR–01/03
AT25010/020/040
8Y1 – MAP
PIN 1 INDEX AREA
A
1
3
4
2
PIN 1 INDEX AREA
E1
D1
D
L
8
6
5
7
b
e
A1
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
MAX
0.90
0.05
5.10
3.20
1.15
1.15
0.35
NOM
–
NOTE
A
A1
D
0.00
4.70
2.80
0.85
0.85
0.25
–
4.90
3.00
1.00
1.00
0.30
0.65 TYP
0.60
E
D1
E1
b
e
L
0.50
0.70
7/25/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
8Y1
B
R
17
0606K–SEEPR–01/03
8Y2 – TAP
PIN 1 INDEX AREA
A
PIN 1 INDEX AREA
D
D1
E1
e
b
L
A1
E
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
MAX
0.90
0.05
6.60
3.20
3.15
1.15
0.30
NOM
–
NOTE
A
A
A1
D
0.00
6.20
2.80
2.85
0.85
0.20
–
6.40
3.00
3.00
1.00
0.25
0.65 TYP
0.40
E
D1
E1
b
e
L
0.30
0.50
7/25/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8Y2, 8-lead (6.40 x 3.00 mm Body) TSSOP Array Package
(TAP) Y2
8Y2
A
R
18
AT25010/020/040
0606K–SEEPR–01/03
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