AT24C512-10TU-1.8 [ATMEL]
Two-wire Serial EEPROM; 两线串行EEPROM
| 型号： | AT24C512-10TU-1.8 |
| 厂家： | 
ATMEL |
| 描述： | Two-wire Serial EEPROM |
| 文件： | 总22页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized 65,536 x 8
• Two-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 128-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
Two-wire Serial
EEPROM
• High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
• Automotive Devices Available
512K (65,536 x 8)
• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead LAP, 8-lead SAP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Die
AT24C512
Description
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s
cascadable feature allows up to four devices to share a common two-wire bus. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The devices are available in space-
saving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead
Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is avail-
able in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
Note: Not recommended for new
design; please refer to
AT24C512B datasheet.
Table 1. Pin Configurations
8-lead PDIP
8-lead TSSOP
Pin Name
A0–A1
SDA
Function
Address Inputs
Serial Data
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
NC
SCL
SDA
NC
SCL
SDA
SCL
Serial Clock Input
Write Protect
No Connect
GND
GND
WP
8-lead SOIC
NC
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
NC
SCL
SDA
GND
8-ball dBGA2
8-lead Leadless Array
8-lead SAP
VCC
WP
8
7
6
5
1
2
3
4
A0
8
7
6
5
1
2
3
4
A0
VCC
WP
VCC
WP
8
7
6
5
1
2
3
4
A0
A1
A1
A1
SCL
SDA
NC
NC
GND
SCL
SDA
SCL
SDA
NC
GND
GND
Bottom View
Bottom View
Bottom View
Rev. 1116O–SEEPR–1/07
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature..................................–55°C to +125°C
Storage Temperature.....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
2
AT24C512
1116O–SEEPR–1/07
AT24C512
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are
hardwired or left not connected for hardware compatibility with other AT24Cxx devices.
When the pins are hardwired, as many as four 512K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Address-
ing section. If the pins are left floating, the A1 and A0 pins will be internally pulled down
to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is
>3 pF, Atmel recommends connecting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected high to VCC, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is
>3 pF, Atmel recommends connecting the pin to GND. Switching WP to VCC prior to a
write operation creates a software write protect function.
Memory Organization AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of
128-bytes each. Random word addressing requires a 16-bit data word address.
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1116O–SEEPR–1/07
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
CC = +1.8V to +5.5V (unless otherwise noted)
V
Symbol
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
3.6
5.5
5.5
2.0
3.0
1.0
3.0
2.0
6.0
Units
V
VCC1
VCC2
VCC3
ICC1
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
V
V
VCC = 5.0V
VCC = 5.0V
VCC = 1.8V
VCC = 3.6V
VCC = 2.7V
VCC = 5.5V
READ at 400 kHz
WRITE at 400 kHz
1.0
2.0
mA
mA
µA
ICC2
Standby Current
(1.8V option)
ISB1
VIN = VCC or VSS
µA
Standby Current
(2.7V option)
ISB2
VIN = VCC or VSS
Standby Current
(5.0V option)
ISB3
ILI
VCC = 4.5 - 5.5V
VIN = VCC or VSS
VOUT = VCC or VSS
VIN = VCC or VSS
6.0
3.0
3.0
µA
µA
µA
Input Leakage Current
0.10
0.05
Output Leakage
Current
ILO
VIL
Input Low Level(1)
Input High Level(1)
Output Low Level
Output Low Level
–0.6
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
VIH
VCC x 0.7
VOL2
VCC = 3.0V
VCC = 1.8V
IOL = 2.1 mA
VOL1
IOL = 0.15 mA
0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
4
AT24C512
1116O–SEEPR–1/07
AT24C512
Table 4. AC Characteristics
Applicable over recommended operating range from TA = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted) Test conditions are listed in Note 2.
1.8 Volt
Max
2.7 Volt
Max
5.0 Volt
Max
Symbol
fSCL
Parameter
Min
Min
Min
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
100
400
1000
tLOW
4.7
4.0
0.1
1.3
1.0
0.4
0.4
tHIGH
tAA
µs
4.5
0.05
0.9
0.05
0.55
µs
Time the bus must be free before a
new transmission can start(1)
tBUF
4.7
1.3
0.5
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
4.0
4.7
0
0.6
0.6
0
0.25
0.25
0
µs
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
µs
µs
200
100
100
ns
1.0
0.3
0.3
µs
tF
300
300
100
ns
tSU.STO
tDH
4.7
0.6
50
0.25
50
µs
ns
100
tWR
20 or 5(3)
10 or 5(3)
10 or 5(3)
ms
Endurance(1) 5.0V, 25°C, Page Mode
100K
100K
100K
Write Cycles
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤50 ns
Input and output timing reference voltages: 0.5VCC
3. The Write Cycle Time of 5 ms only applies to the AT24C512 devices bearing the process letter “A” on the package (the mark
is located in the lower right corner on the top side of the package).
5
1116O–SEEPR–1/07
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C512 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6
AT24C512
1116O–SEEPR–1/07
AT24C512
Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA
ACK
8th BIT
WORDn
(1)
wr
t
START
STOP
CONDITION
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
7
1116O–SEEPR–1/07
Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
8
AT24C512
1116O–SEEPR–1/07
AT24C512
Device Addressing
The 512K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 7 on page 10). The device
address word consists of a mandatory “1”, “0” sequence for the first five most significant
bits as shown. This is common to all two-wire EEPROM devices.
The 512K uses the two device address bits A1, A0 to allow as many as four devices on
the same bus. These bits must compare to their corresponding hardwired input pins.
The A1 and A0 pins use an internal proprietary circuit that biases them to a logic low
condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the device will return to a standby state.
DATA SECURITY: The AT24C512 has a hardware data protection scheme that allows
the user to Write Protect the whole memory when the WP pin is at VCC
.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a “0” and then clock in the first 8-bit data word. Following receipt
of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a
microcontroller, then must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory.
All inputs are disabled during this write cycle and the EEPROM will not respond until the
write is complete (see Figure 8 on page 11).
PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 127
more data words. The EEPROM will respond with a “0” after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (see
Figure 9 on page 11).
The data word address lower 7 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 128 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address roll over during write is from the
last byte of the current page to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The Read/Write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0”, allowing the read or write sequence to continue.
9
1116O–SEEPR–1/07
Read Operations
Read operations are initiated the same way as write operations with the exception that
the Read/Write select bit in the device address word is set to “1”. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by “1”. This
address stays valid between operations as long as the chip power is maintained. The
address roll over during read is from the last byte of the last memory page, to the first
byte of the first page.
Once the device address with the Read/Write select bit set to “1” is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input “0” but does generate a following
stop condition (see Figure 10 on page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the Read/Write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a “0” but does generate a following stop condition (see Figure 11 on page 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will roll over and the sequential
read will continue. The sequential read operation is terminated when the microcontroller
does not respond with a “0” but does generate a following stop condition (see Figure 12
on page 12).
Figure 7. Device Address
10
AT24C512
1116O–SEEPR–1/07
AT24C512
Figure 8. Byte Write
Figure 9. Page Write
Figure 10. Current Address Read
Figure 11. Random Read
11
1116O–SEEPR–1/07
Figure 12. Sequential Read
12
AT24C512
1116O–SEEPR–1/07
AT24C512
Ordering Information(1)
Ordering Code
Package
Operation Range
AT24C512C1-10CU-2.7(2)
AT24C512C1-10CU-1.8(2)
AT24C512-10PU-2.7(2)
AT24C512-10PU-1.8(2)
AT24C512W-10SU-2.7(2)
AT24C512W-10SU-1.8(2)
AT24C512N-10SU-2.7(2)
AT24C512N-10SU-1.8(2)
AT24C512-10TU-2.7(2)
AT24C512-10TU-1.8(2)
AT24C512Y4-10YU-1.8(2)
AT24C512U4-10UU-1.8(2)
8CN1
8CN1
8P3
8P3
8S2
Lead-free/Halogen-free/
Industrial Temperature
8S2
8S1
(–40°C to 85°C)
8S1
8A2
8A2
8Y4
8U4-1
AT24C512-W1.8-11(3)
Die Sale
Industrial Temperature
(–40°C to 85°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics
tables.
2. “U” designates Green package + RoHS compliant.
3. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM marketing.
Package Type
8CN1
8P3
8-lead, 0.300" Wide, Leadless Array Package (LAP)
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8-lead, 0.200” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP)
8-ball, die Ball Grid Array Package (dBGA2)
8S2
8S1
8A2
8Y4
8U4-1
Options
–2.7
–1.8
Low-voltage (2.7V to 5.5V)
Low-voltage (1.8V to 3.6V)
13
1116O–SEEPR–1/07
Packaging Information
8U4-1 — dBGA2
D
A1 BALL PAD CORNER
5.
b
E
A1
A
TOP VIEW
A2
A1 BALL PAD CORNER
2
1
SIDE VIEW
A
B
C
D
e
(e1)
d
(d1)
BOTTOM VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
8 SOLDER BALLS
MIN
MAX
NOM
NOTE
SYMBOL
A
0.81 0.91 1.00
0.15 0.20 0.25
0.40 0.45 0.50
0.25 0.30 0.35
2.47 BSC
A
A
b
1
2
D
E
e
4.07 BSC
0.75 BSC
e1
0.74 REF
d
d1
0.75 BSC
0.80 REF
5. Dimension 'b' is measured at the maximum solder ball diameter.
This drawing is for general information only.
1/5/05
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8U4-1, 8-ball, 2.47 x 4.07 mm Body, 0.75 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
R
PO8U4-1
A
14
AT24C512
1116O–SEEPR–1/07
AT24C512
8CN1 – LAP
Marked Pin1 Indentifier
E
A
D
A1
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
7
2
3
MIN
0.94
0.30
0.36
7.90
4.90
MAX
1.14
0.38
0.46
8.10
5.10
NOM
1.04
NOTE
SYMBOL
A
6
5
A1
b
0.34
b
0.41
1
4
D
8.00
E
5.00
e1
L
e
1.27 BSC
0.60 REF
.0.67
e1
L
Bottom View
0.62
0.92
0.72
1.02
1
1
L1
0.97
Note: 1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
11/8/04
DRAWING NO.
REV.
B
TITLE
1150 E.Cheyenne Mtn Blvd.
Colorado Springs, CO 80906
8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
8CN1
R
Leadless Array Package (LAP)
15
1116O–SEEPR–1/07
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
16
AT24C512
1116O–SEEPR–1/07
AT24C512
8S2 – EIAJ SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0°
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8°
NOM
NOTE
SYMBOL
A1
A
A1
b
5
5
C
D
E1
E
D
2, 3
Side View
L
∅
e
1.27 BSC
4
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
TITLE
REV.
DRAWING NO.
2325 Orchard Parkway
San Jose, CA 95131
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
8S2
C
R
17
1116O–SEEPR–1/07
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
B
C
D
E1
E
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0°
–
–
1.27
∅
8°
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
18
AT24C512
1116O–SEEPR–1/07
AT24C512
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
19
1116O–SEEPR–1/07
8Y4 – SAP
PIN 1 INDEX AREA
A
PIN 1 ID
D
E1
L
A1
E
e
b
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
MAX
0.90
0.05
6.20
5.10
3.15
3.15
0.45
NOM
–
NOTE
A
A1
D
0.00
5.80
4.70
2.85
2.85
0.35
–
6.00
E
4.90
D1
E1
b
3.00
3.00
0.40
e
1.27 TYP
3.81 REF
0.60
e1
L
0.50
0.70
5/24/04
DRAWING NO.
REV.
TITLE
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80817
8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package
(SAP) Y4
8Y4
A
R
20
AT24C512
1116O–SEEPR–1/07
AT24C512
Revision History
Doc. Rev.
Date
Comments
1116O
1/2007
Revision history implemented.
Added Note to Page 1 recommending new device.
21
1116O–SEEPR–1/07
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