AT21CS01-SSHM12-B [ATMEL]
EEPROM, 128X8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, PLASTIC, MS-012AA, SOIC-8;
| 型号： | AT21CS01-SSHM12-B |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 128X8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, PLASTIC, MS-012AA, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总37页 (文件大小：1497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT21CS01
Single-Wire, I/O Powered Serial EEPROM with a
Unique, Factory Programmed 64-bit Serial Number
1-Kbit (128 x 8)
DATASHEET
Features
Low voltage operation
̶
Device is self-powered via 1.7V to 3.6V pull-up voltage on the SI/O line
Internally organized as 128 words of 8 bits each (1-Kbit)
Single-Wire serial interface with I2C protocol structure
̶
Device communication is achieved through a single I/O pin
Standard Speed and High Speed Mode options
̶
̶
15.4kbps maximum bit rate in Standard Speed Mode
125kbps maximum bit rate in High Speed Mode
8-byte Page Write or single Byte Writes allowed
Discovery Response feature for quick detection of devices on the bus
ROM Zone support
̶
Device is segmented into four 256-bit zones, each of which can be
permanently made read-only (ROM)
256-bit Security Register
̶
Lower 8 bytes contains a factory programmed, read-only,
64-bit Serial Number that is unique to all Atmel Single-Wire products
Upper 16 bytes are user-programmable and permanently lockable
̶
Self-timed write cycle (5ms max)
Manufacturer Identification support
̶
Device responds with unique value for Atmel as well as density and revision
information
High reliability
̶
̶
̶
Endurance: 1,000,000 write cycles
Data retention: 100 years
IEC 61000-4-2 Level 4 ESD Compliant (±8kV Contact, ±15kV Air Discharge)
Green (Lead-free/Halide-free/RoHS Compliant) package options
8-lead SOIC, 3-lead SOT23, and 4-ball Thin WLCSP
̶
Die sale options in wafer form and tape and reel
Description
The Atmel® AT21CS01 provides 1,024 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 128 words of 8 bits
each. The device’s software addressing scheme allows up to eight devices to
share a common Single-Wire bus. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage
operation are essential. Some applications examples include analog sensor
calibration data storage, ink and toner printer cartridge identification, and
management of after-market consumables. The device is available in
space-saving package options and operates with an external pull-up voltage from
1.7V to 3.6V on the SI/O line.
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
Table of Contents
1. Pin Descriptions and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Device Block Diagram and System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Device Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
System Configuration using Single-Wire Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Device Operation and Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Single-Wire Bus Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1
Device Reset / Power-up and Discovery Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1.1
3.1.1.2
Resetting The Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device Response Upon Reset or Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.2
3.1.3
Interrupting the Device During an Active Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input and Output Bit Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.3.1
3.1.3.2
3.1.3.3
3.1.3.4
Data Input Bit Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Start / Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Communication Interruptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Output Bit Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Device Addressing and I2C Protocol Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. Available Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
EEPROM Access (Opcode Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Security Register Access (Opcode Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Lock Security Register (Opcode 2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ROM Zone Register Access (Opcode 7h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Freeze ROM Zone State (Opcode 1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Manufacturer ID Read (Opcode Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standard Speed Mode (Opcode Dh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
High Speed Mode (Opcode Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
6.2
6.3
6.4
6.5
Device Behavior During Internal Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Writing to the Security Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Locking the Security Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.5.1
6.5.2
Device Response to a Write Command on a Locked Device . . . . . . . . . . . . . . . . . . . . . . 17
Check Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.6
Setting the Device Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.6.1
6.6.2
Standard Speed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
High Speed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
7. Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1
7.2
7.3
7.4
Current Address Read within the EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Random Read within the EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Sequential Read within the EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Operations in the Security Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4.1
Serial Number Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5
Manufacturer ID Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8. ROM Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1
ROM Zone Size and ROM Zone Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1.1 ROM Zone Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Programming and Reading the ROM Zone Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2
8.2.1
8.2.2
8.2.3
Reading the status of a ROM Zone Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Writing to a ROM Zone Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Freeze ROM Zone Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.3
Device Response to a Write Command Within an Enabled ROM Zone . . . . . . . . . . . . . . . . . . . . . . 26
9. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.1
9.2
9.3
9.4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC and AC Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.4.1
9.4.2
Reset and Discovery Response Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Data Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.5
9.6
EEPROM Cell Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Device Default Condition from Atmel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.1 Ordering Code Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.2 Ordering Code Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11. Part Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12.1 8S1 — 8-lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12.2 3ST1 — 3-lead SOT23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12.3 4U-6 — 4-ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
3
1.
Pin Descriptions and Pinouts
Table 1-1.
Pin Descriptions
Pin
Type
Pin
Symbol
Asserted
State
Pin Name and Functional Description
No Connect: The NC pins are not internally connected. These pins can be
connected to GND or left floating.
NC
—
—
—
Ground: The ground reference for the power supply. GND should be
connected to the system ground.
GND
Power
Serial Input and Output: The SI/O pin is an open-drain, bi-directional
input/output pin used to serially transfer data to and from the device.
The SI/O pin must be pulled-high using an external pull-up resistor (not to
exceed 4K in value) and may be wire-ORed with any number of other open-
drain or open-collector pins from other devices on the same bus.
Power,
SI/O
—
Input/Output
The device also uses the SI/O pin as its voltage source by drawing and
storing power during the periods that the pin is pulled high to a voltage level
between 1.7V and 3.6V.
8-lead SOIC
3-lead SOT23
4-ball WLCSP
SI/O NC
1
2
3
4
8
7
6
5
NC
NC
NC
NC
NC
SI/O
2
NC
3
GND
NC
GND NC
1
SI/O
GND
Top View
Top View
Top View
Note: Package drawings are not to scale.
4
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
2.
Device Block Diagram and System Configuration
2.1
Device Block Diagram
Figure 2-1.
Block Diagram
Device
Configuration
Latches
Device
Power
Extraction
Memory
System Control
Module
SI/O
High Voltage
Generation Circuit
Reset
Detection
EEPROM Array
Command
Control
1 page
Column Decoder
Data Register
Internal
Timing
Generation
Data & ACK
Input/Output Control
DOUT
DIN
GND
2.2
System Configuration using Single-Wire Serial EEPROMs
Figure 2-2.
System Configuration using Single-Wire Serial EEPROMs
VPUP
RPUP
(See Section 9.3 for requirements.)
V
CC
SI/O
Bus Master:
Microcontroller
SI/O
SI/O
SI/O
Slave 1
AT21CS01
Slave 0
AT21CS01
Slave 7
AT21CS01
GND
GND
GND
GND
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
5
3.
Device Operation and Communication
The AT21CS01 operates as a Slave device and utilizes a single wire digital serial interface to communicate with
a host controller, commonly referred to as the Bus Master. The Master controls all Read and Write operations to
the Slave devices on the serial bus. The device has two speeds of operation, Standard Speed Mode and High
Speed Mode.
The device utilizes an 8-bit data structure. Data is transferred to and from the device via the Single-Wire serial
interface using the Serial Input/Output (SI/O) pin. Power to the device is also provided via the SI/O pin, thus only
the SI/O pin and the GND pin are required for device operation. Data sent to the device over the Single-Wire
bus is interpreted by the state of the SI/O pin during specific time intervals or slots. Each time slot is referred to
as a Bit Frame and lasts tBIT in duration. The Master initiates all Bit Frames by driving the SI/O line low. All
commands and data information are transferred with the Most-Significant Bit (MSB) first.
The software sequence sent to the device is an emulation of what would be sent to an I2C Serial EEPROM with
the exception that typical 4-bit Device Type Identifier of 1010b in the Device Address is replaced by a 4-bit
opcode. The device has been architected in this way to allow for rapid deployment and significant reuse of
existing I2C firmware. Please refer to Section 4., “Device Addressing and I2C Protocol Emulation” for more
details about the way the device operates.
During bus communication, one data bit is transmitted in every Bit Frame, and after eight bits (one byte) of data
has been transferred, the receiving device must respond with either an acknowledge (ACK) or a
no-acknowledge (NACK) response bit during a ninth bit window. There are no unused clock cycles during any
Read or Write operation, so there must not be any interruptions or breaks in the data stream during each data
byte transfer and ACK or NACK clock cycle. In the event where an unavoidable system interrupt is required,
please refer to the requirements outlined in Section 3.1.3.3, “Communication Interruptions”.
3.1
Single-Wire Bus Transactions
Data transmitted over the SI/O line can be one of five possible types:
Reset and Discovery Response
Logic 0 or Acknowledge (ACK)
Logic 1 or No Acknowledge (NACK)
Start Condition
Stop Condition
The Reset and Discovery Response is not considered to be part of the data stream to the device, whereas the
remaining four transactions are all required in order to send data to and receive data from the device. The
difference between the different types of data stream transactions is the duration that SI/O is driven low within
the Bit Frame.
3.1.1 Device Reset / Power-up and Discovery Response
3.1.1.1 Resetting The Device
A Reset and Discovery Response sequence is used by the Master to reset the device as well as to perform a
general bus call to determine if any devices are present on the bus.
To begin the Reset portion of the sequence, the Master must drive SI/O low for a minimum time. If the device is
not currently busy with other operations, the Master can drive SI/O low for a time of tRESET. The length of tRESET
differs for Standard Speed Mode and for High Speed Mode. However, if the device is busy, the Master must
drive SI/O for a longer time of tDSCHG to ensure the device is reset as discussed in Section 3.1.2. The reset time
forces any internal charge storage within the device to be consumed, causing the device to lose all remaining
standby power available internally.
Upon SI/O being released for a sufficient amount of time to allow the device time to power up and initialize, the
Master must then always request a Discovery Response Acknowledge from the AT21CS01 prior to any
commands being sent to the device. The Master can then determine if an AT21CS01 is present by sampling for
the Discovery Response Acknowledge from the device.
6
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
3.1.1.2 Device Response Upon Reset or Power-Up
After the device has been powered up or after the Master has reset the device by holding the SI/O line low for
tRESET or tDSCHG, the Master must then release the line which will be pulled high by an external pull-up resistor.
The Master must then wait an additional minimum time of tRRT before the Master can request a Discovery
Response Acknowledge from the device.
The Discovery Response Acknowledge sequence begins by the Master driving the SI/O line low which will start
the AT21CS01’s internal timing circuits. The Master must continue to drive the line low for tDRR
.
During the tDRR time, the AT21CS01 will respond by concurrently driving SI/O low. The device will continue to
drive SI/O low for a total time of tDACK. The Master should sample the state of the SI/O line at tMSDR past the
initiation of tDRR. By definition, the tDACK minimum is longer than the tMSDR maximum time, thereby ensuring the
Master can always correctly sample the SI/O for a level less than VIL. After the tDACK time has elapsed, the
AT21CS01 will release SI/O which will then be pulled high by the external pull-up resistor.
The Master must then wait tHTSS to creates a Start condition before continuing with the first command (see
Section 3.1.3.2 for more details about Start conditions). By default, the device will come out of reset in High
Speed Mode. Changing the device to Standard Speed Mode is covered in Section 5.7 on page 13. The
AT21CS01 will power up with its internal address pointer set to zero.
The timing requirements for the Reset and Discovery Response sequence for both Standard Speed and High
Speed Mode can be found in Section 9.4, “AC Characteristics” on page 28.
3.1.2 Interrupting the Device During an Active Operation
To conserve the stored energy within the onboard parasitic power system and minimize overall active current,
the AT21CS01 will not monitor the SI/O line for new commands while its busy executing a previously sent
command. As a result, the device is not able to sense how long SI/O has been in a given state. If the Master
requires to interrupt the device during an active operation, it must drive SI/O low long enough to deplete all of its
remaining stored power. This time is defined as tDSCHG, after which a normal Discovery Response can begin by
releasing the SI/O line.
Figure 3-1.
Reset and Discovery Response Waveform
MASTER
AT21CS01
PULL-UP RESISTOR
tHTSS
tPUP
V
IH
Master
Sampling
Window
Begin Next
Command with
Start Condition
tDRR
SI/O
V
IL
tRRT
tMSDR
tDACK
tRESET / tDSCHG
3.1.3 Data Input and Output Bit Frames
Communication with the AT21CS01 is conducted in time intervals referred to as a Bit Frame and last tBIT in
duration. Each Bit Frame contains a single binary data value. Input Bit Frames are used to transmit data from the
Master to the AT21CS01 and can either be a Logic 0 or a Logic 1. An output Bit Frame carries data from the
AT21CS01 to the Master. In all input and output cases, the Master initiates the Bit Frame by driving the SI/O line
low. Once the AT21CS01 detects the SI/O being driven below the VIL level, its internal timing circuits begin to run.
AT21CS01 [DATASHEET]
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7
The duration of each Bit Frame is allowed to vary from bit to bit as long as the variation does not cause the tBIT
length to exceed the specified minimum and maximum values (see Section 9.4 on page 28). The tBIT
requirements will vary depending on whether the device is set for Low Speed or High Speed Mode. For more
information about setting the speed of the device, refer to Section 6.6, “Setting the Device Speed” on page 18.
3.1.3.1 Data Input Bit Frames
A data input Bit Frame can be used by the Master to transmit either a Logic 0 or Logic 1 data bit to the
AT21CS01. The input Bit Frame is initiated when the Master drives the SI/O line low. The length of time that the
SI/O line is held low will dictate whether the Master is transmitting a Logic 0 or a Logic 1 for that Bit Frame. For
a Logic 0 input, the length of time that the SI/O line must be held low is defined as tLOW0. Similarly, for a Logic 1
input, the length of time that the SI/O line must be held low is defined as tLOW1
.
The AT21CS01 will sample the state of the SI/O line after the maximum tLOW1 but prior to the minimum tLOW0
after SI/O was driven below the VIL threshold to determine if the data input is a Logic 0 or a Logic 1. If the Master
is still driving the line low at the sample time, the AT21CS01 will decode that Bit Frame as a Logic 0 as SI/O will
be at a voltage less than VIL. If the Master has already released the SI/O line, the AT21CS01 will see a voltage
level greater than or equal to VIH because of the external pull-up resistor, and that Bit Frame will be decoded as
a Logic 1. The timing requirements for these parameters can be found in Section 9.4, “AC Characteristics” on
page 28.
A Logic 0 condition has multiple uses in the I2C emulation sequences. It is used to signify a ‘0’data bit, and it
also is used for an Acknowledge (ACK) response. Additionally, a Logic 1 condition is also is used for a No
Acknowledge (NACK) response in addition to the nominal ‘1‘ data bit.
Below, Figure 3-2 and Figure 3-3 depict the Logic 0 and Logic 1 input Bit Frames.
Figure 3-2.
Logic 0 Input Condition Waveform
MASTER
PULL-UP RESISTOR
VIH
SI/O
VIL
t
t
RCV
LOW0
t
BIT
Figure 3-3.
Logic 1 Input Condition Waveform
MASTER
PULL-UP RESISTOR
VIH
SI/O
VIL
tLOW1
tBIT
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3.1.3.2 Start / Stop Condition
All transactions to the AT21CS01 begin with a Start condition; therefore, a Start can only be transmitted by the
Master to the Slave. Likewise, all transactions are terminated with a Stop condition and thus a Stop condition
can only be transmitted by the Master to the Slave.
The Start and Stop conditions require identical biasing of the SI/O line. The Start/Stop condition is created by
holding the SI/O line at a voltage of VPUP for a duration of tHTSS. Refer to Section 9.4 for timing minimums and
maximums.
Figures Figure 3-4 and Figure 3-5 depict the Start and Stop Conditions.
Figure 3-4.
Start Condition Waveform
MASTER
PULL-UP RESISTOR
VIH
SI/O
VIL
t
HTSS
Figure 3-5.
Stop Condition Waveform
MASTER
PULL-UP RESISTOR
VIH
Previous
Bit Frame
t
RCV
SI/O
VIL
t
HTSS
3.1.3.3 Communication Interruptions
In the event that a protocol sequence is interrupted midstream, this sequence can be resumed at the point of
interruption if the elapsed time of inactivity (where SI/O is idle) is less that the maximum tBIT time. The maximum
allowed value will differ if the device is High Speed Mode or Low Speed Mode (see Section 6.6).
Caution:
The interruption of protocol must not occur during a write sequence immediately after a Logic 0 “ACK”
response when sending data to be written to the device. In this case, the interruption will be interpreted
as a Stop condition and will cause an internal write cycle to begin. The device will be busy for tWR time
and will not respond to any commands.
For systems that cannot accurately monitor the location of interrupts, it is recommended to ensure
that a minimum interruption time be observed consistent with the longest busy operation of the
device (tWR). Communicating with the device while it is in an internal write cycle by the Master
driving SI/O low could cause the byte(s) being written to become corrupted and must be avoided.
The behavior of the device during a write cycle is described in more detail in Section 6.1.
If the sequence is interrupted for longer than the maximum tBIT, the Master must wait at least the minimum tHTSS
before continuing. By waiting the minimum tHTSS time, a new Start condition is created and the device is ready to
receive a new command. It is recommended that the Master start over and repeat the transaction that was
interrupted midstream.
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9
3.1.3.4 Data Output Bit Frame
A data output Bit Frame is used when the Master is to receive communication back from the AT21CS01. Data
output Bit Frames are used when reading any data out as well as any ACK or NACK responses from the device.
Just as in the input Bit Frame, the Master initiates the sequence by driving the SI/O line below the VIL threshold
which engages the AT21CS01’s internal timing generation circuit.
Within the output Bit Frame is the critical timing parameter tRD, which is defined as the amount of time the
Master must continue to drive the SI/O line low after crossing the below VIL threshold to request a data bit back
from the AT21CS01. Once the tRD duration has expired, the Master must release the SI/O line.
If the AT21CS01 is responding with a Logic 0 (for either a ‘0’ data bit or an ACK response), it will begin to pull
the SI/O line low concurrently during the tRD window and continue to hold it low for a duration of tHLD0, after
which it will release the line to be pulled back up to VPUP (see Figure 3-6). Thus, when the Master samples SI/O
within the tMRS window, it will see a voltage less than VIL and decode this event as a Logic 0. By definition, the
tHLD0 time is longer than the tMRS time and therefore the Master is guaranteed to sample while the AT21CS01 is
still driving the SI/O line low.
Figure 3-6.
Logic 0 Data Output Bit Frame Waveform
MASTER
AT21CS01
PULL-UP RESISTOR
t
PUP
VIH
VIL
Master
Sampling
Window
t
RCV
SI/O
t
RD
t
MRS
t
HLD0
t
BIT
If the AT21CS01 intends to respond with a Logic 1 (for either a ‘1’ data bit or a NACK response), it will not drive
the SI/O line low at all. Once the Master releases the SI/O line after the maximum tRD has elapsed, the line will
be pulled up to VPUP. Thus when the Master samples the SI/O line within the tMRS window, it will detect a voltage
greater than VIH and decode this event as a Logic 1.
The data output Bit Frame is shown in greater detail below in Figure 3-7.
Figure 3-7.
Logic 1 Data Output Bit Frame Waveform
MASTER
AT21CS01
PULL-UP RESISTOR
t
PUP
VIH
VIL
Master
Sampling
Window
SI/O
t
RD
t
MRS
t
BIT
Note: AT21CS01 will not drive the SI/O line during a Logic 1 output Bit Frame.
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4.
Device Addressing and I2C Protocol Emulation
Accessing the device requires a Start condition followed by an 8-bit Device Address word. The AT21CS01
protocol sequence emulates what would be required for an I2C Serial EEPROM, with the exception that the
beginning four bits of the device address are used as an opcode for the different commands and actions that the
device can perform.
Since multiple Slave devices can reside on the bus, each Slave device must have its own unique address so
that the Master can access each device independently. After the 4-bit opcode, the following three bits of the
Device Address Byte are comprised of the slave address bits. The three slave address bits are pre-programmed
by Atmel prior to shipment and are read-only. Obtaining devices with different slave address bit values is done
by a purchasing a specific ordering code. Please refer to Section 10., “Ordering Information” on page 30 for
explanation of which ordering code corresponds with a specific slave address value.
Following the three slave address bits is a Read/Write select bit where a Logic 1 indicates a Read and a Logic 0
indicates a Write. Upon the successful comparison of the Device Address, the EEPROM will return an ACK
(Logic 0). If the 4-bit opcode is invalid or the three bits of slave address do not match what is preprogrammed in
the device, the device will not respond on the SI/O line and will return to a standby state.
Table 4-1.
Device Address Byte
4-bit Opcode
Pre-programmed Slave Address Bits
Read/Write
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Refer to Section 5.
A2
A1
A0
R/
W
Following the Device Address Byte, a Memory Address Byte must be transmitted to the device immediately. The
Memory Address Byte contains a 7-bit memory array address to specify which location in the EEPROM to start
reading or writing. Please refer to Table 4-2 to review these bit positions.
Table 4-2.
Memory Address Byte
Bit 7
Bit 6
Bit 5
A5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Don’t Care
A6
A4
A3
A2
A1
A0
4.1
Memory Organization
The AT21CS01 internal memory array is partitioned into two regions. The main 1-Kbit EEPROM is organized as
16 pages of 8 bytes each. The Security Register is 256 bits in length, organized as four pages of 8 bytes each.
The lower two pages of the Security Register are read-only and have a factory programmed, 64-bit Serial
Number that is unique across all Atmel AT21CS series Serial EEPROMs. The upper two pages of the Security
Register are user-programmable and can be subsequently locked (see Section 6.5).
Figure 4-1.
Memory Architecture Diagram
1-Kbit Address Range (00h-7Fh)
Zone 0
Main
1-Kbit
Four, 256-bit
ROM Zones
Zone 1
Zone 2
Zone 3
EEPROM
Each can be
independently
set to read-only
Opcode
1010b(Ah)
256-bit
64-bit Serial Number
Read-Only
Security
Address Range (00h-07h)
Register
Permanently Lockable
by Software
User-Programmable Memory
Opcode
Address Range (10h-1Fh)
1011b(Bh)
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11
5.
Available Opcodes
Table 5-1 outlines available opcodes for the AT21CS01.
Table 5-1.
Command
Opcodes used by the AT21CS01
4-bit Opcode
Brief Description of Functionality
EEPROM Access
1010(Ah)
1011(Bh)
0010(2h)
0111(7h)
0001(1h)
1100(Ch)
1101(Dh)
1110(Eh)
Read/Write the contents of the main memory array.
Read/Write the contents of the Security Register.
Permanently lock the contents of the Security Register.
Inhibit further modification to a zone of the EEPROM array.
Permanently lock the current state of the ROM Zone Registers.
Query manufacturer and density of device.
Security Register Access
Lock Security Register
ROM Zone Register Access
Freeze ROM Zone State
Manufacturer ID Read
Standard Speed Mode
High Speed Mode
Switch to standard speed mode operation.
Switch to high speed mode operation (power-on default).
5.1
5.2
EEPROM Access (Opcode Ah)
The opcode Ah is used to read data from and write data to the EEPROM. Please refer to See Section 7., “Read
Operations” on page 19 for more details about reading data from the device. For details about writing to the
EEPROM, please refer to Section 6., “Write Operations” on page 14.
Security Register Access (Opcode Bh)
The opcode Bh is used to read data from and write data to the Security Register. Please refer to Section 7.4,
“Read Operations in the Security Register” on page 21 for more details about reading data from the Security
Register. For details about writing to the user-programmable portion of the Security Register, please refer to
section Section 6.4, “Writing to the Security Register” on page 16.
5.3
5.4
Lock Security Register (Opcode 2h)
The opcode 2h is used to permanently lock the user-programmable portion of the Security Register. Please
refer to Section 6.5, “Locking the Security Register” on page 17.
ROM Zone Register Access (Opcode 7h)
The AT21CS01 is partitioned into four, 256-bit zones, each of which can be independently and permanently
made read-only (ROM). The state of each zone is stored in a configuration register which can be read from or
written to using the opcode 7h. The ROM Zone functionality is explained in greater detail in Section 8., “ROM
Zones” on page 23.
5.5
Freeze ROM Zone State (Opcode 1h)
The opcode 1h is used to permanently freeze the current state of the ROM Zone Registers. Once set, the ROM
Zone Registers are read-only; therefore, any zone that is not already read-only cannot be subsequently
converted to ROM. Please refer to Section 8.2.3, “Freeze ROM Zone Registers” on page 25 for additional
details.
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5.6
5.7
5.8
Manufacturer ID Read (Opcode Ch)
Manufacturer identification, device density, and device revision information can be read from the device using
the opcode Ch. The full details of the format of the data returned by this command are found in Section 7.5,
“Manufacturer ID Read” on page 22.
Standard Speed Mode (Opcode Dh)
The AT21CS01 can be set to Standard Speed Mode or checked to see whether or not it is in Standard Speed
Mode with the use of the Dh opcode. Further details are covered in Section 6.6.1, “Standard Speed Mode” on
page 18.
High Speed Mode (Opcode Eh)
The AT21CS01 can be set to High Speed Mode or checked to see whether or not it is in High Speed Mode with
the use of the Eh opcode. Further details are covered in Section 6.6.2, “High Speed Mode” on page 18.
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6.
Write Operations
All Write operations for the AT21CS01 begin with the Master sending a Start condition, followed by a Device
Address Byte (opcode Ah for the EEPROM and opcode Bh for the Security Register) with the R/W bit set to ‘0’
followed by the Memory Address Byte. Next, the data value(s) to be written to the device are sent. Data values
must be sent in eight bit increments to the device followed by a Stop condition. If a Stop condition is sent
somewhere other than at the byte boundary, the current write operation will be aborted.
The AT21CS01 allows single Byte Writes, partial Page Writes, and full Page Writes.
6.1
6.2
Device Behavior During Internal Write Cycle
To ensure that the address and data sent to the device for writing are not corrupted while any type of internal
write operation is in progress, commands sent to the device are blocked from being recognized until the internal
operation is completed. If a write interruption occurs (SI/O pulsed low) and is small enough to not deplete the
internal power storage, the device will NACK signaling that the operation is in progress. If an interruption is
longer than tDSCHG then internal write operation will be terminated and may result in data corruption.
Byte Write
The AT21CS01 supports writing of a single 8-bit byte and requires a 7-bit Memory Word address to select which
byte to write.
Upon receipt of the proper Device Address Byte (with opcode of Ah) and Memory Address Byte, the EEPROM
will send a Logic 0 to signify an ACK. The device will then be ready to receive the data byte. Following receipt of
the complete 8-bit data byte, the EEPROM will respond with an ACK. A Stop condition must then occur;
however, since a Stop condition is defined as a null Bit Frame with SI/O pulled high, the Master does not need to
drive the SI/O line to accomplish this. If a Stop condition is sent at any other time, the Write operation is aborted.
After the Stop condition is complete, the EEPROM will enter an internally self-timed write cycle, which will
complete within a time of tWR, while the data is being programmed into the nonvolatile EEPROM. The SI/O pin
must be pulled high via the external pull-up resistor during the entire tWR cycle. After the maximum tWR time has
elapsed, the Master may begin a new bus transaction.
Warning: Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the byte
being programmed to be corrupted. Other memory locations within the memory array will not be
affected. Note Section 6.1 for the behavior of the device while the write cycle is in progress. If the
Master must interrupt a write operation, the SI/O line must be driven low for tDSCHG as noted in
Section 3.1.2.
Figure 6-1.
Byte Write
Stop Condition
by Master
Device Address
Memory Address
Data In Byte
1
MSB
0
1
0
A2 A1 A0
0
0
x
A6 A5 A4 A3 A2 A1 A0
0
D
D
D
D
D
D
D
D
0
SI/O
MSB
MSB
Start Condition
by Master
ACK
by Slave
ACK
by Slave
`ACK
by Slave
Note:
x = Don’t care bit in the place of A7 as this bit falls outside the 1-Kbit addressable range.
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6.3
Page Write
A Page Write operation allows up to eight bytes to be written in the same write cycle, provided all bytes are in
the same row (address bits A6 through A3 are the same) of the memory array. Partial Page Writes of less than
eight bytes are allowed.
A Page Write is initiated the same way as a Byte Write, but the Bus Master does not send a Stop condition after
the first data byte is clocked in. Instead, after the EEPROM acknowledges receipt of the first data byte, the Bus
Master can transmit up to an additional seven data bytes. The EEPROM will respond with an ACK after each
data byte is received. Once all data bytes have been sent, the device requires a Stop condition to begin the
write cycle. However, since a Stop condition is defined as a null Bit Frame with SI/O pulled high, the Master
does not need to drive the SI/O line to accomplish this. If a Stop condition is sent at any other time, the Write
operation is aborted. After the Stop condition is complete, the internally self-timed write cycle will begin.The SI/O
pin must be pulled high via the external pull-up resistor during the entire tWR cycle. Thus, in a multi-slave
environment, communication to other Single-Wire devices on the bus should not be attempted while any
devices are in an internal write cycle.
The lower three bits of the memory address are internally incremented following the receipt of each data byte.
The higher order address bits are not incremented, and the device retains the memory page location. Page
Write operations are limited to writing bytes within a single physical page, regardless of the number of bytes
actually being written. When the incremented word address reaches the page boundary, the address counter
will “roll over” to the beginning of the same page. Nevertheless, creating a roll over event should be avoided as
previously loaded data in the page could become unintentionally altered.After the maximum tWR time has
elapsed, the Master may begin a new bus transaction.
Warning: Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the byte
being programmed to be corrupted. Other memory locations within the memory array will not be
affected. Note Section 6.1 for the behavior of the device while the write cycle is in progress. If the
Master must interrupt a write operation, the SI/O line must be driven low for tDSCHG as noted in
Section 3.1.2.
Figure 6-2.
Page Write
Stop Condition
by Master
Device Address
Memory Address
Data In Byte (1)
Data In Byte (8)
1
MSB
0
1
0
A2 A1 A0
0
0
x
A6 A5 A4 A3 A2 A1 A0
0
D
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
D
0
SI/O
MSB
MSB
Start Condition
by Master
ACK
by Slave
ACK
by Slave
ACK
by Slave
ACK
by Slave
Note:
x = Don’t care bit in the place of A7 as this bit falls outside the 1-Kbit addressable range.
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6.4
Writing to the Security Register
The Security Register supports Bytes Writes, Page Writes, and Partial Page Writes in the upper 16 bytes (upper
two pages of eight bytes each) of the region. Page Writes and Partial Page Writes in the Security Register have
the same page boundary restrictions and behavior requirements as they do in the EEPROM.
Upon receipt of the proper Device Address Byte (with opcode of Bh specified) and Memory Address Byte, the
EEPROM will send a Logic 0 to signify an ACK. The device will then be ready to receive the first data byte.
Following receipt of the data byte, the EEPROM will respond with an ACK and the Master can send up to an
additional seven bytes if desired. The EEPROM will respond with an ACK after each data byte is successfully
received. Once all of the data bytes have been sent, the device requires a Stop condition to begin the write
cycle. However, since a Stop condition is defined as a null Bit Frame with SI/O pulled high, the Master does not
need to drive the SI/O line to accomplish this. After the Stop condition is complete, the EEPROM will enter an
internally self-timed write cycle, which will complete within a time of tWR, while the data is being programmed into
the nonvolatile EEPROM. The SI/O pin must be pulled high via the external pull-up resistor during the entire tWR
cycle. Figure 6-3 is included below as an example of a Byte Write operation in the Security Register.
Figure 6-3.
Byte Write in the Security Register
Stop Condition
by Master
Device Address
A2 A1 A0
Security Register Address
Data In Byte
1
MSB
0
1
1
0
0
x
x
x
1
A3 A2 A1 A0
0
D
D
D
D
D
D
D
D
0
SI/O
MSB
MSB
Start Condition
by Master
ACK
by Slave
ACK
by Slave
ACK
by Slave
Note:
x = Don’t care values in the place of A7 - A5 as these bits falls outside the addressable range of the Security
Register.
Warning: Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the byte
being programmed to be corrupted. Other memory locations within the memory array will not be
affected. Note Section 6.1 for the behavior of the device while the write cycle is in progress. If the
Master must interrupt a write operation, the SI/O line must be driven low for tDSCHG as noted in
Section 3.1.2.
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6.5
Locking the Security Register
The Lock command is an irreversible sequence that will permanently prevent all future writing to the upper 16
bytes of the Security Register on the AT21CS01. Once the Lock command has been executed, the entire
32 byte Security Register becomes read-only. Once the Security Register has been locked, it is not possible to
unlock it.
The Lock command protocol emulates a Byte Write operation to the Security Register, however, the opcode
0010b(2h) is required along with the A7 through A4 bits of the Memory Address being set to 0110b(6h). The
remaining bits of the Memory Address, as well as the Data Byte are don’t care bits. Even though these bits are
don’t cares, they still must be transmitted to the device. An ACK response to the Memory Address and Data
Byte indicates the Security Register is not currently locked. A NACK response indicates the Security Register is
already locked. Please refer to Section 6.5.2 for details about determining the Lock status of the Security
Register.
The sequence completes with a Stop condition to initiate a self-timed internal write cycle. If a Stop condition is
sent at any other time, the Lock operation is aborted. Since a Stop condition is defined as a null Bit Frame with
SI/O pulled high, the Master does not need to drive the SI/O line to accomplish this. Upon completion of the
write cycle, (taking a time of tWR), the Lock operation is complete and the Security Register will become
permanently read-only.
Warning: Any attempt to drive the SI/O line low during the tWR time period may cause the Lock operation to
not complete successfully, and must be avoided.
Figure 6-4.
Lock Command
Stop Condition
by Master
Device Address
Lock Security Register Address
Data In Byte
0
MSB
0
1
0
A2 A1 A0
0
0
0
1
1
0
X
X
X
X
0
X
X
X
X
X
X
X
X
0
SI/O
MSB
MSB
Start Condition
by Master
ACK
by Slave
ACK
by Slave
ACK
by Slave
6.5.1 Device Response to a Write Command on a Locked Device
A locked device will respond differently to a write command to the Security Register compared to a device that
has not been locked. Writing to the Security Register is accomplished by sending a Start condition followed by a
Device Address Byte with the opcode of 1011b(Bh), the appropriate slave address combination, and the
Read/Write bit set as a Logic 0. Both a locked device and a device that has not been locked will return an ACK.
Next the 8-bit Word Address is sent and again, both devices will return an ACK. However, upon sending the
Data Input byte, a device that has already been locked will return a NACK and be immediately ready to accept a
new command, whereas a device that has not been locked will return an ACK to the Data Input byte as per
normal operation for a write command as described in Section 6. on page 14.
6.5.2 Check Lock Command
The Check Lock command follows the same sequence as the Lock command (including 0110bin the A7
through A4 bits of the Memory Address Byte) with the exception that only the Device Address Byte and Memory
Address Byte need to be transmitted to the device. An ACK response to the Memory Address Byte indicates
that the Lock has not been set while a NACK response indicates that the Lock has been set. If the Lock has
already been enabled, it cannot be reversed. The Check Lock command is completed by the Master sending a
Stop bit to the device (defined as a null Bit Frame).
Figure 6-5.
Check Lock Command
Stop Condition
by Master
Device Address
A2 A1 A0
Lock Security Register Address
0
MSB
0
1
0
0
0
0
1
1
0
X
X
X
X
SI/O
MSB
Start Condition
by Master
ACK
by Slave
ACK by Slave
if Unlocked
NACK by Slave
if Locked
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6.6
Setting the Device Speed
The AT21CS01 can be set to Standard Speed Mode (15.4kbps max) or High Speed Mode (125kbps max)
through a software sequence. Upon executing a Reset and Discovery Response sequence (see Section 3.1.1
on page 6), the device will default to High Speed Mode.
6.6.1 Standard Speed Mode
The device can be set to Standard Speed Mode or checked to see whether or not it is in Standard Speed Mode
with the use of the Dh opcode. This transaction only requires eight bits.
To set the device to Standard Speed Mode, the Master must send a Start condition, followed by the Device
Address Byte with the opcode of 1101b(Dh) specified, along with the appropriate slave address combination
and the Read/Write bit set to a Logic 0. The device will return an ACK (Logic 0) and will be immediately ready to
receive commands for Standard Speed Operation.
To determine if the device is already set to Standard Speed Mode, the Device Address Byte with the opcode of
1101b(Dh) must be sent to the device, along with the appropriate slave address combination and the
Read/Write bit set to a Logic 1. The device will return an ACK (Logic 0) if it was set for Standard Speed Mode. It
will return a NACK (Logic 1) if the device was not currently set for Standard Speed Mode.
6.6.2 High Speed Mode
The device can be set to High Speed Mode or checked to see whether or not it is in High Speed Mode with the
use of the Eh opcode. This transaction only requires eight bits. The power-on default for the device is High
Speed Mode.
To set the device to High Speed Mode, the Master must send a Start condition, followed by the Device Address
Byte with the opcode of 1110b(Eh) specified, along the appropriate slave address combination and the
Read/Write bit set to a Logic 0. The device will return an ACK (Logic 0) and will be immediately ready to receive
commands for High Speed Operation.
To determine if the device is already set to High Speed Mode, the Device Address Byte with the opcode of
1110b(Eh) specified, must be sent to the device, along with the appropriate slave address combination and the
Read/Write bit set to a Logic 1. The device will return an ACK (Logic 0) if it was set for High Speed Mode. It will
return a NACK (Logic 1) if the device was not currently set for High Speed Mode.
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7.
Read Operations
Read operations are initiated in a similar way as Write operations with the exception that the Read/Write select
bit in the Device Address Byte must be set to a Logic 1. There are multiple Read operations supported by the
device:
Current Address Read within the EEPROM
Random Read within the EEPROM
Sequential Read within the EEPROM
Read from the Security Register
Manufacturer ID Read
Warning: The AT21CS01 contains a single, shared memory address pointer that maintains the address of the
next byte in the EEPROM or Security Register to be accessed. For example, if the last byte read or
written was memory location 0Dh of the EEPROM, then the address pointer will be pointing to
memory location 0Eh of the EEPROM. As such, when changing from a Read in one region to the
other, the first read operation in the new region should begin with a Random Read instead of a
Current Address Read to ensure the address pointer is set to a known value within the desired
region.
If the end of the EEPROM or the Security Register is reached, then the address pointer will “roll over” back to
the beginning (address 00h) of that region. The address pointer retains its value between operations as long as
the pull-up voltage on the SI/O pin is maintained or as long as the device has not been reset. If the device has
been power cycled or reset, then the internal address pointer will default to 00h.
7.1
Current Address Read within the EEPROM
The internal address pointer must be pointing to a memory location within the EEPROM in order to perform a
Current Address Read from the EEPROM. To initiate the operation, the Master must send a Start condition,
followed by the Device Address Byte with the opcode of 1010b(Ah) specified, along with the appropriate slave
address combination and the Read/Write bit set to a Logic 1. After the Device Address Byte has been sent, the
AT21CS01 will return an ACK (Logic 0).
Following the ACK, the device is ready to output one byte (eight bits) of data. The Master initiates the all bits of
data by driving the SI/O line low to start. The AT21CS01 will hold the line low after the Master releases it to
indicate a Logic 0. If the data is Logic 1, the AT21CS01 will not hold the SI/O line low at all, causing it to be
pulled high by the pull-up resistor once the Master releases it. This sequence repeats for eight bits.
After the Master has read the first data byte and no further data is desired, the Master must return a NACK
(Logic 1) response to end the Read operation and return the device to the standby mode. Figure 7-1 depicts this
sequence.
If the Master would like the subsequent byte, it would return an ACK (Logic 0) and the device will be ready
output the next byte in the memory array. Please refer to Section 7.3, “Sequential Read within the EEPROM” for
details about continuing to read beyond one byte.
Warning: If the last operation to the device was an access to the Security Register, then a Random Read
should be performed to ensure that the address pointer is set to a known memory location within
the EEPROM.
Figure 7-1.
Current Address Read
Stop Condition
by Master
Device Address
Data Out Byte (n)
1
MSB
0
1
0
A2 A1 A0
1
0
D
D
D
D
D
D
D
D
1
SI/O
MSB
Start Condition
by Master
ACK
by Slave
NACK
by Master
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
19
7.2
Random Read within the EEPROM
A Random Read begins in the same way as a Byte Write operation which will load a new EEPROM memory
address into the address pointer. However, instead of sending the Data byte and Stop condition of the Byte
Write, a repeated Start condition is sent to the device. This sequence is referred to as a “dummy write”. After the
Device Address and Memory Address Bytes of the “dummy write” have been sent, the AT21CS01 will return an
ACK response. The Master can then initiate a Current Address Read, beginning with a new Start condition, to
read data from the EEPROM. Please refer to Section 7.1 for details on how to perform a Current Address Read.
Figure 7-2.
Random Read
Stop Condition
by Master
Device Address
Memory Address
Device Address
A2 A1 A0
Data Out Byte (n)
1
MSB
0
1
0
A2 A1 A0
0
0
x
A6 A5 A4 A3 A2 A1 A0
0
1
0
1
0
1
0
D
D
D
D
D
D
D
D
1
SI/O
MSB
MSB
MSB
Start Condition
by Master
ACK
by Slave
Restart
by Master
ACK
by Slave
ACK
by Slave
NACK
by Master
Dummy Write
7.3
Sequential Read within the EEPROM
Sequential Reads start as either a Current Address Read or as a Random Read. However, instead of the
Master sending a NACK (Logic 1) response to end a Read operation after a single byte of data has been read,
the Master sends an ACK (Logic 0) to instruct the AT21CS01 to output another byte of data. As long as the
device receives an ACK from the Master after each byte of data has been output, it will continue to increment
the address counter and output the next byte data from the EEPROM. If the end of the EEPROM is reached,
then the address pointer will “roll over” back to the beginning (address 00h) of the EEPROM region. To end the
Sequential Read operation, the Master must send a NACK response after the device has output a complete
byte of data. After the device receives the NACK, it will end the Read operation and return to the standby mode.
Warning: If the last operation to the device accessed the Security Register, then a Random Read should be
performed to ensure that the address pointer is set to a known memory location within the
EEPROM.
Figure 7-3.
Sequential Read from a Current Address Read
Stop Conditon
by Master
Device Address
A2 A1 A0
Data Out Byte (n)
Data Out Byte (n+x)
1
MSB
0
1
0
1
0
D
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
D
1
SI/O
MSB
MSB
Start Condition
by Master
ACK
by Slave
ACK
by Master
NACK
by Master
Figure 7-4.
Sequential Read from a Random Read
Device Address
A2 A1 A0
Memory Address
1
MSB
0
1
0
0
0
x
A6 A5 A4 A3 A2 A1 A0
0
SI/O
MSB
Start Condition
by Master
ACK
by Slave
ACK
by Slave
Dummy Write
Device Address
A2 A1 A0
Stop Condition
by Master
Data Out Byte (n)
Data Out Byte (n + x)
1
0
1
0
1
0
D
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
D
1
MSB
MSB
MSB
Restart
by Master
ACK
by Slave
ACK
by Master
NACK
by Master
20
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
7.4
Read Operations in the Security Register
The Security Register can be read by using either a Random Read or a Sequential Read operation. Due to the
fact that the EEPROM and Security Register share a single address pointer register, a “dummy write” must be
performed to correctly set the address pointer in the Security Register. This is why a Random Read or
Sequential Read must be used as these sequences include a “dummy write.” Bits A7 through A5 are don’t care
bits as these fall outside the addressable range of the Security Register. Current Address Reads of the Security
Register are not supported.
In order to read the Security Register, the Device Address Byte must be specified with the opcode 1011b(Bh)
instead of the opcode 1010b(Ah).The Security Register can be read to read the 64-bit Serial Number or the
remaining user-programmable data.
7.4.1 Serial Number Read
The lower eight bytes of the Security Register contain a factory programmed, guaranteed unique, 64-bit Serial
Number. In order to guarantee a unique value, the entire 64-bit Serial Number must be read starting at Security
Register address location 00h. Therefore, it is recommended that a Sequential Read started with a Random
Read operation be used, ensuring that the Random Read sequence uses a Device Address Byte with opcode
1011b(Bh) specified in addition to the Memory Address Byte being set to 00h.
The first byte read out of the 64-bit Serial Number is the Product Identifier (A0h). Following the Product
Identifier, a 48-bit unique number is contained in bytes 1 though 6. The last byte of the serial number contains a
cyclic redundancy check (CRC) of the other 56 bits. The CRC is generated using the polynomial
X8 + X5 + X4 + 1. The structure of the 64-bit Serial Number is depicted in Table 7-1.
Table 7-1.
Byte 7
64-bit Factory Programmed Serial Number Organization
Byte 6 Byte 5 Byte 4 Byte 3
Byte 2
Byte 1
Byte 0
8-bit
Product
Identifier
(A0h)
8-bit
CRC Value
48-bit Unique Number
After all eight bytes of the Serial Number have been read, the Master can return a NACK (Logic 1) response to
end the Read operation and return the device to the standby mode. If the Master sends an ACK (Logic 0)
instead of a NACK, then the next byte (address location 08h) in the Security Register will be output. If the end of
the Security Register is reached, then the address pointer will “roll over” back to the beginning (address location
00h) of the Security Register.
Figure 7-5.
Serial Number Read
Device Address
Serial Number Starting Address
1
MSB
0
1
1
A2 A1 A0
0
0
X
X
X
0
0
0
0
0
0
SI/O
MSB
Start Condition
by Master
ACK
by Slave
ACK
by Slave
Dummy Write
Device Address
A2 A1 A0
Stop Condition
by Master
Serial Number Byte 00h
Serial Number Byte 07h
1
0
1
1
1
0
D
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
D
1
MSB
MSB
MSB
Restart
by Master
ACK
by Slave
ACK
by Master
NACK
by Master
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
21
7.5
Manufacturer ID Read
The AT21CS01 offers the ability to query the device for manufacturer, density, and revision information. By
using a specific opcode and following the format of a Current Address Read, the device will return a 24-bit value
that corresponds with the I2C identifier value reserved for Atmel, along with further data to signify a 1-Kbit
density and the device revision.
To read the Manufacturer ID data, the Master must send a Start condition, followed by the Device Address Byte
with the opcode of 1100b(Ch) specified, along the appropriate slave address combination and the Read/Write
bit set to a Logic 1. After the Device Address Byte has been sent, the AT21CS01 will return an ACK (Logic 0). If
the Read/Write bit is set to a Logic 0 to indicate a write, the device will NACK (Logic 1) since the Manufacturer
ID data is read-only.
After the device has returned an ACK, it will then send the first byte of Manufacturer ID data which contains the
eight most significant bits (D23 — D16) of the 24-bit data value. The Master can then return an ACK (Logic 0) to
indicate it successfully received the data, upon which the device will send the second byte (D15 — D8) of
Manufacturer ID data. The process repeats until all three bytes have been read out and the Master sends a
NACK (Logic 1) to complete the sequence. Figure 7-6 depicts this sequence below. If the Master ACKs
(Logic 0) the third byte, the internal pointer will roll over back to the first byte of Manufacturer ID data.
Figure 7-6.
Manufacturer ID Read
Stop Condition
by Master
Device Address
Manufacturer ID Byte 1
Manufacturer ID Byte 2
Manufacturer ID Byte 3
1
MSB
1
0
0
A2 A1 A0
1
0
D
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
D
1
SI/O
LSB
(D0)
MSB
(D23)
Start Condition
by Master
ACK
by Slave
ACK
by Master
ACK
by Master
NACK
by Master
Table 7-2 below provides the format of the Manufacturer ID data.
Table 7-2.
Manufacturer ID Data Format
AT21CS01 Response
Hex Value
Bit Position
within 24-bit value
Data Type
Field Width
Binary Value
Indication
Reserved Value
for Atmel
Manufacturer
Device Density
Device Revision
12 bits
D23 — D12
00Dh
0000-0000-1101
Single-Wire,
1Kb
9 bits
3 bits
D11 — D3
D2 — D0
0010-0000-0
000
200h
Revision 1
The Manufacturer Identifier portion of the ID is returned in the 12 most significant bits of the three bytes read
out. The value reserved for Atmel is 0000-0000-1101b(00Dh). Therefore, the first byte read out by the
device will be 00h. The upper nibble of the second byte read out is Dh.
The least significant 12 bits of the 24-bit ID is comprised of an Atmel defined value that indicates the device
density and revision. Bits D11 through D3 indicate the device density and bits D2 through D0 indicate the device
revision. The output is shown more specifically in Table 7-2.
The overall 24-bit value returned by the AT21CS01 is 00D200h.
22
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Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
8.
ROM Zones
8.1
ROM Zone Size and ROM Zone Registers
Certain applications require that portions of the EEPROM memory array be permanently protected against
malicious attempts at altering program code, data modules, security information, or encryption/decryption
algorithms, keys, and routines. To address these applications, the memory array is segmented into four different
memory zones of 256 bits each. A ROM Zone mechanism has been incorporated that allows any combination of
individual memory zones to be permanently locked so that they become read-only (ROM). Once a memory zone
has been converted to ROM, it can never be erased or programmed again, and it can never be unlocked from
the ROM state. Table 8-2 shows the address range of each of the four memory zones.
8.1.1 ROM Zone Registers
Each 256-bit memory zone has a corresponding single-bit ROM Zone Register that is used to control the ROM
status of that zone. These registers are nonvolatile and will retain their state even after a device power cycle or
reset operation. The following table outlines the two states of the ROM Zone Registers. Each ROM Zone
Register has specific ROM Zone Register Address that is reserved for read or write access.
Table 8-1.
ROM Zone Register Values
Value
ROM Zone Status
0
1
ROM Zone is not enabled and that memory zone can be programmed and erased (the default state).
ROM Zone is enabled and that memory zone can never be programmed or erased again.
Issuing the ROM Zone command to a particular ROM Zone Register Address will set the corresponding ROM
Zone Register to the Logic 1 state. Each ROM Zone Register can only be set once; therefore, once set to the
Logic 1 state, a ROM Zone cannot be reset back to the Logic 0 state.
Table 8-2.
ROM Zone Address Ranges
Memory
ROM Zone
Zone
Starting Memory Address
Ending Memory Address
Register Address
0
1
2
3
0h
1Fh
3Fh
5Fh
7Fh
01h
02h
04h
08h
20h
40h
60h
AT21CS01 [DATASHEET]
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23
8.2
Programming and Reading the ROM Zone Registers
8.2.1 Reading the status of a ROM Zone Register
To check the current status of a ROM Zone Register, the Master must emulate a Random Read sequence with
the exception that the opcode 0111b(7h) will be used. The dummy write portion of the Random Read sequence
is needed to specify which ROM Zone Register address is to be read.
This sequence begins by the Master sending a Start condition, followed by a Device Address Byte with the
opcode of 7h in the four most significant bits, along with the appropriate slave address combination and the
Read/Write bit set to a Logic 0. The AT21CS01 will respond with an ACK. Next, the ROM Zone Register
address intended to be read is transmitted to the device, and the device will ACK this byte as well. Then an
additional Start condition is sent to the device with the same Device Address Byte as before, but now with the
Read/Write bit set to a Logic 1, to which the device will return an ACK.
Following this Device Address Byte is an 8-bit ROM Zone Register Address byte. The four most significant bits
are not used and are therefore don’t care bits. The address sent to the device must match one of the ROM Zone
Register Addresses specified in Table 8-2. After the ROM Zone Register Address has been sent, the
AT21CS01 will return an ACK (Logic 0).
After the AT21CS01 has sent the ACK, the device will output either 00h or FFh data byte. A 00h data byte
indicates that the ROM Zone Register is zero, meaning the zone has not been set as ROM. If the device outputs
FFh data, then the memory zone has been set to ROM and cannot be altered.
Table 8-3.
Output Data
Read ROM Zone Register – Output Data
ROM Zone Register Value
00h
FFh
ROM Zone Register value is zero (zone is not set as ROM).
ROM Zone Register value is one (zone is permanently set as ROM).
Figure 8-1.
Reading the State of a ROM Zone Register
Stop Condition
by Master
Device Address
A2 A1 A0
ROM Zone Register Address
Device Address
A2 A1 A0
Data Out Byte (00h or FFh)
0
MSB
1
1
1
0
0
0
0
0
0
A3 A2 A1 A0
0
0
1
1
1
1
0
D
D
D
D
D
D
D
D
1
SI/O
MSB
MSB
MSB
Start Condition
by Master
ACK
by Slave
Restart
by Master
ACK
by Slave
ACK
by Slave
NACK
by Master
Dummy Write
8.2.2 Writing to a ROM Zone Register
A ROM Zone Register can only be written to a Logic 1 which will set the corresponding memory zone to a ROM
state. Once a ROM Zone Register has been written, it can never be altered again.
To write to a ROM Zone Register, the Master must send a Start condition, followed by the Device Address Byte
with the opcode of 0111b(7h) specified, along with the appropriate slave address combination and the
Read/Write bit set to a Logic 0. The device will return an ACK. After the Device Address Byte has been sent, the
AT21CS01 will return an ACK.
Following the Device Address Byte is an 8-bit ROM Zone Register Address byte. The address sent to the device
must match one of the ROM Zone Register Addresses specified in Table 8-2. After the ROM Zone Register
Address has been sent, the AT21CS01 will return an ACK.
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Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
After the AT21CS01 has sent the ACK, the Master must send an FFh data byte in order to set the appropriate
ROM Zone Register to the Logic 1 state. The device will then return an ACK and, after a Stop condition is
executed, the device will enter a self-time internal write cycle, lasting tWR. If a Stop condition is sent at any other
point in the sequence, the write operation to the ROM Zone Register is aborted. The device will not respond till
any commands until the tWR time has completed. This sequence is depicted in Figure 8-2.
Figure 8-2.
Writing to a ROM Zone Register
Stop Condition
by Master
Device Address
A2 A1 A0
ROM Zone Register Address
Data In Byte (FFh)
0
MSB
1
1
1
0
0
0
0
0
0
A3 A2 A1 A0
0
1
1
1
1
1
1
1
1
0
SI/O
MSB
MSB
Start Condition
by Master
ACK
by Slave
ACK
by Slave
ACK
by Slave
Warning: Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the register
being programmed to become corrupted. Note Section 6.1 for the behavior of the device while a
write cycle is in progress. If the Master must interrupt a write operation, the SI/O line must be driven
low for tDSCHG as noted in Section 3.1.2.
8.2.3 Freeze ROM Zone Registers
The current ROM Zone state can be frozen so that no further modifications to the ROM Zone Registers can be
made. Once frozen, this event cannot be reversed.
To freeze the state of the ROM Zone Registers, the Master must send a Start condition, followed by the Device
Address Byte with the opcode of 0001b(1h) specified, along with the appropriate slave address combination
and the Read/Write bit set to a Logic 0. The device will return either an ACK (Logic 0) response if the ROM Zone
Registers have not been previously frozen or a NACK (Logic 1) response if the registers have already been
frozen.
If the AT21CS01 returns an ACK, the Master must send a fixed arbitrary address byte value of 55h, to which the
device will return an ACK (Logic 0). Following the 55h Address byte, a Data byte of AAh must be sent by the
Master. The device will ACK after the AAh data byte. If an Address byte other than 55h or a Data byte other than
AAh is sent, the device will NACK (Logic 1) and the freeze operation will not be performed.
To complete the Freeze ROM Zone Register sequence, a Stop condition is required. If a Stop condition is sent
at any other point in this sequence, the operation is aborted. Since a Stop condition is defined as a null Bit
Frame with SI/O pulled high, the Master does not need to drive the SI/O line to accomplish this. After the Stop
condition is complete, the internally self-timed write cycle will begin.The SI/O pin must be pulled high via the
external pull-up resistor during the entire tWR cycle.
Figure 8-3.
Freezing the ROM Zone Registers
Stop Condition
by Master
Device Address
A2 A1 A0
Fixed Abitrary Address (55h)
Data In Byte (AAh)
0
MSB
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
SI/O
MSB
MSB
Start Condition
by Master
ACK
by Slave
ACK
by Slave
ACK
by Slave
Warning: Any attempt to drive the SI/O line low during the tWR time period may cause the Freeze operation to
not complete successfully, and must be avoided.
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
25
8.3
Device Response to a Write Command Within an Enabled ROM Zone
The AT21CS01will respond differently to a write command in a memory zone that has been set to ROM
compared to write command in a memory zone that has not been set to ROM. Writing to the EEPROM is
accomplished by sending a Start condition followed by a Device Address Byte with the opcode of 1010b(Ah),
the appropriate slave address combination, and the Read/Write bit set as a Logic 0. Since a memory address
has not been input at this point in the sequence, the device return an ACK. Next, the 8-bit Word Address is sent
which will result in an ACK from the device, regardless if that address is in a memory zone that has been set to
ROM. However, upon sending the Data Input byte, a write command to an address that was in a memory zone
that was set to ROM will result in a NACK response from the AT21CS01 and the device will be immediately
ready to accept a new command. If the address being written was in a memory zone that had not been set to
ROM, the device will return an ACK to the Data Input byte as per normal operation for write operations as
described in Section 6. on page 14.
26
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
9.
Electrical Specifications
9.1
Absolute Maximum Ratings
Functional operation at the “Absolute Maximum Ratings” or any other
conditions beyond those indicated in Section 9.2 is not implied or
guaranteed. Stresses beyond those listed under “Absolute Maximum
Ratings” and/or exposure to the “Absolute Maximum Ratings” for
extended periods may affect device reliability and cause permanent
damage to the device.
Temperature under Bias. . . . . . -55C to +125C
Storage Temperature . . . . . . . . -65C to +150C
Voltage on any pin
with respect to ground . . . . -0.6V to VPUP + 0.5V
The voltage extremes referenced in the “Absolute Maximum Ratings”
are intended to accommodate short duration undershoot/overshoot
pulses that the device may be subjected to during the course of
normal operation and does not imply or guarantee functional device
operation at these levels for any extended period of time.
DC Output Current . . . . . . . . . . . . . . . . . . 5.0mA
9.2
9.3
DC and AC Operating Range
Table 9-1.
DC and AC Operating Range
AT21CS01
Operating Temperature (Case)
VPUP Voltage tied to SI/O
Industrial Temperature Range
Low Voltage Grade
-40C to +85C
1.7V to 3.6V
DC Characteristics
Table 9-2.
DC Characteristics
Parameters are applicable over the operating range in Section 9.2, unless otherwise noted.
Symbol
Parameter
Test Condition
High Speed Mode
Standard Speed Mode
VPUP = 1.7V
Min
1.7
Typical(1)
Max
3.6
Units
V
VPUP
Pull-up Voltage
2.7
3.6
V
130
0.2
200
1.8
RPUP
Pull-up Resistance
VPUP = 2.7V
k
k
mA
mA
μA
μA
V
VPUP = 3.6V
0.33
—
4
IA1
IA2
Active Current, Read
Active Current, Write
VPUP = 3.6V
VPUP = 3.6V
VPUP = 1.8V(2)
VPUP = 3.6V
SI/O = VPUP
0.08
0.20
0.6
0.3
—
0.5
—
1.5
ISB
Standby Current
SI/O = VPUP
—
0.7
2.5
VIL
Input Low Level(2)(3)
Input High Level(2)(3)
SI/O Hysteresis(2)(3)(4)
Output Low Level
Bus Capacitance
–0.6
VPUP x 0.7
0.128
0
0.5
VIH
VPUP + 0.5
1.17
0.4
V
VHYS
VOL
CBUS
V
IOL = 4mA
V
—
1000
pF
Notes: 1. Typical values characterized at TA = +25°C unless otherwise noted.
2. This parameter is characterized but is not 100% tested in production.
3. VIH, VIL, and VHYS are a function of the internal supply voltage, which is a function of VPUP, RPUP, CBUS, and
timing used. Use of a lower VPUP, higher RPUP, higher CBUS, and shorter tRCV creates lower VIH, VIL and VHYS
values.
4. Once VIH is crossed on a rising edge of SI/O, the voltage on SI/O must drop at least by VHYS to be detected as
a Logic 0.
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
27
9.4
AC Characteristics
9.4.1 Reset and Discovery Response Timing
Table 9-3. Reset and Discovery Response Timing
Parameters applicable over operating range in Section 9.2, unless otherwise noted. Test conditions shown in Note 3.
Standard Speed(1)
High Speed
Symbol Parameter and Condition
Units
μs
Min
Max
Min
Max
tRESET
tDSCHG
tRRT
Reset Low Time, Device in Inactive State
480
—
48
150
8
—
Discharge Low Time, Device in Active Write Cycle (tWR
)
150
N/A
N/A
N/A
N/A
N/A
—
—
—
μs
Reset Recovery time
N/A
N/A
N/A
N/A
N/A
μs
(2)
tDRR
Discovery Response Request
1
2 - tPUP
24
μs
tDACK
tMSDR
tHTSS
Discovery Response Acknowledge Time
Master Strobe Discovery Response Time
SI/O High Time for Start / Stop Condition
8
μs
2
6
μs
150
—
μs
Notes: 1. Due to the fact that the device will default to High Speed mode upon reset, the Reset and Discovery Response Timing
after tRESET does not apply for Standard Speed Mode. High Speed Mode timing applies in all cases after tRESET
.
2. tPUP is the time required once the SI/O line is released to be pulled up from VIL to VIH. This value is application specific
and is a function of the loading capacitance on the SI/O line as well as the RPUP chosen. Limits for these values are
provided in Section 9.3.
3. AC measurement conditions for the table above:
Loading capacitance on SI/O: 100pF
RPUP (bus line pull-up resistor to VPUP): 1k; VPUP: 2.7V
9.4.2 Data Communication Timing
Table 9-4. Data Communication Timing
Parameters applicable over operating range in Section 9.2, unless otherwise noted. Test conditions shown in Note 1.
Standard Speed
High Speed
Min Max
tLOW0
tPUP(2) + tRCV
Symbol Parameter and Condition
Frame Type
Units
Min
Max
Input and Output
Bit Frame
+
tBIT
Bit Frame Duration
40
100
25
—
μs
SI/O High Time for Start / Stop
Condition
tHTSS
Input Bit Frame
600
—
150
μs
tLOW0
tLOW1
tRD
SI/O Low Time, Logic 0 Condition
SI/O Low Time, Logic 1 Condition
Input Bit Frame
Input Bit Frame
24
4
64
6
1
1
16
μs
μs
μs
μs
μs
8
8 - tPUP
8
2
(2)
(2)
Master SI/O Low Time During Read Output Bit Frame
4
2 - tPUP
(2)
(2)
tMRS
tHLD0
Master Read Strobe Time
Output Bit Frame tRD + tPUP
tRD + tPUP
2
6
Data Output Hold Time (Logic 0)
Output Bit Frame
8
8
24
2
Input and Output
Bit Frame
tRCV
Slave Recovery Time
—
—
2(3)
—
—
—
μs
μs
tNOISE
Noise filtering capability on SI/O
Input Bit Frame
0.5
Notes: 1. AC measurement conditions for the table above:
Loading capacitance on SI/O: 100pF
RPUP (bus line pull-up resistor to VPUP): 1k; VPUP: 2.7V
2. tPUP is the time required once the SI/O line is released to be pulled up from VIL to VIH. This value is application specific
and is a function of the loading capacitance on the SI/O line as well as the RPUP chosen. Limits for these values are
provided in Section 9.3.
3. The system designer must select an combination of RPUP, CBUS, and tBIT such that the minimum tRCV is satisfied. The
relationship of tRCV within the bit frame can be expressed by the following formula: tBIT = tLOW0 + tPUP + tRCV
.
28
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
9.5
EEPROM Cell Performance Characteristics
Operation
Test Condition
Min
Max
Units
TA = 25°C, VPUP(min) < VPUP < VPUP(max)
Byte or Page Write Mode
Write Cycle Time (tWR
)
—
5
ms
TA = 25°C, VPUP(min) < VPUP < VPUP(max)
Byte or Page Write Mode
Write Endurance(1)
Data Retention(2)
1,000,000
100
—
—
Write Cycles
Years
TA = 55°C, VPUP(min) < VPUP < VPUP(max)
Notes: 1. Write endurance performance is determined through characterization and the qualification process.
2. The data retention capability is determined through qualification and checked on each device in production.
9.6
Device Default Condition from Atmel
The AT21CS01 is delivered with the EEPROM array set to Logic 1 state resulting in FFh data in all locations.
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
29
10. Ordering Information
10.1 Ordering Code Detail
A T 2 1 C S 0 1 - S S H M # # - T
Atmel Designator
Shipping Carrier Option
T
B
= Tape and Reel
= Bulk (Tubes)
Product Family
21CS = Single Wire Serial EEPROM
with 64-bit, Read-only Serial Number
Product Variation
10 = 0-0-0 Slave Address (A ,A ,A )
11 = 0-0-1 Slave Address (A2,A1,A0)
12 = 0-1-0 Slave Address (A2,A1,A0)
13 = 0-1-1 Slave Address (A2,A1,A0)
14 = 1-0-0 Slave Address (A2,A1,A0)
15 = 1-0-1 Slave Address (A2,A1,A0)
16 = 1-1-0 Slave Address (A2,A1,A0)
17 = 1-1-1 Slave Address (A2,A1,A0)
0B = 0-0-0 Slave Address (A22,A11,A00),
WLCSP package with
Device Density
01 = 1 Kilobit
Back Side Coating
Operating Voltage
M
= 1.7V to 3.6V
Package Device Grade or
Wafer/Die Thickness
H = Green, NiPdAu Lead Finish
Industrial Temperature Range
(-40°C to +85°C)
U = Green, SnAgCu Ball
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Package Option
SS = JEDEC SOIC
ST = SOT23
U
= WLCSP
WWU= Wafer Unsawn
30
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
10.2 Ordering Code Information
Delivery Information
Operation
Range
Atmel Ordering Code
Lead Finish
Package
Form
Quantity
AT21CS01-SSHM##-T
Tape and Reel 4,000 per Reel
NiPdAu
(Lead-free/Halogen-free)
8S1
AT21CS01-SSHM##-B
AT21CS01-STUM##-T
AT21CS01-UUM0B-T(1)
Bulk (Tubes)
100 per Tube
Industrial
Temperature
(-40C to 85C)
Matte Tin
(Lead-free/Halogen-free)
3TS1
4U-6
Tape and Reel 5,000 per Reel
Tape and Reel 5,000 per Reel
Note 2
SnAgCu
(Lead-free/Halogen-free)
AT21CS01-WWU11M(2)
N/A
Wafer Sale
Notes: 1. WLCSP Package
This device includes a backside coating to increase product robustness.
CAUTION: Exposure to ultraviolet (UV) light can degrade the data stored in EEPROM cells. Therefore,
customers who use a WLCSP product must ensure that exposure to ultraviolet light
does not occur.
2. For wafer sales, please contact Atmel Sales.
Package Type
8S1
8-lead, 0.15” wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
3-lead, 1.30mm body, Plastic Thin Shrink Small Outline Package (SOT23)
4-ball, 2 x 2 Grid Array, 0.4mm minimum pitch, Wafer Level Chip Scale Package (WLCSP)
3TS1
4U-6
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
31
11. Part Markings
AT21CS01: Package Marking Information
8-lead SOIC
3-lead SOT-23
4-ball WLCSP
Top Mark
###%U
YMXX
ATMLHYWW
###&%
AAAAAAAA
XX
@
Bottom Mark
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT21CS01
Truncation Code ###: K1
Date Codes
Slave Address
Y = Year
4: 2014
5: 2015
6: 2016
7: 2017
M = Month
A: January
B: February
...
WW = Work Week of Assembly
% = Slave Address
8: 2018
9: 2019
0: 2020
1: 2021
02: Week 2
04: Week 4
...
A: Address 000 E: Address 100
B: Address 001 F: Address 101
C: Address 010 G: Address 110
D: Address 011 H: Address 111
L: December
52: Week 52
Country of Assembly
@ = Country of Assembly
Voltage & = Voltage
Lot Number
AAA...A = Atmel Wafer Lot Number
Grade/Lead Finish Material
H: Industrial/NiPdAu
M: 1.7V min
Trace Code
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
10/30/14
TITLE
DRAWING NO.
REV.
AT21CS01SM, AT21CS01 Package Marking Information
21CS01SM
B
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
32
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
12. Packaging Information
12.1 8S1 — 8-lead SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
–
0.10
MAX
1.75
0.25
NOM
–
–
NOTE
SYMBOL
A1
A
A1
b
0.31
0.17
–
0.51
0.25
C
D
E
E1
e
–
4.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
–
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
L
0.40
0°
1.27
8°
Ø
–
3/6/2015
DRAWING NO. REV.
8S1
TITLE
GPC
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
SWB
H
Package Drawing Contact:
packagedrawings@atmel.com
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
33
12.2 3ST1 — 3-lead SOT23
3
GND
E1
E
C
L
SDA
VCC
1
2
e1
End View
Top View
b
A2
A
SEATING
PLANE
e
A1
D
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. Dimension D does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.25mm per end. Dimension E1 does not include interlead flash
or protrusion. Interlead flash or protrusion shall not exceed
0.25mm per side.
2. The package top may be smaller than the package bottom.
Dimensions D and E1 are determined at the outermost extremes
of the plastic body exclusive of mold flash, tie bar burrs, gate
burrs and interlead flash, but including any mismatch between
the top and bottom of the plastic body.
MIN
0.89
0.01
0.88
2.80
2.10
1.20
MAX
1.12
0.10
1.02
3.04
2.64
1.40
NOM
NOTE
SYMBOL
A
-
A1
A2
D
-
-
1,2
1,2
2.90
E
-
3. These dimensions apply to the flat section of the lead between
0.08 mm and 0.15mm from the lead tip.
E1
L1
e1
b
1.30
0.54 REF
1.90 BSC
-
0.50
3
0.30
This drawing is for general information only. Refer to JEDEC
Drawing TO-236, Variation AB for additional information.
12/11/09
REV.
TITLE
GPC
TBG
DRAWING NO.
3TS1, 3-lead, 1.30mm Body, Plastic Thin
Shrink Small Outline Package (Shrink SOT)
3TS1
B
Package Drawing Contact:
packagedrawings@atmel.com
34
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
12.3 4U-6 — 4-ball WLCSP
TOP VIEW
BOTTOM SIDE
0.015 (4X)
k
A1 CORNER
1
2
2
1
A
A1 CORNER
A
A
B
e1
E
B
db
d1
B
D
d0.015 m C
v
SIDE VIEW
0.05
m
d
C A B
A
A1
SEATING PLANE
A2
C
k 0.075 C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
TYP
MAX
NOTE
3
A
A1
A2
D
0.313
0.334
0.355
—
—
0.094
0.240
—
—
PIN ASSIGNMENT MATRIX
Contact Atmel for details
0.400 BSC
d1
E
1
2
Contact Atmel for details
0.400 BSC
A
B
NC
NC
SI/O
GND
e1
b
0.170
0.185
0.200
Note: 1. Dimensions are NOT to scale.
2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu.
3. Product offered with Back Side Coating.
8/7/15
TITLE
GPC
DRAWING NO.
REV.
4U-6, 4-ball 2x2 Array, 0.40mm Pitch
Wafer Level Chip-Scale Package (WLCSP) with BSC
GPH
4U-6
B
Package Drawing Contact:
packagedrawings@atmel.com
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
35
13. Revision History
Doc. No.
Date
Comments
8903A
08/2015
Initial document release.
36
AT21CS01 [DATASHEET]
Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015
X X
X X X X
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
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© 2015 Atmel Corporation. / Rev.: Atmel-8903A-SEEPROM-AT21CS01-Datasheet_082015.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
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