AT17LV65-10PC [ATMEL]
FPGA Configuration E2PROM; FPGA配置E2PROM
| 型号： | AT17LV65-10PC |
| 厂家： | 
ATMEL |
| 描述： | FPGA Configuration E2PROM |
| 文件： | 总10页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories Designed
To Store Configuration Programs For Programmable Gate Arrays
• Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
• Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs,
XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000
• Cascadable To Support Additional Configurations or Future Higher-density Arrays
(17C128 and 17C256 only)
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available In the Space-efficient Plastic DIP or Surface-mount
PLCC and SOIC Packages
• In-System Programmable Via 2-Wire Bus
FPGA
Configuration
E2PROM
• Emulation of 24CXX Serial EPROMs
• Available in 3.3V ± 10% LV Version
Description
65K, 128K and 256K
The AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA Configuration
EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration mem-
ory for Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-pin
DIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The AT17 Series
organization supplies enough memory to configure one or multiple smaller FPGAs.
Using a special feature of the AT17 Series, the user can select the polarity of the reset
function by programming a special EEPROM bit.
AT17C65
AT17C128
AT17C256
The AT17 Series can be programmed with industry standard programmers.
Pin Configurations
20-pin PLCC
20-Pin SOIC
8-Pin DIP
0391E-A–5/97
Controlling The AT17 Series Serial EEPROMs
Most connections between the FPGA device and the Serial
tion cycle. If a system reset is applied to the FPGA, it will
EEPROM are simple and self-explanatory.
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the AT17 Series
does not see the external reset signal and will not reset its
internal address counters and, consequently, will remain
out of sync with the FPGA for the remainder of the configu-
ration cycle.
• The DATA output of the AT17 Series drives DIN of the
FPGA devices.
• The master FPGA CCLK output drives the CLK input of
the AT17 Series.
Condition 2
• The CEO output of any AT17C/LV128/256 drives the CE
input of the next AT17C/LV128/256 in a cascade chain of
PROMs.
The FPGA D/P output drives only the CE input of the AT17
Series, while its OE input is driven by the inversion of the
input to the FPGA RESET input pin. This connection works
under all normal circumstances, even when the user aborts
a configuration before D/P has gone High. A High level on
the RESET/OE input to the AT17C/LVxxx – during FPGA
reset – clears the Configurator's internal address pointer,
so that the reconfiguration starts at the beginning. The
AT17 Series does not require an inverter since the RESET
polarity is programmable.
• SER_EN must be connected to VCC
.
There are, however, two different ways to use the inputs
CE and OE, as shown in the AC Characteristics wave-
forms.
Condition 1
The simplest connection is to have the FPGA D/P output
drive both CE and RESET/OE in parallel (Figure 1). Due to
its simplicity, however, this method will fail if the FPGA
receives an external reset condition during the configura-
Block Diagram
AT17 Series
2
AT17 Series
Pin Configurations
PLCC/
SOIC
Pin
2
DIP
Pin
1
Name
I/O Description
DATA
I/O Three-state DATA output for reading. Input/Output pin for programming.
Clock input. Used to increment the internal address and bit counter for reading
and programming.
4
2
CLK
I
RESET/Output Enable input (when SER_EN is High). A Low level on both the
CE and RESET/OE inputs enables the data output driver. A High level on
RESET/OE resets both the addresss and bit counters. A logic polarity of this
input is programmable as either RESET/OE or RESET/OE. This document
describes the pin as RESET/OE.
6
8
3
4
RESET/OE
CE
I
Chip Enable input. Used for device selection. A Low level on both CE and OE
enables the data output driver. A High level on CE disables both the address
and bit counters and forces te device into a low power mode. Note this pin will
not enable/disable the device in 2-wire Serial mode (ie; when SER_EN is Low).
10
14
5
6
GND
CEO
Ground Pin
O
Chip Enable Out output. This signal is asserted Low on the clock cycle following
the last bit read from the memory. It will stay Low as long as CE and OE are
both Low. It will then follow CE until OE goes High. Thereafter CEO will stay
High until the entire PROM is read again and senses the status of RESET
polarity.
A2
I
I
Device selection input, A2. This is used to enable (or select) the device during
programming and when SER_EN is Low (see Programming Guide for more
details).
Serial enable is normally high during FPGA loading operations. Bringing
SER_EN low, enables the 2-wire serial interface for programming.
17
20
7
8
SER_EN
VCC
+3.3V/+5V power supply pin.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature.........................-55°C to +125°C
Storage Temperature............................-65°C to +150°C
Voltage on Any Pin
with Respect to Ground.................... -0.1V to VCC + 0.5V
Supply Voltage (Vcc).............................. -0.5 V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.)... 260°C
ESD (RZAP = 1.5K, CZAP = 100pF) ........................2000V
3
After configuration is complete, the address counters of all
cascaded Configurators are reset if the reset signal drives
the RESET/OE on each Configurator Active.
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power up, or on command, depending on the state of the
three FPGA mode pins. In Master Mode, the FPGA auto-
matically loads the configuration program from an external
memory. The Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE inputs can be tied to ground. For
more details, please reference the AT17C Series Program-
ming Guide.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the 2-
wire interface. The programming is done at VCC supply
only. Programming super voltages are generated inside the
chip. See the Programming Specification for Atmel's Con-
figuration Memories Application Note for further informa-
tion. The AT17C Series parts are read/write at 5V nominal.
The AT17LV parts are read/write at 3.0V nominal.
Cascading Serial Configuration
EEPROMs
(AT17C/LV128 and AT17C/LV256)
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded Configurators provide additional memory (17C/
LV128 and 17C/LV256 only).
After the last bit from the first Configurator is read, the next
clock signal to the Configurator asserts its CEO output Low
and disables its DATA line. The second Configurator recog-
nizes the Low level on its CE input and enables its DATA
output.
AT17C/LVXXX Reset Polarity
The AT17C/LVXXX lets the user choose the reset polarity
as either RESET/OE or RESET/OE.
Standby Mode
Figure 1. Condition 1 Connection
The AT17C/LVXXX enters a low-power standby mode
whenever CE is asserted High. In this mode, the Configura-
tor consumes less than 1.0 mA of current. The output
remains in a high impedance state regardless of the state
of the OE input.
Operating Conditions
AT17CXXX AT17LVXXX
Symbol Description
Min/Max
Min/Max
Units
Supply voltage relative to GND
-0°C to +70°C
Commercial
4.75/5.25
3.0/3.6
V
Supply voltage relative to GND
-40°C to +85C°
VCC
Industrial
Military
4.5/5.5
4.5/5.5
3.0/3.6
3.0/3.6
V
V
Supply voltage relative to GND
-55°C to +125C
AT17 Series
4
AT17 Series
DC Characteristics
VCC = 5V ± 5% Commercial / 5V ± 10% Ind./Mil.
Symbol Description
Min
2.0
0
Max
VCC
0.8
Units
V
VIH
VIL
High-level input voltage
Low-level input voltage
V
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level output voltage (IOH = -4 mA)
Low-level output voltage (IOL = +4 mA)
High-level output voltage (IOH = -4 mA)
Low-level output voltage (IOL = +4 mA)
High-level output voltage (IOH = -4 mA)
Low-level output voltage (IOL = +4 mA)
Supply current, active mode
3.7
V
Commercial
Industrial
Military
0.32
0.37
V
3.6
3.5
V
V
V
0.4
10
10
75
150
1
V
mA
µA
µA
µA
mA
mA
Input or output leakage current (VIN = VCC or GND)
-10
Commercial
Industrial/Military
Commercial
Supply current, standby mode AT17C256
Supply current, standby mode AT17C128/65
ICCS
Industrial/Military
2
DC Characteristics
VCC = 3.3V ± 10%
Symbol Description
Min
2.0
0
Max
VCC
0.8
Units
V
VIH
VIL
High-level input voltage
Low-level input voltage
V
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level output voltage (IOH = -2.5 mA)
Low-level output voltage (IOL = +3 mA)
High-level output voltage (IOH = -2 mA)
Low-level output voltage (IOL = +3 mA)
High-level output voltage (IOH = -2 mA)
Low-level output voltage (IOL = +2.5 mA)
Supply current, active mode
2.4
V
Commercial
Industrial
Military
0.4
0.4
V
2.4
2.4
V
V
V
0.4
5
V
mA
µA
µA
µA
Input or output leakage current (VIN = VCC or GND)
-10
10
50
100
Commercial
ICCS
Supply current, standby mode
Industrial/Military
5
AC Characteristics
AC Characteristics When Cascading
AT17 Series
6
AT17 Series
AC Characteristics for AT17C256
VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil.
Commercial
Min Max
Industrial/Military
Symbol Description
Min
Max
25
Units
ns
(2)
TOE
TCE
OE to Data Delay
25
45
50
(2)
(2)
CE to Data Delay
45
ns
TCAC
CLK to Data Delay
55
ns
(2)
TOH
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
0
0
ns
(3)
TDF
50
50
ns
TLC
20
20
20
20
40
0
ns
THC
TSCE
THCE
CLK High Time
ns
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time to CLk (to guarantee proper counting)
OE High Time (guarantees counter is reset)
MAX Input Clock Frequency
35
ns
0
ns
THOE
FMAX
20
20
12.5
ns
12.5
MHz
AC Characteristics for AT17C256 When Cascading
VCC = 5V± 5% Commercial / VCC = 5V ± 10% Ind./Mil.
Commercial
Min Max
Industrial/Military
Symbol Description
Min
Max
50
Units
ns
(3)
TCDF
TOCK
TOCE
TOOE
CLK to Data Float Delay
50
35
35
30
(2)
(2)
(2)
CLK to CEO Delay
40
ns
CE to CEO Delay
35
ns
RESET/OE to CEO Delay
35
ns
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
7
AC Characteristics for AT17C65/128
VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil.
Commercial
Min Max
Industrial/Military
Symbol Description
Min
Max
150
50
Units
ns
(2)
TOE
TCE
OE to Data Delay
110
50
(2)
(2)
CE to Data Delay
ns
TCAC
CLK to Data Delay
50
55
ns
(2)
TOH
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
0
0
ns
(3)
TDF
50
50
ns
TLC
30
30
45
0
35
35
50
5
ns
THC
TSCE
THCE
CLK High Time
ns
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time to CLk (to guarantee proper counting)
OE High Time (guarantees counter is reset)
MAX Input Clock Frequency
ns
ns
THOE
FMAX
50
60
ns
(4)
10
10
MHz
AC Characteristics for AT17C65/128 When Cascading
VCC = 5V± 5% Commercial / VCC = 5V ± 10% Ind./Mil.
Commercial
Min Max
Industrial/Military
Symbol Description
Min
Max
50
Units
ns
(3)
TCDF
TOCK
TOCE
CLK to Data Float Delay
50
65
55
55
(2)
(2)
CLK to CEO Delay
75
ns
CE to CEO Delay
60
ns
(2)
TOE
RESET/OE to CEO Delay
55
ns
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
4. During cascade FMAX = 8 MHz.
AT17 Series
8
AT17 Series
AC Characteristics
VCC = 3.3V ± 10%
Commercial
Min Max
Industrial/Military
Symbol Description
Min
Max
45
Units
ns
(2)
TOE
TCE
OE to Data Delay
40
60
75
(2)
(2)
CE to Data Delay
60
ns
TCAC
CLK to Data Delay
80
ns
(2)
TOH
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
0
0
ns
(3)
TDF
55
55
ns
TLC
25
25
35
0
25
25
60
0
ns
THC
TSCE
THCE
CLK High Time
ns
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time to CLk (to guarantee proper counting)
OE High Time (guarantees counter is reset)
MAX Input Clock Frequency
ns
ns
THOE
FMAX
25
10
25
8
ns
(4)
10
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test lead = 50 pf.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV afrom steady state active levels.
4. During cascade FMAX = 8 MHz.
AC Characteristics When Cascading
VCC = 3.3V ± 10%
Commercial
Min Max
Industrial/Military
Symbol Description
Min
Max
60
Units
ns
(3)
TCDF
TOCK
TOCE
TOOE
CLK to Data Float Delay
60
55
55
40
(2)
(2)
(2)
CLK to CEO Delay
60
ns
CE to CEO Delay
60
ns
RESET/OE to CEO Delay
45
ns
9
Ordering Information - 5V Devices
Memory
Size (K)
Ordering Code
Package
Operation Range
64K
AT17C65-10PC
AT17C65-10JC
AT17C65-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17C65-10PI
AT17C65-10JI
AT17C65-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
128K
256K
AT17C128-10PC
AT17C128-10JC
AT17C128-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17C128-10PI
AT17C128-10JI
AT17C128-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
AT17C256-10PC
AT17C256-10JC
AT17C256-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17C256-10PI
AT17C256-10JI
AT17C256-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
Ordering Information - 3.3V Devices
Memory
Size (K)
Ordering Code
Package
Operation Range
64K
AT17LV65-10PC
AT17LV65-10JC
AT17LV65-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17LV65-10PI
AT17LV65-10JI
AT17LV65-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
128K
256K
AT17LV128-10PC
AT17LV128-10JC
AT17LV128-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17LV128-10PI
AT17LV128-10JI
AT17LV128-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
AT17LV256-10PC
AT17LV256-10JC
AT17LV256-10SC
8P3
20J
20S
Commercial
(0°C to 70°C)
AT17LV256-10PI
AT17LV256-10JI
AT17LV256-10SI
8P3
20J
20S
Industrial
(-40°C to 85°C)
Package Type
8P3
20J
20S
8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20-Lead, Plastic J-Leaded Chip Carrier (PLCC)
20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
AT17 Series
10
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