AT17LV128-10SL [ATMEL]
Configuration Memory, 128KX1, Serial, CMOS, PDSO20, 0.300 INCH, PLASTIC, MS-013AC, SOIC-20;
| 型号： | AT17LV128-10SL |
| 厂家： | 
ATMEL |
| 描述： | Configuration Memory, 128KX1, Serial, CMOS, PDSO20, 0.300 INCH, PLASTIC, MS-013AC, SOIC-20 时钟 ATM 异步传输模式 光电二极管 内存集成电路 |
| 文件： | 总26页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,
2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
• Supports both 3.3V and 5.0V Operating Voltage Applications
• In-System Programmable (ISP) via Two-Wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera® FLEX®, APEX™
Devices, ORCA®, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs
• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
• Very Low-power CMOS EEPROM Process
FPGA
Configuration
EEPROM
Memory
• Programmable Reset Polarity
• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP
Packages
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Low-power Standby Mode
• High-reliability
AT17LV65
– Endurance: 100,000 Write Cycles
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for
Commercial Parts (at 70°C)
• Green (Pb/Halide-free/RoHS Compliant) Package Options Available
AT17LV128
AT17LV256
AT17LV512
AT17LV010
AT17LV002
AT17LV040
1. Description
The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-
to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-
lead PLCC, 20-lead SOIC and 44-lead TQFP, see Table 1-1. The AT17LV series
Configurators uses a simple serial-access procedure to configure one or more FPGA
devices. The user can select the polarity of the reset function by programming four
EEPROM bytes. These devices also support a write-protection mechanism within its
programming mode.
3.3V and 5V
System Support
The AT17LV series configurators can be programmed with industry-standard pro-
grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
2321I–CNFG–2/08
Table 1-1.
AT17LV Series Packages
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
Package
AT17LV002
AT17LV040
(3)
8-lead LAP
8-lead PDIP
Yes
Yes
Yes
Yes
–
Yes
–
Use 8-lead
LAP(1)
Use 8-lead
LAP(1)
(3)
8-lead SOIC
Yes
20-lead PLCC
20-lead SOIC
44-lead TQFP
Yes
Yes(2)
–
Yes
Yes(2)
–
Yes
Yes(2)
Yes
–
–
Yes
Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC
package is not available for the AT17LV512/010/002 devices, it is possible to use an 8-lead
LAP package instead.
2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the
AT17LV512/010/002 devices.
3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.
2. Pin Configuration
Figure 2-1. 8-lead LAP
DATA 1
CLK 2
8 VCC
7 SER_EN
6 CEO (A2)
5 GND
(WP(1)) RESET/OE 3
CE 4
Figure 2-2. 8-lead SOIC
DATA
CLK
1
2
3
4
8
7
6
5
VCC
SER_EN
CEO (A2)
GND
(WP(1)) RESET/OE
CE
Figure 2-3. 8-lead PDIP
DATA
1
2
3
4
8
7
6
5
VCC
CLK
(WP(1)) RESET/OE
CE
SER_EN
CEO (A2)
GND
2
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
Figure 2-4. 20-lead PLCC
CLK
4
5
6
7
8
18 NC
(WP1(2)) NC
(WP(1)) RESET/OE
(WP2(2)) NC
17 SER_EN
16 NC
15 NC (READY(2))
14 CEO (A2)
CE
Notes: 1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
3. The CEO feature is not available on the AT17LV65 device.
Figure 2-5. 20-lead SOIC(1)
NC
DATA
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
NC
NC
CLK
SER_EN
NC
NC
RESET/OE
NC
NC
CEO (A2)
NC
CE
NC
NC
GND
NC
Note:
1. This pinout only applies to AT17LV65/128/256 devices.
3
2321I–CNFG–2/08
Figure 2-6. 20-lead SOIC(1)
DATA
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
NC
CLK
NC
SER_EN
NC
NC
NC
NC
NC
NC
NC
RESET/OE
CEO
NC
NC
CE
GND
Notes: 1. This pinout only applies to AT17LV512/010/002 devices.
2. The CEO feature is not available on the AT17LV65 device.
Figure 2-7. 44 TQFP
NC
NC
NC
NC
NC
NC
1
33
32
31
30
29
28
27
26
25
24
23
NC
2
NC
3
NC
4
NC
5
NC
6
NC
(WP1(1)) NC
7
NC
NC
NC
NC
NC
8
NC
9
NC
10
11
NC
READY
Note:
1. This pin is only available on AT17LV002 devices.
4
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
Figure 2-8. Block Diagram
SER_EN
WP1(2)
WP2(2)
POWER ON
RESET
READY(2)
(1)
Notes: 1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
3. The CEO feature is not available on the AT17LV65 device.
5
2321I–CNFG–2/08
3. Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly
with the FPGA device control signals. All FPGA devices can control the entire configuration pro-
cess and retrieve data from the configuration EEPROM without requiring an external intelligent
controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA
output pin and enable the address counter. When RESET/OE is driven High, the configuration
EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the
output of the AT17LV series configurator. If CE is held High after the RESET/OE reset pulse, the
counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven Low,
the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the
address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High,
this document will describe RESET/OE.
4. Pin Description
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002
AT17LV040
8
8
DIP/
LAP/
SOIC
8
DIP/
LAP
DIP/
LAP/
SOIC
20
PLCC
20
SOIC
20
PLCC
20
SOIC
20
PLCC
20
SOIC
44
TQFP
44
TQFP
Name
DATA
CLK
I/O
I/O
1
2
–
3
2
4
–
6
2
4
–
6
1
2
–
3
–
4
5
2
4
1
3
1
2
–
3
–
4
5
2
4
1
3
40
43
–
40
43
–
I
I
I
I
I
WP1
5
–
5
–
RESET/OE
WP2
6
8
6
8
13
–
13
–
7
–
7
–
CE
4
5
8
8
8
10
11
13
–
8
10
11
13
–
15
18
15
18
GND
10
10
10
10
CEO
O
I
6
14
14
6
14
6
14
21
21
A2
READY
SER_EN
VCC
O
I
–
7
8
–
–
–
7
8
15
17
20
–
–
7
8
15
17
20
–
23
35
38
23
35
38
17
20
17
20
18
20
18
20
Note:
1. The CEO feature is not available on the AT17LV65 device.
6
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
4.1
4.2
DATA
CLK
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
4.3
4.4
WP1
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010/002 devices.
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver. The logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed active Low. This document
describes the pin as RESET/OE.
4.5
4.6
4.7
WP
WP2
CE
Write protect (WP) input (when CE is Low) during programming only (SER_EN Low). When WP
is Low, the entire memory can be written. When WP is enabled (High), the lowest block of the
memory cannot be written. This pin is only available on AT17LV65/128/256 devices.
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010 devices.
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the Two-Wire Serial Programming mode (SER_EN Low).
4.8
4.9
GND
CEO
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
Chip Enable Output (active Low). This output goes Low when the address counter has reached
its maximum value. In a daisy chain of AT17LV series devices, the CEO pin of one device must
be connected to the CE input of the next device in the chain. It will stay Low as long as CE is
Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until
the entire EEPROM is read again. This CEO feature is not available on the AT17LV65 device.
7
2321I–CNFG–2/08
4.10 A2
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
4.11 READY
4.12 SER_EN
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin is used.
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to VCC
.
4.13 VCC
3.3V ( 10ꢀ) and 5.0V ( 5ꢀ Commercial, 10ꢀ Industrial) power supply pin.
5. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17LV Serial Configuration EEPROM has
been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil-
inx applications.
6. Control of Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and
self-explanatory.
• The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17LV series configurator.
• The CEO output of any AT17LV series configurator drives the CE input of the next
configurator in a cascaded chain of EEPROMs.
• SER_EN must be connected to VCC (except during ISP).
• The READY(1) pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
Note:
1. This pin is not available for the AT17LV65/128/256 devices.
8
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
7. Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its
CEO output Low and disables its DATA line driver. The second configurator recognizes the Low
level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be
tied to its inactive (High) level.
The AT17LV65 devices do not have the CEO feature to perform cascaded configurations.
8. AT17LV Series Reset Polarity
The AT17LV series configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. This feature is supported by industry-standard programmer
algorithms.
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be pro-
grammed by the Two-Wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip.
10. Standby Mode
The AT17LV series configurators enter a low-power standby mode whenever CE is asserted
High. In this mode, the AT17LV65/128/256 configurator consumes less than 50 µA of current at
3.3V (100 µA for the AT17LV512/010 and 200 µA for the AT17LV002/040). The output remains
in a high-impedance state regardless of the state of the OE input.
9
2321I–CNFG–2/08
11. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Operating Temperature................................... -40°C to +85°C
Storage Temperature.................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.)............ 260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
12. Operating Conditions
3.3V
5V
Symbol
Description
Min
Max
Min
Max
Units
Supply voltage relative to GND
-0°C to +70°C
Commercial
3.0
3.6
4.75
5.25
V
VCC
Supply voltage relative to GND
-40°C to +85°C
Industrial
3.0
3.6
4.5
5.5
V
10
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
13. DC Characteristics
VCC = 3.3V 10ꢀ
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002/
AT17LV040
Symbol
VIH
Description
Min
Max
VCC
0.8
Min
Max
VCC
0.8
Min
Max
VCC
0.8
Units
V
High-level Input Voltage
2.0
0
2.0
0
2.0
0
VIL
Low-level Input Voltage
V
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
Supply Current, Active Mode
2.4
2.4
2.4
V
Commercial
Industrial
0.4
0.4
0.4
V
2.4
-10
2.4
-10
2.4
-10
V
0.4
5
0.4
5
0.4
5
V
mA
µA
µA
µA
Input or Output Leakage Current (VIN = VCC or GND)
Commercial
Industrial
10
50
100
10
10
100
100
150
150
ICCS
Supply Current, Standby Mode
14. DC Characteristics
VCC = 5V 5ꢀ Commercial; VCC = 5V 10ꢀ Industrial
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002/
AT17LV040
Symbol
VIH
Description
Min
Max
VCC
0.8
Min
Max
VCC
0.8
Min
Max
VCC
0.8
Units
V
High-level Input Voltage
2.0
0
2.0
0
2.0
0
VIL
Low-level Input Voltage
V
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
Supply Current, Active Mode
3.7
3.86
3.86
V
Commercial
Industrial
0.32
0.32
0.32
V
3.6
-10
3.76
-10
3.76
-10
V
0.37
10
0.37
10
0.37
10
V
mA
µA
µA
µA
Input or Output Leakage Current (VIN = VCC or GND)
Commercial
Industrial
10
10
10
75
200
200
350
350
ICCS
Supply Current, Standby Mode
150
11
2321I–CNFG–2/08
15. AC Waveforms
CE
TSCE
THCE
TSCE
RESET/OE
CLK
THOE
TLC
THC
TOH
TOE
TCAC
TDF
TCE
DATA
TOH
16. AC Waveforms when Cascading
RESET/OE
CE
CLK
T
CDF
FIRST BIT
LAST BIT
DATA
CEO
T
OCK
T
T
OOE
OCE
T
OCE
12
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
17. AC Characteristics
VCC = 3.3V 10ꢀ
AT17LV65/128/256
Commercial Industrial
AT17LV512/010/002/040
Commercial Industrial
Symbol
Description
Min
Max
50
Min
Max
Min
Max
50
Min
Max
Units
ns
(1)
TOE
OE to Data Delay
55
60
80
55
60
60
(1)
TCE
CE to Data Delay
60
55
ns
(1)
TCAC
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
75
55
ns
TOH
0
0
0
0
ns
(2)
TDF
55
55
50
50
ns
TLC
THC
25
25
25
25
25
25
25
25
ns
CLK High Time
ns
CE Setup Time to CLK
(to guarantee proper counting)
TSCE
35
60
30
35
ns
ns
CE Hold Time from CLK
(to guarantee proper counting)
THCE
0
0
0
0
THOE
FMAX
OE High Time (guarantees counter is reset)
Maximum Clock Frequency
25
25
25
25
ns
10
10
15
10
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
18. AC Characteristics when Cascading
VCC = 3.3V 10ꢀ
AT17LV65/128/256
Commercial Industrial
Min Max
AT17LV512/010/002/040
Commercial Industrial
Min Max
Symbol
Description
Min
Max
60
Min
Max
50
Units
ns
(2)
TCDF
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
60
60
60
45
50
55
40
35
10
(1)
TOCK
55
50
ns
(1)
TOCE
55
35
ns
(1)
TOOE
RESET/OE to CEO Delay
40
35
ns
FMAX
Maximum Clock Frequency
8
8
12.5
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
13
2321I–CNFG–2/08
19. AC Characteristics
VCC = 5V 5ꢀ Commercial; VCC = 5V 10ꢀ Industrial
AT17LV65/128/256
Commercial Industrial
AT17LV512/010/002/040
Commercial Industrial
Symbol
Description
Min
Max
30
Min
Max
Min
Max
30
Min
Max
Units
ns
(1)
TOE
OE to Data Delay
35
45
55
35
45
50
(1)
TCE
CE to Data Delay
45
45
ns
(1)
TCAC
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
50
50
ns
TOH
0
0
0
0
ns
(2)
TDF
50
50
50
50
ns
TLC
THC
20
20
20
20
20
20
20
20
ns
CLK High Time
ns
CE Setup Time to CLK (to guarantee proper
counting)
TSCE
35
40
20
25
ns
ns
CE Hold Time from CLK (to guarantee proper
counting)
THCE
0
0
0
0
THOE
FMAX
OE High Time (guarantees counter is reset)
Maximum Clock Frequency
20
20
20
20
ns
12.5
12.5
15
15
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
20. AC Characteristics when Cascading
VCC = 5V 5ꢀ Commercial; VCC = 5V 10ꢀ Industrial
AT17LV65/128/256
Commercial Industrial
Min Max
AT17LV512/010/002/040
Commercial Industrial
Min Max
Symbol
Description
Min
Max
50
Min
Max
50
Units
ns
(2)
TCDF
CLK to Data Float Delay
CLK to CEO Delay
50
40
35
35
10
50
40
(1)
TOCK
35
35
ns
(1)
TOCE
CE to CEO Delay
35
35
35
ns
(1)
TOOE
RESET/OE to CEO Delay
Maximum Clock Frequency
30
30
30
ns
FMAX
10
12.5
12.5
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
14
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
21. Thermal Resistance Coefficients(1)
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002
AT17LV040
Package Type
θ
JC [°C/W]
45
45
135.71
37
45
–
8CN
4
Leadless Array Package (LAP)
θJA
115.71
37
159.60
–
–
[°C/W](2)
θ
JC [°C/W]
–
–
Plastic Dual Inline Package
(PDIP)
8P3
θJA
107
45
107
–
–
[°C/W](2)
θ
JC [°C/W]
–
–
Plastic Gull Wing Small Outline
(SOIC)
8S1
20J
θJA
150
35
–
–
–
[°C/W](2)
θ
JC [°C/W]
35
35
90
–
Plastic Leaded Chip Carrier
(PLCC)
θJA
90
90
–
[°C/W](2)
θ
JC [°C/W]
–
Plastic Gull Wing Small Outline
(SOIC)
20S2
44A
θJA
–
[°C/W](2)
θ
JC [°C/W]
–
–
–
–
17
62
17
62
Thin Plastic Quad Flat
Package (TQFP)
θJA
[°C/W](2)
Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site.
2. Airflow = 0 ft/min.
15
2321I–CNFG–2/08
Figure 21-1. Ordering Code
AT17LV65A-10PC
Vo l t ag e
Size (Bits)
Special Pinouts
Package
Te mperature
C
P
N
J
3.0V to 5.5V
65
= 65K
A
= Altera
= 8CN4 C = Commercial
128
256
512
010
002
040
= 128K
= 256K
= 512K
= 1M
Blank = Xilinx/Atmel/
Other
= 8P3
= 8S1
= 20J
I = Industrial
U = Fully Green
S
= 20S2
TQ = 44A
BJ = 44J
= 2M
= 4M
Package Type
8CN4
8P3
8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
20-lead, Plastic J-leaded Chip Carrier (PLCC)
20J
20S2
44A
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
16
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
22. Ordering Information
22.1 Standard Package Options
Memory Size
Ordering Code
Package(2)(3)
8P3
8S1
20J
Operation Range
AT17LV65-10PC
AT17LV65-10NC
AT17LV65-10JC
AT17LV65-10PI
AT17LV65-10NI
AT17LV65-10JI
Commercial
(0° C to 70°C)
64-Kbit(1)
8P3
8S1
20J
Industrial
(-40° C to 85°C)
AT17LV128-10PC
AT17LV128-10NC
AT17LV128-10JC
AT17LV128-10SC
AT17LV128-10PI
AT17LV128-10NI
AT17LV128-10JI
AT17LV128-10SI
AT17LV256-10PC
AT17LV256-10NC
AT17LV256-10JC
AT17LV256-10SC
AT17LV256-10PI
AT17LV256-10NI
AT17LV256-10JI
AT17LV256-10SI
AT17LV512-10PC
AT17LV512-10JC
AT17LV512-10PI
AT17LV512-10JI
AT17LV010-10PC
AT17LV010-10JC
AT17LV010-10PI
AT17LV010-10JI
8P3
8S1
20J
Commercial
(0° C to 70°C)
20S2
8P3
8S1
20J
128-Kbit(1)
Industrial
(-40° C to 85°C)
20S2
8P3
8S1
20J
Commercial
(0° C to 70°C)
20S2
8P3
8S1
20J
256-Kbit(1)
Industrial
(-40° C to 85°C)
20S2
8P3
20J
Commercial
(0° C to 70°C)
512-Kbit(1)
8P3
20J
Industrial
(-40° C to 85°C)
8P3
20J
Commercial
(0° C to 70°C)
1-Mbit(1)
2-Mbit(1)
8P3
20J
Industrial
(-40° C to 85°C)
Commercial
AT17LV002-10JC
AT17LV002-10JI
20J
20J
(0° C to 70°C)
Industrial
(-40° C to 85°C)
Notes: 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics.
2. For the -10SC and -10SI packages, customers may migrate to the AT17LVXXX-10SU.
3. For the -10TQC and -10TQI packages, customers may migrate to the AT17LVXXX-10TQU.
17
2321I–CNFG–2/08
22.2 Green Package Options (Pb/Halide-free/RoHS Compliant)
Memory Size
Ordering Code
Package
Operation Range
AT17LV256-10CU
8CN4
AT17LV256-10JU
AT17LV256-10NU
AT17LV256-10PU
AT17LV256-10SU
AT17LV512-10CU
AT17LV512-10JU
AT17LV010-10CU
AT17LV010-10JU
AT17LV010-10PU
AT17LV002-10CU
AT17LV002-10JU
AT17LV002-10SU
AT17LV002-10TQU
AT17LV040-10TQU
20J
8S1
256-Kbit(1)
8P3
20S2
8CN4
20J
512-Kbit(1)
1-Mbit(1)
Industrial
8CN4
20J
(-40° C to 85°C)
8P3
8CN4
20J
2-Mbit(1)
4-Mbit(1)
20S2
44A
44A
Note:
1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics.
18
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
23. Packaging Information
23.1 8CN4 – LAP
Marked Pin1 Indentifier
E
A
A1
D
Side View
Top View
Pin1 Corner
L1
0.10 mm
TYP
8
7
1
COMMON DIMENSIONS
(Unit of Measure = mm)
e
2
3
MIN
0.94
0.30
0.45
5.89
5.89
MAX
1.14
0.38
0.55
6.09
6.09
NOM
1.04
NOTE
1
SYMBOL
A
A1
b
0.34
6
5
0.50
b
D
5.99
4
E
5.99
e
1.27 BSC
1.10 REF
1.00
e1
L
e1
L
0.95
1.25
1.05
1.35
1
1
Bottom View
L1
1.30
Note: 1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
2/15/08
GPC
DMH
DRAWING NO.
TITLE
REV.
8CN4, 8-lead (6 x 6 x 1.04 mm Body),
Package Drawing Contact:
packagedrawings@atmel.com
8CN4
D
Lead Pitch 1.27mm,
Leadless Array Package (LAP)
19
2321I–CNFG–2/08
23.2 8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
20
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
23.3 8S1 – SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
MAX
NOM
NOTE
SYMBOL
A1
A1
0.10
–
0.25
D
SIDE VIEW
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
TITLE
DRAWING NO.
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
C
Small Outline (JEDEC SOIC)
R
21
2321I–CNFG–2/08
23.4 20J – PLCC
PIN NO. 1
1.14(0.045) X 45˚
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
9.779
8.890
9.779
8.890
7.366
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
A1
A2
D
–
–
–
–
10.033
D1
E
–
9.042 Note 2
10.033
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
9.042 Note 2
8.382
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
20J
B
R
22
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
23.5 20S2 – SOIC
23
2321I–CNFG–2/08
23.6 44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
24
AT17LV65/128/256/512/010/002/040
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
24. Revision History
Revision Level – Release Date History
H – March 2006
I – February 2008
Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI.
Removed -10SC, 10SI, -10TQC, -10TQI, -10BJC and -10BJI
devices from ordering information.
25
2321I–CNFG–2/08
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
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Le Krebs
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-en-
Yvelines Cedex
France
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
Product Contact
Web Site
Technical Support
Sales Contact
www.atmel.com
configurator@atmel.com
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
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2321I–CNFG–2/08
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