APL1608 [ASB]
PLL Module; PLL模块
| 型号： | APL1608 |
| 厂家： | 
ADVANCED SEMICONDUCTOR BUSINESS INC. |
| 描述： | PLL Module |
| 文件： | 总1页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PlerowTM APL1608
PLL Module
Features
Description
The plerowTM PLL synthesizer module was
designed for use in wireless and wireline
systems in a wide range of frequency from
50 MHz to 6 GHz. ASB’s PLL provides ex-
ceptionally low spurious and phase noise
performance with fast locking time and low
current consumption. All products are avail-
able in a surface-mount type package.
· 5 dBm Output Level at 1608MHz
· 2nd Harmonic : < -30 dBc
· Spurious Level : < -70 dBc
· Lock Time : < 10ms
· 30 mA Current Consumption
· Dielectric Resonator
Specifications
Parameter
Frequency Range
Output Power
Unit
MHz
dBm
V
Min.
1570
4
Typical
1608
5
Max.
1645
6
More Information
Supply Voltage
4.75
5.00
25
5.25
30
Website: www.asb.co.kr
E-mail: sales@asb.co.kr
Current Consumption
Channel Step Size
2nd Harmonics
mA
kHz
dBc
dBc
ms
200
-35
-80
3
Tel: (82) 42-528-7223
Fax: (82) 42-528-7222
-30
-70
10
Spurious Level
ASB Inc., 4th Fl. Venture Town
Bldg., 367-17 Goijeong-Dong,
Seo-Gu, Daejon 302-716, Korea
Lock Time
Reference Frequency
Reference Input Level
Phase Noise (C / N)
@ 1 kHz
MHz
dBm
10
-5
0
5
-75
@ 10 kHz
@ 100 kHz
-100
dBc/Hz
-118
Output Impedance
Operating Temp. Range
Package Type & Size
50
Ω
°C
-30
25
85
mm
SMT, 19.0W×19.0L×5.8H
1) Measurement conditions are as follows: T = 25°C, VCC = 5.0 V, Freq. =1608 MHz, 50 ohm system.
Outline Drawing
Top View
Bottom View
Dimension (mm)
Pin Configuration
CLOCK
A
B
C
D
E
F
G
H
I
19.0
19.0
5.8
1
2
3
4
9
D
E
F
DATA
ENABLE
OSC IN
A
C
1.5
0.5
VCC (VCO)
1.75
1.35
15.0
0.9
13
15
RF OUT
VCP (PLL)
LOCK DETECT
Ground
I
16
H
G
Others
Tolerance: ± 0.2
B
Side View
1/1
www.asb.co.kr
12/30/2005
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