CS1616 [APEX]
Single Stage Dimmable Offline AC/DC Controller for LED Lamps; 单级可调光离线式AC / DC控制器，用于LED照明
| 型号： | CS1616 |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | Single Stage Dimmable Offline AC/DC Controller for LED Lamps |
| 文件： | 总16页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS1615
CS1616
Single Stage Dimmable Offline AC/DC
Controller for LED Lamps
Features
Overview
• Best-in-class Dimmer Compatibility
- Leading-edge (TRIAC) Dimmers
- Trailing-edge Dimmers
- Digital Dimmers (Dimmers with an Integrated Power
Supply)
• Flicker-free Dimming
The CS1615 and CS1616 are high-performance single
stage dimmable offline AC/DC controllers. The CS1615/16
is a cost-effective solution that provides unmatched single-
and multi-lamp dimmer-compatibility performance for
dimmable LED applications. The CS1615 is designed for
120VAC line voltage applications, and the CS1616 is
designed for 230VAC line voltage applications.
• 0% to 100% Smooth Dimming
• Primary-side Regulation (PSR)
Across a broad range of dimmers, the CS1615/16 provides
smooth flicker free dimming, and consistently dims to
nearly zero light output, which closely matches the dimming
performance of incandescent light bulbs. Cirrus Logic’s
patent pending approach to dimmer compatibility provides
full functionality on a wide range of dimmers, including
leading-edge, trailing-edge, and digital dimmers.
• Active Power Factor Correction (PFC)
- >0.9 Power Factor
• Constant-current Output
- Flyback
- Buck-boost
• Tight LED Current Regulation: Better than ±5%
• Low THD: Less Than 20%
• Up to 90% Efficiency
• Fast Startup
Applications
• Retro-fit LED Lamps
• External LED Drivers
• LED Luminaries
• IEC61000-3-2 Compliant
• Meets NEMA SSL 6 Dimming Standard
- Closely Matches Incandescent S-curve
• Protection Features
• Commercial Lighting
- Output Open Circuit
- Output Short Circuit
- External Overtemperature Using NTC
Ordering Information
See page 14.
L1
D4
T1
Vrect
LED+
C6
R6
C5
C7
R4
R5
LED-
VAUX
D3
R2
R3
D5
2
IAC
BR1
R1
AC
Mains
BR1
D2
Q1
CS1615/16
Q3
13
11
5
GD
SOURCE
VAUX
Q2
R7
C1
C2
FBSENSE
FBAUX
eOTP
D1
16
10
14
C8
BR1
BR1
VDD
SGND CTRL1 CTRL2 GND
12
RS
C3
C4
Z1
4
8
9
RSense
R8
NTC
RCTRL1 RCTRL2
Cirrus Logic, Inc.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2013
JUN’13
DS961F1
(All Rights Reserved)
CS1615/16
1. INTRODUCTION
VDD
Voltage
Regulator
14
VDD
13
12
GD
VDD(on)
VDD(off)
POR
+
-
VZ
GND
Blank
OLP
3
Iref
-
+
15k
VOLP(th )
2
ADC
IAC
OCP
+
-
VOCP(th)
Peak
Control
+
-
11
FBSENSE
5
+
-
SOURCE
VSOURCE(th)
VPk_Max
(th )
DAC
-
+
VFSTART(th )
tVAUX
4
SGND
Output
Overvoltage
+
-
VOVP(th )
VDD
8
Zero-current
Detect
CTRL1
+
-
16
FBAUX
CLAMP
VZCD(th)
VDD
ICONNECT
10
9
MUX
eOTP
-
+
ICLAMP
CTRL2
VCONNECT(th)
3
Figure 1. CS1615/16 Block Diagram
A typical schematic using the CS1615/16 IC is shown on the
previous page.
The digital dual-mode controller is implemented with peak-
current mode primary-side regulation, which eliminates the need
for additional components to provide feedback from the
secondary and reduces system cost and complexity. Voltage
across a user-selected resistor is sensed through pin FBSENSE
to control the peak current of the primary-side inductor. Leading-
edge and trailing-edge blanking on pin FBSENSE prevents false
triggering. The required target LED current and average flyback
transformer and buck-boost inductor input current are set by
attaching resistors RCTRL1 and RCTRL2 on pins CTRL1 and
CTRL2, respectively. The controller ensures half line-cycle
averaged constant output current.
Startup current is provided from a patent-pending, external, high-
voltage source-follower network. In addition to providing startup
current, this unique topology is integral in providing compatibility
with digital dimmers by ensuring VDD power is always available
to the IC. During normal operation, an auxiliary winding on the
flyback transformer or buck-boost inductor back-biases the
source-follower circuit and provides steady-state operating
current to the IC to improve system efficiency.
Rectified input voltage Vrect is sensed as a current into pin IAC
and is used to control the adaptive dimmer-compatibility
algorithm and to extract the phase of the input voltage for output
dimming control. The SOURCE pin is used to provide a control
signal for the high-voltage source-follower circuit during Leading-
edge Mode and Trailing-edge Mode; it also provides the current
during startup.
Pin FBAUX is used for zero-current detection to ensure
quasi-resonant switching of the single stage output. When an
external negative temperature coefficient (NTC) thermistor is
connected to pin eOTP, the CS1615/16 monitors the system
temperature, allowing the controller to reduce the output current
of the system. If the temperature reaches a designated high set
point, the IC is shut down and stops switching.
2
DS961F1
CS1615/16
2. PIN DESCRIPTION
No Connect
NC
IAC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBAUX
NC
Zero-current Detect
No Connect
Rectifier Voltage Sense
Voltage Clamp Current Source
Source Ground
CLAMP
SGND
SOURCE
NC
VDD
IC Supply Voltage
Gate Drive
GD
Source Switch
GND
Ground
No Connect
FBSENSE
eOTP
CTRL2
Flyback Current Sense
No Connect
NC
External Overtemperature Protection
LED Load Current
Dimmer Hold Current
CTRL1
16-lead SOIC and TSSOP
Figure 2. CS1615/16 Pin Assignments
Pin Name
NC
Pin #
I/O
Description
No Connect — Leave pin unconnected.
1
IN
Rectifier Voltage Sense — A current proportional to the rectified line voltage is fed
into this pin. The current is measured with an A/D converter.
IAC
2
IN
Voltage Clamp Current Source — Connect to a voltage clamp circuit on the
source-switched dimmer-compatibility circuit.
CLAMP
SGND
3
4
5
OUT
PWR
IN
Source Ground — Common reference current return for the SOURCE pin.
Source Switch — Connected to the source of the source-switched external high-volt-
age FET.
SOURCE
NC
NC
6
7
IN
IN
No Connect — Connect this pin to VDD using a 47k pull-up resistor.
No Connect — Connect this pin to VDD using a 47kpull-up resistor.
Dimmer Hold Current — Connect a resistor to this pin to set the minimum input cur-
rent being pulled by the flyback/buck-boost stage.
CTRL1
CTRL2
eOTP
8
9
IN
IN
IN
LED Load Current — Connect a resistor to this pin to set the LED current.
External Overtemperature Protection — Connect an external NTC thermistor to this
pin, allowing the internal A/D converter to sample the change to NTC resistance.
10
Feedback Current Sense — The current flowing in the power FET is sensed across a
resistor. The resulting voltage is applied to this pin and digitized for use by the compu-
tational logic to determine the FET's duty cycle.
FBSENSE
11
IN
Ground — Common reference. Current return for both the input signal portion of the
IC and the gate driver.
GND
GD
12
13
PWR
OUT
Gate Drive — Gate drive for the power FET.
IC Supply Voltage — Connect a storage capacitor to this pin to serve as a reservoir
for operating current for the device, including the gate drive current to the power tran-
sistor.
VDD
14
PWR
NC
15
16
-
No Connect — Leave pin unconnected.
Zero-current Detect — Connect to the flyback/buck-boost inductor auxiliary winding
for demagnetization current zero-crossing detection.
FBAUX
IN
DS961F1
3
CS1615/16
3. CHARACTERISTICS AND SPECIFICATIONS
3.1 Electrical Characteristics
Typical characteristics conditions:
Minimum/Maximum characteristics conditions:
• TA = 25°C, VDD = 12V, GND = 0V
• TJ = -40°C to +125 °C, VDD = 11V to 17V, GND = 0V
• All voltages are measured with respect to GND.
• Unless otherwise specified, all currents are positive
when flowing into the IC.
Parameter
VDD Supply Voltage
Condition
Symbol
Min
Typ
Max
Unit
After Turn-on
VDD Increasing
VDD Decreasing
Operating Range
VDD
VST(th)
VSTP(th)
VZ
11
-
17
V
V
V
V
Turn-on Threshold Voltage
Turn-off Threshold Voltage (UVLO)
Zener Voltage
-
-
8.5
7.5
-
-
-
I
DD = 20mA
(Note 1)
(Note 2)
18.5
19.8
VDD Supply Current
Startup Supply Current
Operating Supply Current
Reference
VDD<VST(th)
IST
-
-
-
200
-
A
CL = 0.25nF, fsw 70 kHz
4.5
mA
Reference Current
CS1615
CS1616
Vrect = 200V
Iref
-
-
133
133
-
-
A
A
Vrect = 400V
Zero-current Detect
FBZCD Threshold
VFBZCD(th)
tFBZCB
IZCD
-
-
200
-
-
-
-
mV
s
FBZCD Blanking
2
ZCD Sink Current
(Note 3)
-2
-
-
mA
V
FBAUX Upper Voltage
Current Sense
IZCD = 1mA
VDD+0.6
Max Peak Control Threshold
Leading-edge Blanking
Delay to Output
VPk_Max(th)
tLEB
-
-
-
1.4
550
-
-
-
V
ns
ns
100
Pulse Width Modulator
Minimum On Time
-
-
-
-
0.55
12.8
6
-
-
-
-
s
s
Maximum On Time
Minimum Switching Frequency
Maximum Switching Frequency
Gate Driver
tFB(Min)
tFB(Max)
kHz
kHz
200
Output Source Resistance
Output Sink Resistance
Rise Time
ZOUT
ZOUT
-
-
-
-
24
11
-
-
-
CL = 0.25nF
CL = 0.25nF
30
20
ns
ns
Fall Time
-
4
DS961F1
CS1615/16
Parameter
Condition
Symbol
Min
Typ
Max
Unit
Flyback/Buck-boost Protections
Overcurrent Protection (OCP)
Overvoltage Protection (OVP)
Open Loop Protection (OLP)
(Note 4)
(Note 5)
(Note 4)
VOCP(th)
VOVP(th)
VOLP(th)
-
-
-
1.69
1.25
200
-
-
-
V
V
mV
External Overtemperature Protection (eOTP)
Pull-up Current Source – Maximum
ICONNECT
-
-
-
-
80
-
-
±5
-
A
Conductance Accuracy
(Note 6)
(Note 6)
Conductance Offset
±250
1.25
nS
V
Current Source Voltage Threshold
VCONNECT(th)
-
Internal Overtemperature Protection (iOTP)
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
(Note 7)
(Note 7)
TSD
-
-
135
14
-
-
ºC
ºC
TSD(Hy)
Notes:
1. The CS1615/16 has an internal shunt regulator that limits the voltage on the VDD pin. Shunt regulation voltage VZ is defined in
the VDD Supply Voltage section on page 4.
2. For test purposes, load capacitance CL is connected to pin GD and is equal to 0.25nF.
3. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased
does not exceed specification.
4. Protection is implemented using pin FBSENSE. See the CS1615/16 Block Diagram on page 2.
5. Protection is implemented using pin FBAUX. See the CS1615/16 Block Diagram on page 2
6. The conductance is specified in Siemens (S or 1/). Each LSB of the internal ADC corresponds to 250nS or one parallel 4M
resistor. Full scale corresponds to 256 parallel 4M resistors or 15.625k.
7. Specifications are guaranteed by design and are characterized and correlated using statistical process methods.
DS961F1
5
CS1615/16
3.2 Thermal Resistance
Symbol
Parameter
SOIC
TSSOP
Unit
Junction-to-Ambient Thermal Impedance
2 Layer PCB
4 Layer PCB
119
105
138
103
°C/W
°C/W
JA
JC
Junction-to-Case Thermal Impedance
2 Layer PCB
4 Layer PCB
50
44
44
28
°C/W
°C/W
3.3 Absolute Maximum Ratings
Characteristics conditions:
All voltages are measured with respect to GND.
Pin
Symbol
Parameter
Value
Unit
14
VDD
IC Supply Voltage
18.5
V
2,8,9,
10,11,16
Analog Input Maximum Voltage
Analog Input Maximum Current
-0.5 to (VDD+0.5)
5
V
2,8,9,
10,11,16
mA
13
13
5
VGD
IGD
Gate Drive Output Voltage
Gate Drive Output Current
-0.3 to (VDD+0.3)
-1.0 / +0.5
1.1
V
A
ISOURCE Current into Pin
A
3
ICLAMP Clamp Output Current
15
mA
mW
°C
°C
-
PD
TJ
Total Power Dissipation
400
-
Junction Temperature Operating Range
Storage Temperature Range
(Note 8)
-40 to +125
-65 to +150
-
TStg
Electrostatic Discharge Capability
Human Body Model
Charged Device Model
2000
500
V
V
All Pins
ESD
Note:
8. Long-term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at
the rate of 50mW /°C for variation over temperature.
WARNING:
Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
6
DS961F1
CS1615/16
4. TYPICAL PERFORMANCE PLOTS
8
6
3
2
1
0
4
Falling Edge
2
Rising Edge
0
-2
-50
0
50
100
150
0
2
4
6
8
10
12
14
16
18
20
Temperature (ºC)
VDD (V)
Figure 3. UVLO Characteristics
Figure 4. Supply Current vs. Voltage
10
9
20
19.5
19
Turn On
Turn Off
8
18.5
18
7
-50
0
50
100
150
-45
-20
5
25
55
85
105
125
Temperature (ºC)
Temperature (ºC)
Figure 6. Zener Voltage vs. Temperature
Figure 5. Turn On/Off Threshold Voltage vs. Temperature
0.25
-0.25
-0.75
-1.25
-1.75
-2.25
35
30
25
Source
20
15
10
Sink
5
0
-43
25
125
-45
-20
5
25
55
85
105
125
Temperature (ºC)
Temperature (°C)
Figure 8. Reference Current (Iref) Drift vs. Temperature
Figure 7. Gate Drive Resistance vs. Temperature
DS961F1
7
CS1615/16
appropriate operating mode for the IC. The dimmer switch
detection algorithm uses the input line voltage slope and dimmer
phase angle to determine the operating mode that matches the
type of dimmer switch in the system. From there on, it periodically
learns the dimmer type and can change the operating mode if the
type of dimmer switch changes.
5. GENERAL DESCRIPTION
5.1 Overview
The CS1615 and CS1616 are high-performance single stage
dimmable offline AC/DC controllers. The CS1615/16 is a cost-
effective solution that provides unmatched single- and multi-lamp
dimmer-compatibility performance for dimmable LED
applications. The CS1615 is designed for 120VAC line voltage
applications, and the CS1616 is designed for 230VAC line
voltage applications.
5.3.1.1 No-dimmer Mode
If the CS1615/16 determines that the line is not phase cut by a
dimmer switch, the IC operates the flyback/buck-boost in PFC
mode to achieve a power factor greater than 0.9 while regulating
the load current to a level set by resistor RCTRL2. In addition, a
No-dimmer Mode algorithm is applied to the source-controlled
dimmer-compatibility circuit for optimal performance, including
less than 20% of THD and highest possible overall efficiency.
Across a broad range of dimmers, the CS1615/16 provides
smooth flicker free dimming, and consistently dims to nearly zero
light output, which closely matches the dimming performance of
incandescent light bulbs. Cirrus Logic’s patent pending approach
to dimmer compatibility provides full functionality on a wide range
of dimmers, including leading-edge, trailing-edge, and digital
dimmers.
5.2 IC Startup
A high-voltage source-follower circuit is used to deliver startup
current to the IC. During steady-state operation, an auxiliary
winding on the transformer/inductor biases this circuit to an off
state to improve system efficiency, and all IC supply current is
provided from the auxiliary winding. The patent-pending
technology of the high-voltage source-follower circuit enables
system compatibility with digital dimmers (dimmers containing an
internal power supply) by providing a continuous path for the
dimmer’s power supply to recharge during its off state. During
steady-state operation, high-voltage FET Q1 in this circuit is
source-controlled by a variable internal current source on the
SOURCE pin to create the dimmer-compatibility circuit. A
Schottky diode with a forward voltage of less than 0.6V is
recommended for diode D1. Schottky diode D1 will limit inrush
current through the internal diode, preventing damage to the IC.
Figure 9. No-dimmer Mode Waveform
5.3.1.2 Leading-edge Mode
If the CS1615/16 determines that the line is phase cut by a
leading-edge dimmer switch, the IC operates the flyback/buck-
boost in Dimmer Mode and the IC sets the dimmer firing current
as well as the attach current using a source-controlled dimmer-
compatibility circuit for stable TRIAC dimmer operation.
During initial power-up, the IC executes a fast startup algorithm,
which drives the converter with peak currents that are above
normal to charge the output capacitor. Once the output capacitor
reaches a defined voltage, the IC drives the converter with
nominal peak currents until normal operation is achieved.
5.3 IC Operation
5.3.1 Dimmer Detection
The CS1615/16 dimmer switch detection algorithm determines if
a non-dimming switch, a leading-edge dimmer switch, or a
trailing-edge dimmer switch controls the solid-state lighting (SSL)
system. For each type of switch, the IC uses a different operating
mode: for a non-dimming switch, No-dimmer Mode is used; for a
leading-edge dimmer switch, Leading-edge Mode is used; for a
trailing-edge dimmer switch, Trailing-edge Mode is used. As a
result, the overall performance is optimized in terms of power
losses, efficiency, power factor, THD, and dimmer compatibility.
Figure 10. Leading-edge Mode Phase-cut Waveform
5.3.1.3 Trailing-edge Mode
If the CS1615/16 determines that the line is phase cut by a
trailing-edge dimmer switch, the IC operates the flyback/buck-
boost in Dimmer Mode. The IC charges the capacitor in the
When the IC completes UVLO, it executes in Leading-edge
Mode until the dimmer switch detection algorithm determines the
8
DS961F1
CS1615/16
dimmer switch on the falling edge of the input voltage using a
source-controlled dimmer-compatibility circuit.
5.4.1 Clamp Overpower Protection
The CS1615/16 clamp overpower protection (COP) control logic
averages the turn-on time of the clamp circuit. If the output of the
averaging logic exceeds 10%, a COP event is actuated. The
clamp circuit is disabled as well as the flyback/buck-boost
controller and the dimmer-compatibility circuit. The COP fault
state is not cleared until the power to the IC is recycled.
5.5 Dimmer Angle Extraction and the Dim
Mapping Algorithm
When operating with a dimmer, the dimming signal is extracted
in the time domain and is proportional to the conduction angle of
the dimmer. A control variable is passed to the quasi-resonant
flyback/buck-boost controller to achieve a wide range of output
currents.
Figure 11. Trailing-edge Mode Phase-cut Waveform
5.6 Dual-mode Flyback/Buck-boost
5.3.2 Switch Overpower Protection
The CS1615/16 is configurable for isolated or non-isolated
topologies using a flyback transformer or buck-boost inductor,
respectively. The CS1615/16 controls the dual-mode
flyback/buck-boost to satisfy the dimmer hold current
requirement in Dimmer Mode and provide power factor
correction in No-dimmer Mode. The dual-mode ensures a
minimum average input current greater than the required dimmer
hold current when behind a dimmer and shapes the line current
when not behind a dimmer to provide power factor correction. It
also ensures half line-cycle averaged constant output current.
To prevent excessive power dissipation on the source-switched
FET Q1, the CS1615/16 monitors voltage across FET Q1 and
current flow through FET Q1 to calculate average power
dissipation. If the calculated power exceeds the overpower
protection threshold a fault condition occurs. The IC output is
disabled and the controller attempts to restart after
approximately thirty seconds.
5.4 Voltage Clamp Circuit
To keep trailing-edge dimmer switches conducting and from
misfiring, the dimmer switch internal capacitor has to be
charged quickly around the trailing edge of the phase-cut
waveform. In addition to the dimmer compatible circuit, an
optional clamp circuit provides a high-current sinking path for
delivering the required amount of charge onto the dimmer
switch capacitor in a short amount of time.
Figure 13 illustrates the dual-mode flyback topology. The
CS1615/16 regulates output current using primary-side control,
which eliminates the need for opto-coupler feedback. The control
loop operates in peak current control mode. Demagnetization
time of the transformer is sensed by the FBAUX pin using an
auxiliary winding and is used as an input to the control loop.
The CS1615/16 provides active clamp circuitry on the CLAMP
pin, as shown in Figure 12.
D4
Vrect
T1
LED+
LED-
C6
R6
T1
Vrect
C7
C6
R6
D3
13
R4
R5
D5
CS1615/16
VAUX
D3
Q3
GD
R7
R8
R
2
Clamp
11
16
IAC
VDD
ICLAMP
FBSENSE
FBAUX
Q
C8
3
GND
12
CTRL2
9
RSense
S1
CLAMP
Q3
RCTRL2
GD 13
CS1615/16
RSense
Figure 13. Flyback Model
Figure 12. CLAMP Pin Model
DS961F1
9
CS1615/16
Figure 14 illustrates the dual-mode buck-boost topology. The
CS1615/16 regulates the output current by controlling the peak
current to ensure that the target output charge is achieved every
half line-cycle. Demagnetization time of the inductor is sensed by
the FBAUX pin using an auxiliary winding and is used as an input
to the control loop.
the target output charge is achieved every half line-cycle, thus
regulating the output current.
5.6.3 Input Current Shaping
The CS1615/16 shapes the input current by controlling the peak
primary current and the flyback/buck-boost switching frequency.
It shapes the currents differently when behind a dimmer
compared to when not behind a dimmer.
Vrect
LED-
5.6.3.1 Operation Behind a Dimmer
C7
L2
Operating behind a dimmer, the CS1615/16 controls the
switching frequency to ensure that the average input current is
greater than the dimmer hold current requirement. The dimmer
hold current level is sensed using resistor RCTRL1 on pin CTRL1,
which is sampled periodically by an ADC. The value of this
resistor can be determined using the formula shown in
Equation 2.
D4
LED+
CS1615/16
D5
Q3
13
11
16
R7
GD
FBSENSE
FBAUX
VAUX
1.4V 4M
-----------------------------------------------------------
=
RCTRL1
[Eq.2]
GND
12
CTRL2
9
RSense
511 IINCC RSense
R8
C8
RCTRL2
where,
IN(CC) = constant input current used when designing circuit
Sense = resistor attached to pin FBSENSE
I
Figure 14. Buck-boost Model
R
5.6.1 Primary-Side Current Control
5.6.3.2 Operation in No-dimmer Mode
All input current shaping and output power transfer is attained
using a peak current control algorithm. Demagnetization time of
the primary inductor is sensed by the FBAUX pin using an
auxiliary winding and is used as an input to the control algorithm.
The values obtained from resistors RCTRL1 and RCTRL2 are the
other inputs to the control algorithm that help shape the input
current and control the LED current, respectively.
Operating in No-dimmer Mode, the CS1615/16 controls the
switching frequency to ensure that the average input current
follows the line voltage to provide power factor correction. In No-
dimmer Mode the controller is designed to operate in quasi-
resonant mode to improve efficiency.
5.6.4 Max Primary-side Switching Current
Maximum primary-side switching current IPK(max) is set using
resistor RSense connected to pin FBSENSE of the CS1615/16.
The maximum primary-side switching current can be calculated
using Equation 3.
5.6.2 Output Current Regulation
The CS1615/16 regulates output current by controlling the
charge transferred over a half line-cycle. The full-scale output
current target is set using resistor RCTRL2, which is connected on
pin CTRL2. This pin is sampled periodically by an ADC. The
value of this resistor can be determined using Equation 1.
1.4
------------------
=
IPKmax
[Eq.3]
RSense
5.6.5 Auxiliary Winding Configuration
1.4V N 4M
1.25 511 RSense IOUT
-----------------------------------------------------------------------
=
RCTRL2
[Eq.1]
The auxiliary winding is used for zero-current detection (ZCD),
overvoltage protection (OVP), fast startup, and the steady-state
power supply. The voltage on the auxiliary winding is sensed
through pin FBAUX of the CS1615/16 for zero-current detection,
overvoltage protection, and fast startup. The auxiliary winding is
also used to provide the steady-state power supply to the
CS1615/16.
where,
N = turns ratio
OUT = current through LED at maximum output
Sense = resistor attached to pin FBSENSE
I
R
5.6.6 Output Open Circuit Protection
When designing a buck-boost topology the turns ratio N is set to
one.
Output open circuit protection and output overvoltage protection
(OVP) are implemented by monitoring the output voltage through
the transformer auxiliary winding. If the voltage on the FBAUX pin
exceeds a threshold VOVP(th) of 1.25V, a fault condition occurs.
The IC output is disabled and the controller attempts to restart
after approximately one second.
The CS1615/16 uses the value obtained from the resistor along
with the phase-cut and line-cycle period information to determine
the corresponding target full-scale output charge. The IC controls
the inductor switching frequency and peak current to ensure that
10
DS961F1
CS1615/16
of the system (and hence LED current ILED) if the temperature
exceeds 95°C. The large time constant for this filter ensures that
the dim scaling does not happen spontaneously and is not
noticeable (suppress spurious glitches). The eOTP tracking
circuit is designed to function accurately with external
capacitance up to 470pF.
5.6.7 Overcurrent Protection
Overcurrent protection (OCP) is implemented by monitoring the
voltage across the sense resistor. If this voltage exceeds a
threshold VOCP(th) of 1.69V, a fault condition occurs. The IC
output is disabled and the controller attempts to restart after
approximately one second.
The tracking range of this resistance ADC is approximately
15.5k to 4M. The series resistor RS is used to adjust the
resistance of the NTC to fall within the ADC tracking range,
allowing the entire dynamic range of the ADC to be well used.
The CS1615/16 recognizes a resistance (RS+RNTC) equal to
20.3k which corresponds to a temperature of 95°C, as the
beginning of an overtemperature dimming event and starts
reducing the power dissipation. The output current is scaled until
the series resistance (RS+RNTC) value reaches 16.6k (125°C).
Beyond this temperature, the IC shuts down until the resistance
(RS+RNTC) rises above 19.23k. This is not a latched protection
state, and the ADC keeps tracking the temperature in this state
in order to clear the fault state once the temperature drops below
110°C.
5.6.8 Open Loop Protection
Open loop protection (OLP) and sense resistor short protection
are implemented by monitoring the voltage across the resistor. If
the voltage on pin FBSENSE does not reach the protection
threshold VOLP(th) of 200mV, the IC output is disabled, and the
controller attempts to restart after approximately one second.
5.7 Overtemperature Protection
The CS1615/16 incorporates internal overtemperature
protection (iOTP) and the ability to connect an external
overtemperature sense circuit for IC protection. Typically, an
NTC thermistor is used.
5.7.1 Internal Overtemperature Protection
When exiting reset, the chip enters startup and the ADC quickly
(<5ms) tracks the external temperature to check if it is below the
110°C reference code before the controller is powered up. If this
check fails, the chip will wait until this condition becomes true
before initializing the rest of the system.
Internal overtemperature protection (iOTP) is activated, and
switching is disabled when the die temperature of the devices
exceeds 135°C. There is a hysteresis of about 14°C before
resuming normal operation.
For example, a 14k (±1% tolerance) series resistor is required
to allow measurements of up to 130°C to be within the eOTP
tracking range when a 100k NTC with a Beta of 4275. If the
temperature exceeds 95°C, thermistor RNTC is approximately
6.3k and series resistor RS is 14k, so the eOTP pin has a total
resistance of 20.3k. The eOTP pin initiates protective dimming
action by reducing the power dissipation. At 125°C the thermistor
RNTC has 2.6k plus a series resistor RS equal to 14k present
a resistance of 16.6k at the eOTP pin reaching the point where
a thermal shutdown fault intervenes. The CS1615/16 will
continue to monitor pin eOTP and once the series resistor RS
plus the thermistor RNTC rises above 19.23k the device will
resume power conversion (see Figure 16).
5.7.2 External Overtemperature Protection
The external overtemperature protection (eOTP) pin is used to
implement overtemperature protection. A negative temperature
coefficient (NTC) thermistor resistive network is connected to pin
eOTP, usually in the form of a series combination of a resistor RS
and a thermistor RNTC (see Figure 15). The CS1615/16 cyclically
samples the resistance connected to pin eOTP.
CS1615/16
VDD
ICONNECT
eOTP
Control
eOTP
Comp_Out
+
-
10
VCONNECT
(th)
RS
CNTC
(Optional )
NTC
100%
50%
0
Figure 15. eOTP Functional Diagram
The total resistance on the eOTP pin gives an indication of the
temperature and is used in a digital feedback loop to adjust
current ICONNECT into the NTC and series resistor RS to maintain
a constant reference voltage VCONNECT(th) of 1.25V. Current
ICONNECT is generated from a controlled current source with a
full-scale current of 80A. When the loop is in equilibrium, the
voltage on the eOTP pin fluctuates around reference
voltage VCONNECT(th). A resistance ADC is used to generate
current ICONNECT. The ADC output is filtered to suppress noise
and compared against a reference that corresponds to 125°C. A
second low-pass filter with a time constant of two seconds filters
the ADC output and is used to scale down the internal dim level
125
25
95
Temperature (°C)
Figure 16. eOTP Temperature vs. Impedance
If the external overtemperature protection feature is not required,
connect the eOTP pin to GND using a 50k-to-500k resistor to
disable the eOTP feature.
DS961F1
11
CS1615/16
6. PACKAGE DRAWING
16-PIN TSSOP (173 MIL BODY)
F
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BBB $
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$ # "
mm
NOM
- -
inch
NOM
- -
Dimension
MIN
- -
MAX
1.20
0.15
0.30
0.20
5.10
MIN
- -
MAX
0.047
0.006
0.012
0.008
0.201
A
A1
b
0.05
0.19
0.09
4.90
- -
0.002
0.007
0.004
0.193
- -
- -
- -
C
- -
- -
D
5.00
0.197
E
6.40 BSC
4.40
0.252 BSC
0.173
E1
e
4.30
4.50
0.169
0.177
0.65 BSC
0.60
0.026 BSC
0.024
L
0.45
0°
0.75
8°
0.018
0°
0.030
8°
Θ
- -
- -
aaa
bbb
ddd
0.10
0.004
0.10
0.004
0.20
0.008
1. Controlling dimensions are in millimeters.
2. Dimensioning and tolerances per ASME Y14.5M.
3. This drawing conforms to JEDEC outline MO-153, variation AB.
4. Recommended reflow profile is per JEDEC/IPC J-STD-020.
12
DS961F1
CS1615/16
16-PIN SOICN (150 MIL BODY)
mm
NOM
- -
inch
Dimension
MIN
- -
MAX
1.75
0.25
0.51
0.25
MIN
- -
NOM
- -
MAX
0.069
0.010
0.020
0.010
A
A1
b
0.10
0.31
0.10
- -
0.004
0.012
0.004
- -
- -
- -
c
- -
- -
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
- -
0.390 BSC
0.236 BSC
0.154 BSC
0.050 BSC
- -
E
E1
e
L
0.40
0°
1.27
8°
0.016
0°
0.050
8°
Θ
- -
- -
aaa
bbb
ddd
0.10
0.004
0.010
0.010
0.25
0.25
Notes: 1. Controlling dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M.
3. This drawing conforms to JEDEC outline MS-012, variation AC for standard 16 SOICN narrow body.
4. Recommended reflow profile is per JEDEC/IPC J-STD-020.
DS961F1
13
CS1615/16
7. ORDERING INFORMATION
Ordering Number
CS1615-FSZ
CS1615-FSZR
CS1616-FSZ
CS1616-FSZR
CS1615-FZZ
Container
Bulk
AC Line Voltage
Temperature
Package
120VAC
-40 °C to +125 °C
16-lead SOICN, Lead (Pb) Free
16-lead SOICN, Lead (Pb) Free
16-lead TSSOP, Lead (Pb) Free
16-lead TSSOP, Lead (Pb) Free
Tape & Reel
Bulk
230VAC
120VAC
230VAC
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
Tape & Reel
Bulk
CS1615-FZZR
CS1616-FZZ
Tape & Reel
Bulk
CS1616-FZZR
Tape & Reel
8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
a
b
Part Number
CS1615-FSZ
CS1616-FSZ
CS1615-FZZ
CS1616-FZZ
Peak Reflow Temp
260 °C
MSL Rating
Max Floor Life
7 Days
3
3
3
3
260 °C
7 Days
260 °C
7 Days
260 °C
7 Days
a.MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
b.Stored at 30°C, 60% relative humidity.
14
DS961F1
CS1615/16
REVISION HISTORY
Revision
Date
Changes
T1
JUN 2012
JUL 2012
SEP 2012
OCT 2012
JAN 2013
APR 2013
JUN 2013
Initial release.
Corrected typographical errors.
PP1
PP2
PP3
PP4
PP5
F1
Clarified context and corrected typographical errors.
Clarified context.
Buck-boost content added, and clarified context.
Context clarification.
Final release
DS961F1
15
CS1615/16
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you
go to www.cirrus.com
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16
DS961F1
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