APW7080 [ANPEC]
4A, 26V, 380kHz, Asynchronous Step-Down Converter; 4A ， 26V ， 380kHz ，异步降压转换器
| 型号： | APW7080 |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | 4A, 26V, 380kHz, Asynchronous Step-Down Converter |
| 文件： | 总23页 (文件大小：791K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7080
4A, 26V, 380kHz, Asynchronous Step-Down Converter
General Description
Features
·
·
·
Wide Input Voltage from 4.5V to 26V
The APW7080 is a 4A, asynchronous, step-down converter
with integrated 80mW P-channel MOSFET. The device,
with current-mode control scheme, can convert 4.5~26V
Output Current up to 4A
Adjustable Output Voltage from 0.8V to 90%VIN
- 0.8V Reference Voltage
input voltage to the output voltage adjustable from 0.8 to
90% VIN to provide excellent output voltage regulation.
- ±2.5% System Accuracy
The APW7080 regulates the output voltage in automatic
PSM/PWM mode operation, depending on the output
current, for high efficiency operation over light to full load
current.The APW7080 is also equipped with power-on-
reset, soft-start, and whole protections (undervoltage, over
temperature, and current-limit) into a single package. In
shutdown mode, the supply current drops below 5mA.
·
·
80mW Integrated P-Channel Power MOSFET
High Efficiencyup to 91%
-Pulse-SkippingMode(PSM)/PWM ModeOperation
·
Current-Mode Operation
- Stable with Ceramic Output Capacitors
- Fast Transient Response
·
·
·
·
Power-On-Reset Monitoring
This device, available in an 8-pin SOP-8P package,
provides a very compact system solution with minimal
external components and good thermal conductance.
Fixed 380kHz Switching Frequencyin PWM Mode
Built-in Digital Soft-Start
Output Current-Limit Protection with Frequency
Foldback
100
90
·
·
·
·
·
70% Undervoltage Protection
VOUT =5V
80
Over-Temperature Protection
<5mA Quiescent Current during Shutdown
Thermal-Enhanced SOP-8P Package
Lead Free and Green Devices Available
(RoHS Compliant)
70
60
50
40
30
20
10
VOUT =3.3V
Simplified Application Circuit
0.001
10
0.1
1
0.01
Output Current, IOUT (A)
VIN
+12
C1
10mF
Applications
C2
VIN
·
·
·
·
·
·
·
LCD Monitor / TV
L1
4A
VCC
UGND
LX
C3
Set-Top Box
VOUT
+3.3V
U1
APW7080
Portable DVD
D1
C4
22mF
Wireless LAN
R1
VIN
EN
COMP
1%
FB
ADSL, Switch HUB
Notebook Computer
R2
1%
R4
C5
GND
C6
C7
(Optional)
Step-down Converters Requiring High Efficiency
and 4A Output Current
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Jun., 2008
APW7080
Ordering and Marking Information
Package Code
KA : SOP-8P
APW7080
Operating Ambient Temperature Range
Assembly Material
Handling Code
°
I : -40 to 85 C
Handling Code
Temperature Range
Package Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device
APW7080
XXXXX
APW7080 KA :
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish;
which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-
020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and
halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed
1500ppm by weight).
Pin Configuration
8
1
2
3
4
GND
FB
VIN
EN
9
LX
7
6
5
UGND
VCC
COMP
LX
SOP-8P
Top View
The Pin 5 must be connected to the Exposed Pad
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
VIN Supply Voltage (VIN to GND)
Rating
-0.3 ~ 30
Unit
VIN
V
-2 ~ VIN+0.3
-5 ~ VIN+6
-0.3 ~ 6.5
> 100ns
< 100ns
VIN > 6.2V
VLX
VCC
LX to GND Voltage
V
V
VCC Supply Voltage (VCC to GND)
£
<
VIN+0.3
VIN 6.2V
VUGND_GND
VVIN_UGND
UGND to GND Voltage
VIN to UGND Voltage
-0.3 ~ VIN+0.3
-0.3 ~ 6.5V
-0.3 ~ 20
V
V
EN to GND Voltage
V
FB, COMP to GND Voltage
Maximum Junction Temperature
-0.3 ~ VCC +0.3
150
V
°C
°C
°C
TSTG
TSDR
Storage Temperature
-65 ~ 150
260
Maximum Lead Soldering Temperature, 10 Seconds
Note 1: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device.
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Rev. A.6 - Jun., 2008
APW7080
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Junction-to-Ambient Resistance in Free Air (Note 2)
oC/W
qJA
SOP-8P
SOP-8P
50
Junction-to-Case Resistance in Free Air (Note 3)
qJC
oC/W
10
Note 2: qJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is
soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package.
Recommended Operating Conditions (Note 4)
Symbol
Parameter
Range
4.5 ~ 26
Unit
V
VIN
VIN Supply Voltage
VCC Supply Voltage
4.0 ~ 5.5
0.8 ~ 90% VIN
0 ~ 4
V
VOUT
IOUT
Converter Output Voltage
Converter Output Current
VCC Input Capacitor
V
A
0.22 ~ 2.2
0.22 ~ 2.2
-40 ~ 85
mF
mF
oC
oC
VIN-to-UGND Input Capacitor
Ambient Temperature
Junction Temperature
TA
TJ
-40 ~ 125
Note 4: Refer to the typical application circuits
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise
specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
APW7080
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
SUPPLY CURRENT
IVIN
IVIN_SD
IVCC
VIN Supply Current
VFB = 0.85V, VEN=3V, LX=Open
VEN = 0V, VIN=26V
-
-
-
-
1.0
-
2.0
5
mA
mA
VIN Shutdown Supply Current
VCC Supply Current
VEN = 3V, VCC = 5.0V, VFB=0.85V
VEN = 0V, VCC = 5.0V
0.7
-
-
mA
IVCC_SD
VCC Shutdown Supply Current
1
m
A
VCC 4.2V LINEAR REGULATOR
Output Voltage
VIN = 5.2 ~ 26V, IO = 0 ~ 8mA
IO = 0 ~ 8mA
4.0
-60
8
4.2
-40
-
4.5
0
V
Load Regulation
mV
mA
Current-Limit
VCC > POR Threshold
30
VIN-to-UGND 5.5V LINEAR REGULATOR
Output Voltage (VVIN-UGND
Load Regulation
)
VIN = 6.2 ~ 26V, IO = 0 ~ 10mA
IO = 0 ~ 10mA
5.3
-80
10
5.5
-60
-
5.7
0
V
mV
mA
Current-Limit
VIN = 6.2 ~ 26V
30
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Rev. A.6 - Jun., 2008
APW7080
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise
specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
APW7080
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
POWER-ON-RESET (POR) AND LOCKOUT VOLTAGE THRESHOLDS
VCC POR Voltage Threshold
VCC POR Hysteresis
VCC rising
VEN rising
3.7
-
3.9
0.15
2.5
4.1
-
V
V
V
V
EN Lockout Voltage Threshold
EN Lockout Hysteresis
2.3
-
2.7
-
0.2
VIN-to-UGND Lockout Voltage
Threshold
VVIN-UGND rising
-
-
3.5
0.2
-
-
V
V
VIN-to-UGND Lockout Hysteresis
REFERENCE VOLTAGE
VREF
Reference Voltage
-
0.8
-
-
V
TJ = 25oC, IOUT=0A, VIN=12V
-1.0
+1.0
TJ = -40 ~ 125oC, IOUT = 0 ~ 4A,
Output Voltage Accuracy
%
-2.5
-
+2.5
VIN = 4.5 ~ 26V
Line Regulation
Load Regulation
VIN = 4.5V to 26V, IOUT = 0A
IOUT = 0 ~ 4A
-
-
0.36
0.4
-
-
%
%
OSCILLATOR AND DUTY
FOSC Free Running Frequency
VIN = 4.5 ~ 26V
VFB = 0V
340
380
80
420
kHz
kHz
%
Foldback Frequency
-
-
-
-
-
-
Maximum Converter’s Duty Cycle
Minimum Pulse Width of LX
93
VIN = 4.5 ~ 26V
COMP = Open
200
ns
CURRENT-MODE PWM CONVERTER
Gm
Error Amplifier Transconductance
Error Amplifier DC Gain
-
60
-
400
80
-
-
-
m
A/V
dB
Current-Sense Resistance
0.12
W
P-channel Power MOSFET
Resistance
Between VIN and Exposed Pad,
TJ=25oC
-
80
100
mW
PROTECTIONS
P-channel Power MOSFET
ILIM
Peak Current
VFB falling
5.0
6.5
8.0
A
Current-limit
VUV
FB Under-Voltage Threshold
FB Under-Voltage Hysteresis
FB Under-Voltage Debounce
Over-Temperature Trip Point
Over-Temperature Hysteresis
66
-
70
40
2
74
-
%
mV
-
-
m
s
TOTP
-
150
50
-
oC
oC
-
-
SOFT-START, ENABLE AND INPUT CURRENTS
tSS
Soft-Start Interval
9
9
10.8
12
12
-
ms
ms
V
Preceding Delay before Soft-Start
EN Shutdown Voltage Threshold
EN Enable Voltage Threshold
EN Pin Clamped Voltage
10.8
VEN falling, VIN = 4 ~ 26V
VEN rising, VIN = 4 ~ 26V
IEN=10mA
0.5
-
-
-
-
2.1
17
V
12
V
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Rev. A.6 - Jun., 2008
APW7080
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise
specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
APW7080
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
SOFT-START, ENABLE, AND INPUT CURRENTS (Cont.)
P-channel Power MOSFET
VEN = 0V, VLX = 0V, VIN = 26V
-
-
4
mA
Leakage Current
IFB
IEN
FB Pin Input Current
EN Pin Input Current
VFB = 0.8V
VEN < 3V
-100
-500
-
-
+100
+500
nA
nA
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Rev. A.6 - Jun., 2008
APW7080
Typical Operating Characteristics
Reference Voltage vs. Junction Temperature
Switching Frequency vs. Junction Temperature
420
0.816
410
400
390
380
370
360
350
340
0.812
0.808
0.804
0.800
0.796
0.792
0.788
0.784
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
Junction Temperature, TJ (oC)
Junction Temperature, TJ (oC)
Output Voltage vs. Supply Voltage
Output Voltage vs. Output Current
3.36
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.24
3.36
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.24
IOUT = 1A
VIN = 12V
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage, VIN (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Output Current, IOUT (A)
Current-Limit Level (Peak Current)
vs. Junction Temperature
VIN Input Current vs. SupplyVoltage
1.6
1.4
1.2
1.0
0.8
0.6
8.0
7.5
7.0
6.5
6.0
5.5
5.0
VFB=0.85V
0.4
0.2
0.0
0
4
8
12
16
20
24
28
-50 -25
0
25
50
75 100 125 150
VIN Supply Voltage, VIN (V)
Junction Temperature, TJ (oC)
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APW7080
Typical Operating Characteristics (Cont.)
Efficiency vs. Output Current
EN Clamp Voltage vs. EN Input Current
100
90
80
70
60
50
40
30
20
10
18
16
V=5V
OUT
14
12
10
8
VOUT=3.3V
TJ=-30oC
TJ=25oC
TJ=100oC
6
4
2
0
VIN=12v, L=10mH (DCR=50mW)
C1=10mF, C4=22mF
0.001
0.01
0.1
1
10
1
10
100
1000
10000
Output Current, IOUT (A)
EN Input Current, IEN (mA)
Operating Waveforms
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10mH)
Load Transient Response
Load Transient Response
IOUT = 50mA -> 3A -> 50mA
IOUT rise/f all time=10ms
IOUT = 0.5A -> 3A -> 0.5A
IOUT rise/f all time=10ms
VOUT
VOUT
1
1
3A
3A
IL1
IL1
2
0.5A
2
0A
Ch1 : VOUT, 200mV/Div, DC,
Voltage Offset = 3.3V
Ch2 : IL1, 1A/Div, DC
Time : 50ms/Div
Ch1 : VOUT, 100mV/Div, DC,
Voltage Offset = 3.3V
Ch2 : IL1, 1A/Div, DC
Time : 50ms/Div
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Rev. A.6 - Jun., 2008
APW7080
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10mH)
Power On
Power Off
IOUT = 3A
IOUT = 3A
VIN
VIN
1
1
2
VOUT
VOUT
2
3
IL1
IL1
3
Ch1 : VIN, 5V/Div, DC
Ch2 : VOUT, 2V/Div, DC
Ch3 : IL1, 2A/Div, DC
Time : 5ms/Div
Ch1 : VIN, 5V/Div, DC
Ch2 : VOUT, 2V/Div, DC
Ch3 : IL1, 2A/Div, DC
Time : 5ms/Div
Enable Through EN Pin
Shutdown Through EN Pin
IOUT = 3A
IOUT = 3A
1
1
VEN
VEN
VOUT
VOUT
2
3
2
3
IL1
IL1
Ch1 : VEN, 5V/Div, DC
Ch2 : VOUT, 2V/Div, DC
Ch3 : IL1, 2A/Div, DC
Time : 5ms/Div
Ch1 : VEN, 5V/Div, DC
Ch2 : VOUT, 2V/Div, DC
Ch3 : IL1, 2A/Div, DC
Time : 5ms/Div
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Rev. A.6 - Jun., 2008
APW7080
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10mH)
Over Current
Short Circuit
IOUT = 1 -> 6A
VOUT is shorted to ground by a short wire
VOUT
VOUT
1
1
2
IL1
IL1
2
Ch1 : VOUT, 1V/Div, DC
Ch2 : IL1, 2A/Div, DC
Time : 50ms/Div
Ch1 : VOUT, 1V/Div, DC
Ch2 : IL1, 2A/Div, DC
Time : 50ms/Div
Switching Waveform
Switching Waveform
IOUT = 0.2A
IOUT = 3A
VLX
VLX
1
2
1
2
IL1
IL1
Ch1 : VLX, 5V/Div, DC
Ch2 : IL1, 1A/Div, DC
Time : 1.25ms/Div
Ch1 : VLX, 5V/Div, DC
Ch2 : IL1, 2A/Div, DC
Time : 1.25ms/Div
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Rev. A.6 - Jun., 2008
APW7080
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10mH)
Line Transient Response
VIN = 12V --> 24V --> 24V
VIN rise/f all time=20ms
VOUT
1
VIN
24V
12V
2
Ch1 : VOUT, 50mV/Div, DC,
Voltage Offset = 3.3V
Ch2 : VIN, 5V/Div, DC,
Voltage Offset = 12V
Time : 50ms/Div
Pin Description
PIN
NAME
FUNCTION
Power Input. VIN supplies the power (4.5V to 26V) to the control circuitry, gate driver and step-down
converter switch. Connecting a ceramic bypass capacitor and a suitably large capacitor between
VIN and GND eliminates switching noise and voltage ripple on the input to the IC.
1
VIN
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the
regulator, drive it low to turn it off. Pull up with 100kW resistor for automatic startup.
2
3
EN
Gate driver power ground of the P-channel Power MOSFET. A linear regulator regulates a 5.5V
voltage between VIN and UGND to supply power to P-channel MOSFET gate driver. Connect a
UGND
m
ceramic capacitor (1 F typ.) between VIN and UGND for noise decoupling and stability of the linear
regulator.
Bias input and 4.2V linear regulator’s output. This pin supplies the bias to some control circuits. The
4.2V linear regulator converts the voltage on VIN to 4.2V to supply the bias when no external 5V
4
VCC
m
power supply is connected with VCC. Connect a ceramic capacitor (1 F typ.) between VCC and
GND for noise decoupling and stability of the linear regulator.
5
6
LX
Power Switching Output. Connect this pin to the underside Exposed Pad.
Output of error amplifier. Connect a series RC network from COMP to GND to compensate the
regulation control loop. In some cases, an additional capacitor from COMP to GND is required for
noise decoupling.
COMP
Feedback Input. The IC senses feedback voltage via FB and regulate the voltage at 0.8V.
Connecting FB with a resistor-divider from the output set the output voltage in the range from 0.8V
to 90% VIN.
7
8
FB
GND
LX
Power and Signal Ground.
Power Switching Output. LX is the Drain of the P-channel MOSFET to supply power to the output.
The Exposed Pad provides current with lower impedance than Pin 5. Connect the pad to output LC
filter via a top-layer thermal pad on PCBs. The PCB will be a heat sink of the IC.
9
(Exposed Pad)
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Rev. A.6 - Jun., 2008
APW7080
Block Diagram
VIN
Current Sense
Amplifier
4.2V Regulator
Current
Limit
and
VCC
Power-On-Reset
VCC
POR
UVP
UG
Soft-Start
and
Fault Logic
70%VREF
Gate
Driver
Soft-Start
Inhibit
Gate
Control
UGND
LX
FB
VREF
0.8V
Error
Amplifier
Current
Compartor
COMP
EN
VIN
5.5V
Slope
Compensation
ENOK
2.5V
0.8V
Oscillator
380kHz
Over
Temperature
Protection
Enable
GND
VIN-to-UGND
Linear Regulator
FB
Typical Application Circuit
1. 4.5~26V Single Power Input Step-down Converter (with Ceramic Input/Output Capacitors)
VIN
4.5~26V
C1
10mF
C2
1mF
VIN
4
3
L1
4A
VCC
UGND
C3
1mF
9
5
LX
LX
VOUT
0.8V~90%VIN
/4A
U1
APW7080
D1
C4
22mF
R5
100kW
2
6
R1
1%
EN
VIN
7
COMP
FB
R4
GND
R2
1%
C6
C7
(Optional)
C5
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Rev. A.6 - Jun., 2008
APW7080
Typical Application Circuit (Cont.)
Recommended Feedback Compensation Network Components List:
C6
(pF)
L1
(mH)
15
C4
(mF)
22
44
22
44
22
44
22
44
22
44
22
44
22
44
22
44
22
44
C4 ESR
(mW)
R2
(kW)
10
R4
(kW)
62
VIN
(V)
VOUT
(V)
R1
(kW)
140
140
63
C7
(pF)
C5
(pF)
24
24
24
24
12
12
12
12
12
12
12
12
5
12
12
5
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
22
22
820
820
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
15
10
120
24
10
12
33
1500
1500
820
5
10
63
12
33
51
5
10
63
12
68
24
5
10
63
12
68
51
820
3.3
3.3
2
10
46.9
46.9
30
15
82
15
1000
1000
2200
2200
3300
3300
560
10
15
82
33
4.7
4.7
3.3
3.3
3.3
3.3
2.2
2.2
2.2
2.2
20
56
10
2
30
20
56
20
1.2
1.2
3.3
3.3
1.2
1.2
0.8
0.8
7.5
7.5
46.9
46.9
7.5
7.5
0
15
150
150
68
6.2
12
15
15
15
5
15
68
33
560
5
15
270
270
NC
NC
5.6
12
1500
1500
2700
2700
5
15
5
NC
NC
2.7
6.2
5
0
2. Dual Power Inputs Step-down Converter (VIN=4.5~26V)
+5V
VIN
4.5~26V
C1
10mF
D2
Schottky
Diode
C2
1mF
VIN
4
3
L1
4A
VCC
UGND
C3
1mF
9
5
LX
LX
VOUT
0.8V~90%VIN
/4A
U1
APW7080
D1
C4
22mF
R5
100kW
2
6
R1
1%
EN
VIN
7
COMP
FB
R4
GND
R2
1%
C6
C7
(Optional)
C5
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Rev. A.6 - Jun., 2008
APW7080
Typical Application Circuit (Cont.)
3. 4.5~5.5V Single Power Input Step-down Converter
VIN
4.5~5.5V
C1
10mF
C2
1mF
VIN
4
2
3
VCC
UGND
L1
4A
C3
1mF
9
5
LX
LX
VOUT
0.8V~90%VIN
/4A
U1
APW7080
R5
100kW
D1
C4
22mF
R1
1%
EN
VIN
7
6
COMP
FB
R4
GND
R2
1%
C6
C7
(Optional)
C5
4. +12V Single Power Input Step-down Converter (with Electrolytic Input/Output Capacitors)
VIN
+12V
C1
2.2mF
C8
470mF
C2
1mF
VIN
L1
10uH
4A
4
3
VCC
UGND
C3
1mF
9
5
LX
LX
VOUT
+3.3V/4A
U1
APW7080
D1
C4
470mF
(ESR=30mW)
R5
100kW
R1
46.9k
1%
2
6
EN
VIN
7
COMP
FB
R4
56k
R2
15k
1%
GND
C6
22pF
C5
4700pF
C7
33pF
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Rev. A.6 - Jun., 2008
APW7080
Typical Application Circuit (Cont.)
5. -8V Inverting Converter with 4.5~5.5V Single Power Input
VIN
4.5~5.5V
C1
10mF
R5
100kW
C2
1mF
VIN
3
2
UGND
EN
9
5
LX
LX
L1
6.8mH
4A
4
6
VCC
U1
APW7080
PGND
D1
C3
1mF
R1
90kW
7
COMP
FB
R4
39kW
R2
10kW
AGND
C6
22pF
GND
C4
22mF
C5
560pF
C7
27pF
VOUT
-8V/4A
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Rev. A.6 - Jun., 2008
APW7080
Function Description
Main Control Loop
physically close to the IC to provide good noise
decoupling. The linear regulator is not intended for
powering up any external loads. Do not connect any
external loads to VCC. The linear regulator is also
equipped with current-limit protection to protect itself dur-
ing over-load or short-circuit conditions on VCC pin.
The APW7080 is a constant frequency current mode
switching regulator. During normal operation, the internal
P-channel power MOSFET is turned on each cycle when
the oscillator sets an internal RS latch and would be turned
off when an internal current comparator (ICMP) resets
the latch. The peak inductor current at which ICMP resets
the RS latch is controlled by the voltage on the COMP pin,
which is the output of the error amplifier (EAMP). An
external resistive divider connected between VOUT and
ground allows the EAMP to receive an output feedback
voltage VFB at FB pin. When the load current increases, it
causes a slight decrease in VFB relative to the 0.8V
reference, which in turn causes the COMP voltage to in-
crease until the average inductor current matches the
new load current.
VIN-to-UGND 5.5V Linear Regulator
The built-in 5.5V linear regulator regulates a 5.5V voltage
between VIN and UGND pins to supply bias and gate
charge for the P-channel Power MOSFET gate driver. The
linear regulator is designed to be stable with a low-ESR
ceramic output capacitor of at least 0.22mF. It is also
equipped with current-limit function to protect itself
during over-load or short-circuit conditions between VIN
and UGND.
The APW7080 shuts off the output of the converters when
the output voltage of the linear regulator is below 3.5V
(typical). The IC resumes working by initiating a new soft-
start process when the linear regulator’s output voltage
is above the undervoltage lockout voltage threshold.
VCC Power-On-Reset(POR) and EN Undervoltage
Lockout
The APW7080 keeps monitoring the voltage on VCC pin
to prevent wrong logic operations which may occur when
VCC voltage is not high enough for the internal control
circuitry to operate. The VCC POR has a rising threshold
of 3.9V (typical) with 0.15V of hysteresis.
Digital Soft-Start
The APW7080 has a built-in digital soft-start to control the
output voltage rise and limit the input current surge
during start-up. During soft-start, an internal ramp,
connected to the one of the positive inputs of the error
amplifier, rises up from 0V to 1V to replace the reference
voltage (0.8V) until the ramp voltage reaches the reference
voltage.
An external undervoltage lockout (UVLO) is sensed and
programmed at the EN pin. The EN UVLO has a rising
threshold of 2.5V with 0.2V of hysteresis. The EN UVLO
should be programmed by connecting a resistive divider
from VIN to EN to GND.
After the VCC, EN, and VIN-to-UGNDvoltages exceed their
respective voltage thresholds, the IC starts a start-up
process and then ramps up the output voltage to the
setting of output voltage. Connect a RC network from EN
to GND to set a turn-on delay that can be used to sequence
the output voltages of multiple devices.
The device is designed with a preceding delay about
10.8ms (typical) before soft-start process.
Output Undervoltage Protection
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the
required regulation range. The undervoltage continually
monitors the FB voltage after soft-start is completed. If a
load step is strong enough to pull the output voltage lower
than the undervoltage threshold, the IC shuts down
converter’s output.
VCC 4.2V Linear Regulator
VCC is the output terminal of the internal 4.2V linear
regulator which is powered from VIN and provides power
to the APW7080. The linear regulator is designed to be
stable with a low-ESR ceramic output capacitor powers
the internal control circuitry. Bypass VCC to GND with a
ceramic capacitor of at least 0.22mF. Place the capacitor
The undervoltage threshold is 70% of the nominal output
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Jun., 2008
APW7080
Function Description (Cont.)
Output Undervoltage Protection (Cont.)
voltage. The undervoltage comparator has a built-in 2ms
noise filter to prevent the chips from wrong UVP shut-
down caused by noise. The undervoltage protection works
in a hiccup mode without latched shutdown. The IC will
initiate a new soft-start process at the end of the
preceeding delay.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction tempera-
ture of the APW7080. When the junction temperature ex-
ceeds TJ = +150oC, a thermal sensor turns off the power
MOSFET, allowing the devices to cool. The thermal sensor
allows the converter to start a start-up process and
regulate the output voltage again after the junction
temperature is cooled by 50oC. The OTP is designed
with a 50oC hysteresis to lower the average TJ during con-
tinuous thermal overload conditions, increasing lifetime
of the IC.
Enable/Shutdown
Driving EN to ground places the APW7080 in shutdown.
When in shutdown, the internal power MOSFET turns off,
all internal circuitry shuts down and the quiescent supply
current of VIN reduces to <1mA (typical).
Current-Limit Protection
TheAPW7080 monitors the output current, flowing through
the P-channel power MOSFET, and limits the current peak
at current-limit level to prevent loads and the IC from
damages during overload or short-circuit conditions.
FrequencyFoldback
When the output is shortened to ground, the frequency of
the oscillator will be reduced to about 80kHz. This lower
frequency allows the inductor current to safely discharge,
thereby preventing current runaway. The oscillator’s
frequency will gradually increase to its designed rate
when the feedback voltage on FB again approaches 0.8V.
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Rev. A.6 - Jun., 2008
APW7080
Application Information
Power Sequencing
VIN
VIN
IQ1
The APW7080 can operate with sigle or dual power input(s).
In dual-power applications, the voltage (VCC) applied at
VCC pin must be lower than the voltage (VIN) on VIN pin.
The reason is the internal parasitic diode from VCC to VIN
will conduct due to the forward-voltage between VCC and
VIN. Therefore, VIN must be provided before VCC.
CIN
Q1
IOUT
IL
LX
VOUT
L
ESR
COUT
ICOUT
D1
Setting Output Voltage
The regulated output voltage is determined by:
T=1/FOSC
R1
VOUT = 0.8 ×(1+
)
(V)
R2
VLX
Suggested R2 is in the range from 1K to 20kW. For
portable applications, a 10kW resistor is suggested for
R2. To prevent stray pickup, locate resistors R1 and R2
close to APW7080.
DT
I
IOUT
IL
IOUT
Input Capacitor Selection
IQ1
It is necessary to turn on the P-channel power MOSFET
(Q1) each time when using small ceramic capacitors for
high frequency decoupling and bulk capacitors to sup-
ply the surge current. Place the small ceramic capcaitors
physically close to the VIN and between VIN and the an-
ode of the Schottky diode (D1)
I
ICOUT
VOUT
VOUT
Figure 1 Converter Waveforms
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and
current ratings above the maximum input voltage and
largest RMS current required by the circuit. The capacitor
voltage rating should be at least 1.25 times greater than
the maximum input voltage and a voltage rating of 1.5
Output Capacitor Selection
An output capacitor is required to filter the output and
supply the load transient current. The filtering requirements
are the function of the switching frequency and the ripple
current (DI). The output ripple is the sum of the voltages,
having phase shift, across the ESR and the ideal output
capacitor. The peak-to-peak voltage of the ESR is calcu-
lated as the following equations:
times is a conservative guideline. The RMS current (IRMS
)
of the bulk input capacitor is calculated as the following
equation:
VOUT + VD
........... (1)
IRMS =IOUT × D×(1-D)
(A)
D =
VIN + VD
where D is the duty cycle of the power MOSFET.
VOUT ·(1-D)
........... (2)
........... (3)
DI =
FOSC ·L
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current
rating.
VESR = DI·ESR
(V)
where VD is the forward voltage drop of the diode.
The peak-to-peak voltage of the ideal output capacitor is
calculated as the following equation:
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Jun., 2008
APW7080
Application Information (Cont.)
Output Capacitor Selection (Cont.)
and greater core losses. A reasonable starting point for
setting ripple current is DI £ 0.4 × IOUT(MAX) . Remember, the
maximum ripple current occurs at the maximum input
voltage. The minimum inductance of the inductor is
calculated by using the following equation:
D I
........... (4)
DVCOUT =
(V)
8×FOSC ×COUT
For the applications using bulk capacitors, the DVCOUT
is much smaller than the VESR and can be ignored.
Therefore, the AC peak-to-peak output voltage (DVOUT ) is
shown below:
VOUT ·(VIN - VOUT)
£ 1.2
380000 ·L ·VIN
........... (5)
DVOUT = D I×ESR
(V)
VOUT ·(VIN - VOUT)
........... (6)
L ³
(H)
For the applications using ceramic capacitors, the VESR is
much smaller than the DVCOUT and can be ignored.
Therefore, the AC peak-to-peak output voltage (DVOUT ) is
456000 ·VIN
V
= V
where
IN
IN(MAX)
Output Diode Selection
close to DVCOUT
.
The Schottky diode carries load current during the off-time.
The average diode current is therefore dependent on the
P-channel power MOSFET duty cycle.At high input voltages
the diode conducts most of the time. As VIN approaches
VOUT the diode conducts only a small fraction of the time.
The most stressful condition for the diode is when the
output is short-circuited. Therefore, it is important to
adequately specify the diode peak current and average
power dissipation so as not to exceed the diode ratings.
The load transient requirements are a function of the
slew rate (di/dt) and the magnitude of the transient load
current. These requirements are generally met with a
mix of capacitors and careful layout. High frequency
capacitors initially supply the transient and slow the
current load rate seen by the bulk capacitors. The bulk
filter capacitor values are generally determined by the ESR
(Effective Series Resistance) and voltage rating require-
ments rather than actual capacitance requirements.
Under normal load conditions, the average current
conducted by the diode is:
High frequency decoupling capacitors should be placed
as close to the power pins of the load as physically
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
capacitor’s ESR value is related to the case size with lower
ESR available in larger case sizes. However, the
Equivalent Series Inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness
of the capacitor to high slew-rate transient loading.
VIN - VOUT
ID =
×IOUT
VIN + VD
The APW7080 is equipped with whole protections to
reduce the power dissipation during short-circuit
condition. Therefore, the maximum power dissipation of
the diode is calculated from the maximum output current
as:
PDIODE(MAX) = VD ·ID(MAX)
Inductor Value Calculation
IOUT = IOUT(MAX)
where
The operating frequency and inductor selection are
interrelated in that higher operating frequencies permit
the use of a smaller inductor for the same amount of
inductor ripple current. However, this is at the expense of
efficiency due to an increase in MOSFET gate charge
losses. The equation (2) shows that the inductance value
has a direct effect on ripple current.
Remember to keep lead length short and observe proper
grounding to avoid ringing and increased dissipation.
Accepting larger values of ripple current allows the use of
low inductances, but results in higher output voltage ripple
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Jun., 2008
APW7080
Layout Consideration
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator. In
general, interconnecting impedance should be minimized
by using short, wide printed circuit traces. Signal and
power grounds are to be kept separate and finally
combined using ground plane construction or single
point grounding. Figure 2 illustrates the layout, with bold
lines indicating high current paths. Components along
the bold lines should be placed close together. Below is
a checklist for your layout:
5. Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. The bulk capacitors C8 are
also placed near VIN. Use a wide power ground plane
to connect the C1, C8, C4, and Schottky diode to
provide a low impedance path between the com-
ponents for large and high slew rate current.
1. Begin the layout by placing the power components
first. Orient the power circuitry to achieve a clean power
flow path. If possible, make all the connections on
one side of the PCB with wide, copper filled areas.
SOP-8P
VOUT
L1
VLX
Load
GND
VIN
2. In Figure 2, the loops with same color bold lines
conduct high slew rate current. These interconnecting
impedances should be minimized by using wide and
short printed circuit traces.
GND
Figure 3 Recommended Layout Diagram
Thermal Consideration
3. Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX or others) on the PCB.
Therefore, place the feedback divider and the feed-
back compensation network close to the IC to avoid
switching noise. Connect the ground of feedback
divider directly to the GND pin of the IC using a
dedicated ground trace.
In Figure 4, the SOP-8P is a cost-effective package
featuring a small size, like a standard SOP-8, and a
bottom exposed pad to minimize the thermal resistance
of the package, being applicable to high current
applications. The exposed pad must be soldered to the
top VLX plane. The copper of the VLX plane on the Top layer
conducts heat into the PCB and air. Please enlarge the
area of VLX plan to reduces the case-to-ambient resistance
(qCA).
4. The VCC decoupling capacitor should be right next
to the VCC and GND pins. Capacitor C2 should be
connected as close to the VIN and UGND pins as
possible.
102 mil
1
2
3
4
8
+
VIN
-
7
6
5
1
VIN
SOP-8P
118 mil
C2
C3
C1 C8
5
9
L1
LX
LX
3
4
UGND
+
-
D1
C4
VCC
Load
VOUT
U1
APW7080
EN
COMP
2
6
Exposed
Pad
R1
7
FB
Top
VLX
Die
GND
R4
C5
C6
8
C7
R2
(Optional)
plane
Feedback
Divider
Compensation
Network
Ambient
Air
PCB
Figure 2 Current Path Diagram
Figure 4
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Rev. A.6 - Jun., 2008
APW7080
Package Information
SOP-8P
D
SEE VIEW
A
D1
THERMAL
PAD
°
e
b
c
GAUGE PLANE
SEATING PLANE
L
VIEW A
SOP-8P
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
1.60
MIN.
MAX.
0.063
0.006
A
0.000
0.049
0.012
0.007
0.15
A1
A2
b
0.00
1.25
0.31
0.17
0.020
0.010
0.51
0.25
c
D
0.189
0.098
0.197
0.138
4.80
2.25
5.80
3.80
2.00
5.00
3.50
6.20
4.00
3.00
D1
E
0.228
0.150
0.079
0.244
0.157
0.118
E1
E2
e
h
L
1.27 BSC
0.050 BSC
0.010
0.016
0o
0.020
0.050
8o
0.25
0.40
0o
0.50
1.27
8o
0
Note : 1. Follow JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Jun., 2008
APW7080
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
SOP- 8(P)
A
H
T1
C
d
D
W
E1
F
12.4+2.00 13.0+0.50
-0.00 -0.20
330.0±2.00 50 MIN.
1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
P0
P1
P2 D0
D1
T
A0
B0
K0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10 8.0±0.10 2.0±0.05
1.5 MIN.
6.40±0.20 5.20±0.20 2.10±0.20
(mm)
Devices Per Unit
Package Type
SOP- 8P
Unit
Quantity
Tape & Reel
2500
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Rev. A.6 - Jun., 2008
APW7080
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-
down
ts
Preheat
25
°
t 25 C to Peak
Time
Reliability Test Program
Test item
Method
Description
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
245°C, 5 sec
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Average ramp-up rate
(TL to TP)
Preheat
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
183°C
60-150 seconds
217°C
60-150 seconds
- Time (tL)
Peak/Classification Temperature (Tp)
See table 1
See table 2
Time within 5°C of actual
Peak Temperature (tp)
10-30 seconds
20-40 seconds
Ramp-down Rate
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package. Measured on the body surface.
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Jun., 2008
APW7080
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350
<2.5 mm
³ 2.5 mm
240 +0/-5°C
225 +0/-5°C
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350-2000
Volume mm3
>2000
<1.6 mm
1.6 mm – 2.5 mm
³ 2.5 mm
260 +0°C*
260 +0°C*
250 +0°C*
260 +0°C*
250 +0°C*
245 +0°C*
260 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the
stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C)
at the rated MSL level.
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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Rev. A.6 - Jun., 2008
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