APA3002 [ANPEC]
12W Stereo Class-D Audio Power Amplifier; 12W立体声D类音频功率放大器
| 型号： | APA3002 |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | 12W Stereo Class-D Audio Power Amplifier |
| 文件： | 总29页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APA3002
12W Stereo Class-D Audio Power Amplifier
Features
General Description
·
·
·
Class-D Operation with High Efficiency.
The APA3002 is a monolithic integrated circuit, which pro-
vides precise DC volume control, and a stereo Class-D
32-Step DC Volume Control With Hysteresis
9W Per Channel Output Power into 8W Load at
12V, Class-D Output
audio power amplifiers capable of producing 9W into 8W
(12V) with less than 10% THD+N. The attenuator range
of the volume control in the APA3002 is from 36dB
(VVOLUME=5V) to -40dB (VVOLUME=0V) with 32 steps. The ad-
vantage of internal gain setting can be less components
and PCB area. The circuitries of both thermal and the
over-current protections are integrated in the APA3002. It
protects the chip from being destroyed by over tempera-
ture and over current failure.
·
·
·
·
·
12W Per Channel Output into 6W Load at 12V,
Class-D Output
5V LDO Output for Powering APA4801 Head-
phone Driver
Line Output for APA4801 Headphone Driver with
DC Volume Control
Low Current Consumption in Shutdown Mode
(10mA, Typical)
To simplify the audio system design, the APA3002 com-
bines a line output for external headphone driver with
volume control and a 5V regulator for external headphone
drive, where the speaker output can be switched off by
the headphone jack’s switch pin that connects to the
APA3002’s mode pin as shown in the application circuit.
APA3002 will Auto-Recovery after Over-Current
Protection
·
·
Thermal and Over-Current Protections
TQFN7x7-48 with Thermal Pad Package
TQFP7x7-48P with Thermal Pad Package
Lead Free and Green Devices Available
(RoHS Compliant)
·
Applications
·
·
LCDTV
Active Speaker
Ordering and Marking Information
Package Code
QB: TQFN7x7-48
APA3002
QCA:TQFP7x7-48P
Operating Ambient Temperature Range
Assembly Material
Handling Code
I : -40 to 85 oC
Handling Code
TR: Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Temperature Range
Package Code
APA3002
XXXXX
APA3002 QB:
XXXXX - Date Code
XXXXX - Date Code
APA3002
XXXXX
APA3002 QCA:
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
1
www.anpec.com.tw
Rev. A.6 - Sep., 2009
APA3002
Pin Configurations
36 RCLAMP
SD
RIN-
1
2
3
4
5
6
7
8
9
SD
RIN-
1
2
3
4
5
6
7
8
9
36 RCLAMP
35 MODEOUT
35 MODEOUT
RIN+
34 MODE
RIN+
34 MODE
33 AVDD
2.5VREF
33 AVDD
2.5VREF
LIN+
LIN+
LIN-
32 RVAROUT
31 LVAROUT
30 AGND
32 RVAROUT
31 LVAROUT
30 AGND
LIN-
APA3002
APA3002
LDOREF
VREF
LDOREF
VREF
29 5VLDO
28 COSC
29 5VLDO
28 COSC
27 ROSC
26 AGND
25 LCLAMP
VARDIFF
VARDIFF
VARMAX 10
VOLUME 11
REFGND 12
27 ROSC
VARMAX 10
VOLUME 11
REFGND 12
26 AGND
25 LCLAMP
TQFN7x7-48
(TOP VIEW)
TQFP7x7-48P
(TOP VIEW)
Absolute Maximum Ratings (Note 1)
(Over operating free-air temperature range unless otherwise noted.)
Symbol
Parameter
Rating
Unit
Supply Voltage (AVDD to AGND, LPVDD to LPGND, and
RPVDD to RPGND)
VDD
-0.3 to 15
V
VMODE, VVREF, VVOLUME
VVARDIFF, VVARMAX
VSD
,
Input Voltage (MODE to AGND, VREF, VOLUME, VARDIFF,
and VARMAX to REFGND)
-0.3 to 5.5
Input Voltage (SD to AGND)
-0.3 to VDD+0.3
V
VRIN+, VRIN-,VLIN+,VLIN-
Input Voltage (RIN+, RIN-, LIN+, and LIN- to AGND)
Input Voltage (RPGND and LPGND to AGND)
Output Current (5VLDO)
-0.3 to 7
-0.3 to +0.3
I5VLDO
ILDOREF
TJ
120
mA
Output Current (LDOREF)
20
oC
oC
oC
W
W
Maximum Junction Temperature
150
-65 to +150
260
TSTG
TSDR
PD
Storage Temperature Range
Maximum Lead Soldering Temperature, 10 Seconds
Power Dissipation
Internally Limited
4
RL
Class-D Power Amplifier Minimum Load Resistance
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Copyright ã ANPEC Electronics Corp.
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www.anpec.com.tw
Rev. A.6 - Sep., 2009
APA3002
Thermal Characteristics
Symbol
Parameter
Thermal Resistance -Junction to Ambient (Note 2)
Typical Value
Unit
qJA
oC/W
TQFN7x7-48
TQFP7x7-48P
21
25
Note 2: Please refer to “Thermal Pad Consideration”. The Thermal Pad on the bottom of the IC should be soldered directly to the PCB’s
Thermal Pad area connected to the ground plan by several thermal vias, and the PCB is a 2-layer, 5-inch square area with 2oz copper
thickness.
Recommended Operating Conditions
Range
Symbol
Parameter
Unit
Min.
8.5
3.0
-
Max.
14
5.5
5.5
-
VDD
Supply Voltage
V
V
V
V
V
V
V
Volume Reference Voltage
VREF
Volume Control Pin, Input Voltage VOLUME, VARMAX, VARDIFF
SD
High-level Input Voltage
MODE
2
VIH
3.5
-
-
SD
Low-level Input Voltage
MODE
0.8
2
VIL
-
V5VLDO
-100m
VOH
High-level Output Voltage
MODEOUT sources 1mA
MODEOUT sinks 1mA
-
V
VOL
fOSC
TA
Low-level Output Voltage
Oscillator Frequency
-
+100m
275
85
V
kHz
°C
225
-40
6
Operating Free-Air Temperature
RL
Class-D Power Amplifier Minimum Load Resistance
-
W
Electrical Characteristics
VDD =12V, DGND=AGND=0V, TA= 25oC (unless otherwise noted)
APA3002
Symbol
Parameter
Supply Voltage
Test Condition
Unit
Min.
Typ.
Max.
VDD
8.5
-
-
14
V
Class-D mode, VMODE=0V, VSD =5V,
20
40
mA
no load
IDD
VDD Supply Current
VAROUT mode, VMODE=5V, VSD =5V,
no load
-
-
3
6
mA
ISD
VDD Shutdown Current
VSD = 0V
10
100
mA
CLASS-D MODE, AV=15.7dB (VOLTAGE GAIN=RATIO OF THE FILTERED OUTPUT VOLTAGE TO INPUT VOLTAGE)
-
6
-
10
7.5
12
9
-
-
-
-
THD+N = 1%, fin = 1kHz, RL = 6W
THD+N = 1%, fin = 1kHz, RL = 8W
THD+N = 10%, fin = 1kHz, RL = 6W
THD+N = 10%, fin = 1kHz, RL = 8W
PO
Output Power
W
%
-
Total Harmonic Distortion Plus
Noise
THD+N
-
0.2
-
PO= 5W, fin= 1kHz, RL = 8W
Crosstalk
PSRR
Channel Separation
-
-
90
85
-
-
dB
dB
PO= 5W, fin=1kHz, CB=1mF
RL = 8W, fin = 120Hz
Power Supply Rejection Ratio
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Sep., 2009
APA3002
Electrical Characteristics (Cont.)
VDD =12V, DGND=AGND=0V, TA= 25oC (unless otherwise noted)
APA3002
Typ.
Symbol
Parameter
Test Condition
Unit
Min.
Max.
CLASS-D MODE, AV=15.7dB (VOLTAGE GAIN=RATIO OF THE FILTERED OUTPUT VOLTAGE TO INPUT VOLTAGE)
(CONT.)
With A-Weighting Filter
PO = 5W, RL = 8W
S/N
VOS
Vn
-
-
-
85
-
-
20
-
dB
Output Offset Voltage
Noise Output Voltage
mV
RL = 8W
mV
(rms)
250
High side
Low side
Total
-
-
-
300
250
550
-
-
Power MOSFET Drain-Source
On-State Resistance
Rds(on)
IO=1A
mW
650
VAROUT OUTPUT, AV=10dB
PO
Output Power
-
-
20
25
-
-
mW
%
THD+N = 1%, fin = 1kHz, RL = 32W
THD+N = 10%, fin = 1kHz, RL = 32W
Total Harmonic Distortion Plus
Noise
THD+N
-
-
-
0.05
0.005
63
-
-
-
fin= 1kHz, RL = 32W, PO = 14mW,
VO= 1Vrms, RL=47kW, fin=1kHz
PO=14mW, RL = 32W, fin=1kHz,
CB=1mF
Crosstalk
Channel Separation
dB
CB = 1mF, RL = 32W, fin =120Hz,
VRR=0.2Vrms
PSRR
Vos
Power Supply Rejection Ratio
Output Offset Voltage
-
-
-
85
-
-
20
-
dB
mV
dB
RL = 32W
With A-Weighting Filter
PO= 20mW, RL = 32W,
S/N
80
mV
(rms)
Vn
Noise Output Voltage
-
30
-
CB = 1mF
LINEAR REGULATORS (LDO)
I5VLDO =0-100mA, VSD =5V
No load
V5VLDO
V2.5VREF
PSRR
5V LDO Regulator Output
4.5
0.45X
V5VLDO
5
5.5
0.55X
V5VLDO
V
V
0.50X
V5VLDO
2.5V Reference Voltage
Power Supply Rejection Ratio
-
73
-
dB
CB = 1mF, fin= 120Hz
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Sep., 2009
APA3002
Typical Operating Characteristics
Efficiency vs. Output Power
Efficiency vs. Output Power
100
90
100
90
80
70
60
50
80
70
60
50
40
30
20
10
0
VDD =12V
RL=8W
AV=36dB
Bead filter
AUX-0025
AES-17(20kHz)
Class-D
VDD =12V
RL=8W+33mH
AV=36dB
Bead filter
AUX-0025
AES-17(20kHz)
Class-D
40
30
20
10
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Output Power (W)
Output Power (W)
Output Power vs. Load Resistance
Output Power vs. Supply Voltage
14
12
10
8
18
16
14
12
10
8
Ci=1mF
Av=36dB
fin=1kHz
AUX-0025
AES-17
Ci=1mF
RL=8W
AV=36dB
VDD=14V
THD+N=10%
fin=1kHz
THD+N=10%
AUX-0025
AES-17 (20kHz)
Class-D
(20kHz)
Class-D
VDD=14V
THD+N=1%
THD+N=1%
6
6
VDD=8.5V
THD+N=10%
4
4
2
VDD=8.5V
THD+N=1%
2
0
6
8
10
12
14
16
9
13
14
8.5
10
11
12
Load Resistance (W)
Supply Voltage (V)
Output Power vs. Supply Voltage
THD+N vs. Output Power
18
10
1
VDD=12V
Ci=1mF
RL=6W
Av=15.7dB
AUX-0025
AES-17
(20kHz)
Class-D
Ci=1mF
RL=6W
Av=36dB
fin=1kHz
AUX-0025
16
14
12
10
8
fin=1kHz
THD+N=10%
AES-17 (20kHz)
Class-D
fin=50Hz
0.1
THD+N=1%
fin=15kHz
6
0.01
0.005
4
100m
1
10 20
10m
8.5 9
10
11
12
13
14
Supply Voltage (V)
Output Power (W)
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Sep., 2009
APA3002
Typical Operating Characteristics (Cont.)
THD+N vs. Output Power
THD+N vs. Frequency
10
1
10
R
VDD =14V
Ci=1mF
RL=8W
AV=15.7dB
AUX-0025
AES-17 (20kHz)
Class-D
VDD =14V
Ci=1mF
RL=8W
AV=15.7dB
AUX-0025
AES-17 (20kHz)
Class-D
1
fin=1kHz
0.1
PO=7W
fin=50Hz
0.1
PO=3.5W
1K
fin=15kHz
100m
0.01
PO=0.5W
100
0.005
0.01
10m
1
10 20
20
10K 20K
Frequency (Hz)
Output Power (W)
THD+N vs. Frequency
Crosstalk vs. Frequency
+0
10
VDD =14V
VDD =14V
Ci=1mF
RL=8W
PO=3.5W
AV=15.7dB
AUX-0025
AES-17 (20kHz)
Class-D
-10
Ci=1mF
RL=8W
PO=7W
AUX-0025
AES-17 (20kHz)
Class-D
-20
-30
-40
-50
-60
-70
-80
-90
-100
1
AV=36dB
0.1
AV=10.7dB
Left channel to Right channel
Right channel to Left channel
AV=20.8dB
0.01
20
100
1k
10k 20k
20
100
1k
10k20k
Frequency (Hz)
Frequency (Hz)
Noise vs. Frequency
THD+N vs. Output Power
500m
100m
10
1
VDD =12V
Ci=1mF
RL=8W
Av=15.7dB
AUX-0025
Right Channel
Left Channel
fin=1kHz
fin=50Hz
0.1
VDD =14V
Ci=1mF
RL=8W
AV=15.6dB
AUX-0025
LPF=22~22kHz
A-Weighting
Class-D
0.01
fin=20kHz
AES-17(20kHz)
Class-D
0.001
10m
20
100
1k
10k 20k
10m
100m
1
5 10
Frequency (Hz)
Output Power (W)
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Sep., 2009
APA3002
Typical Operating Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Frequency
10
10
VDD =12V
Ci=1mF
RL=8W
VDD =12V
Ci=1mF
RL=8W
AV=15.7dB
AUX-0025
AES-17(20kHz)
Class-D
PO=5W
AUX-0025
AES-17 (20kHz)
Class-D
1
1
PO=0.5W
PO=5W
AV=36dB
0.1
0.1
PO=2.5W
AV=10.7dB
AV=20.8dB
0.01
0.01
20
100
1k
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
Frequency (Hz)
Crosstalk vs. Frequency
Noise vs. Frequency
+0
500m
VDD =12V
Right Channel
Left Channel
Ci=1mF
RL=8W
-20
PO=2.5W
AV=15.7dB
AUX-0025
AES-17 (20kHz)
Class-D
-40
-60
100m
VDD =12V
Ci=1mF
RL=8W
AV=15.6dB
AUX-0025
-80
Left channel to Right channel
-100
LPF=22~22kHz
A-Weighting
Class-D
Right channel to Left channel
10m
20
-120
100
1k
10k 20k
20
100
500
10k 20k
Frequency (Hz)
Frequency (Hz)
THD+N vs. Output Power
THD+N vs. Frequency
10
1
10
1
VDD =8.5V
Ci=1mF
RL=8W
VDD =8.5V
Ci=1mF
RL=8W
AV=15.7dB
AUX-0025
AES-17(20kHz)
Class-D
AV=15.7dB
AUX-0025
AES-17 (20kHz)
fin=1kHz
Class-D
PO=2.5W
PO=0.5W
0.1
0.1
fin=50Hz
PO=1.25W
100
fin=15kHz
0.01
0.01
10m
100m
1
5
20
1k
10k 20k
Output Power (W)
Frequency (Hz)
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Sep., 2009
APA3002
Typical Operating Characteristics (Cont.)
THD+N vs. Frequency
Noise vs. Frequency
10
500m
VDD =8.5V
Ci=1mF
Right Channel
Left Channel
RL=8W
PO=2.5W
AUX-0025
AES-17 (20kHz)
Class-D
1
100m
VDD =8.5V
Ci=1mF
RL=8W
AV=36dB
0.1
AV=15.6dB
AUX-0025
LPF=22~22kHz
A-Weighting
Class-D
AV=20.8dB
1k
AV=10.7dB
100
10m
0.01
20
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Input Resistance vs. Gain
CMRR vs. Frequency
160
140
120
100
80
VDD =12V
Ci=1mF
RL=8W
VO=1V
AV=15.7dB
AUX-0025
Class-D
Class-D
-20
-30
-40
-50
60
-60
-70
40
20
0
20
100
1k
10k 20k
-50
-30
-10
10
30
50
Gain (dB)
Frequency (Hz)
FrequencyResponse
Shutdown Attenuation vs. Frequency
+40
+35
+0
-10
VDD =12V
Ci=1mF
Gain (36dB)
+150
VDD =12V
Ci=1mF
RL=8W
PO=0.75W
AUX-0025
Class-D
-20 RL=8W
-30
+100
+50
+0
PO=1W
AV=36dB
VSD=0V
AUX-0025
AES-17(20kHz)
Class-D
+30
+25
+20
+15
+10
+5
-40
Phase (36dB)
-50
-60
-70
Phase (15.7dB)
Gain (15.7dB)
-80
-90
-50
-100
-100
-110
-120
-130
-150
+0
10
100
1k
Frequency (Hz)
10k
100k
20
100
1k
Frequency (Hz)
10k 20k
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Rev. A.6 - Sep., 2009
APA3002
Typical Operating Characteristics (Cont.)
Mode Attenuation vs. Frequency
Mute Attenuation vs. Frequency
+0
-10
-20
-30
-40
-50
-60
-70
-80
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
VDD =12V
Ci=1mF
RL=8W
VDD =12V
Ci=1mF
RL=8W
PO=1W
PO=1W
Volume=0V
AUX-0025
AES-17(20kHz)
Class-D
AV=36dB
Mode=5V
AUX-0025
AES-17(20kHz)
Class-D
-100
-110
-120
-130
20
20k
10k
20
100
1k
10k 20k
100
1k
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency
Inter-modulation Performance
+0
-20
-40
+0
VDD =12V
Ci=1mF
fin=19kHz&20kHz
RL=8W
PO=1W
AV=36dB
AUX-0025
Class-D
VDD =12V
RL=8W
-10
VRR=0.5Vrms
AV=36dB
AUX-0025
AES-17(20kHz)
Class-D
-20
-30
-40
-50
-60
-70
-80
-90
-60
-80
-100
-120
VRR: Ripple Voltage on VDD
-100
-140
20
100
1k
10k 20k
50 100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency
PSRR vs. Frequency
+0
+0
T
VDD =12V
T
VDD =12V
-10
-10 No load
VRR=0.5Vrms
LDO
RL=10kW
VRR=0.5Vrms
AV=20dB
-20
-30
-40
-50
-60
-70
-80
-90
-20
-30
-40
-50
-60
-70
-80
-90
VAROUT
VRR: Ripple Voltage on VDD
VRR: Ripple Voltage on VDD
-100
-100
20
100
1k
10k 20k
20
100
1k
10k20k
Frequency (Hz)
Frequency (Hz)
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Sep., 2009
APA3002
Typical Operating Characteristics (Cont.)
THD+N vs. Output Power
THD+N vs. Frequency
10
1
10
1
VDD =12V
Ci=1mF
COUT=150mF
RL=32W
AV=10dB
LPF=80kHz
VAROUT
VDD =12V
Ci=1mF
COUT=150mF
RL=32W
AV=10dB
PO=14mW
LPF=80kHz
VAROUT
fin=20kHz
fin=50Hz
0.1
0.1
fin=1kHz
0.01
0.01
0
5m
10m 15m 20m
Output Power (W)
25m 30m
20
100
1k
10k 20k
Frequency (Hz)
Crosstalk vs. Frequency
Noise vs. Frequency
+0
100m
10m
R
VDD =12V
Ci=1mF
COUT=150mF
-10
-20 RL=32W
AV=10dB
-30
-40
-50
-60
-70
-80
PO=14mW
LPF=80kHz
VAROUT
VDD =12V
Ci=1mF
COUT=150mF
RL=32W
AV=10dB
Left channel to Right channel
Right channel to Left channel
A-weighting
VAROUT
1m
-90
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
FrequencyResponse
THD+N vs. Output Voltage
+300
10
1
+10
+9
VDD =12V
Ci=1mF
Gain
+280
+260
+240
+220
+200
+180
+160
+140
COUT=150mF
RL=10kW
AV=10dB
LPF=80kHz
VAROUT
+8
+7
+6
+5
+4
+3
+2
+1
VDD =12V
Ci=1mF
COUT=150mF
RL=32W
AV=10dB
PO=2mW
VAROUT
fin=20kHz
0.1
0.01
fin=50Hz
Phase
1k
fin=1kHz
0.001
+0
+120
0
500m
1
1.5
2
2.5
20
100
10k
200k
Output Voltage (V)
Frequency (Hz)
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APA3002
Typical Operating Characteristics (Cont.)
THD+N vs. Frequency
Crosstalk vs. Frequency
10
1
+0
TTTTT TTTT
VDD =12V
Ci=1mF
-20
COUT=150mF
RL=10kW
AV=10dB
VO=1.25V
LPF=80kHz
VAROUT
VDD =12V
Ci=1mF
-40
-60
COUT=150mF
RL=10kW
AV=10dB
VO=1.25V
LPF=80kHz
VAROUT
0.1
-80
0.01
Left channel to Right channel
-100
Right channel to Left channel
0.001
-120
20
100
1k
10k 20k
20
100
1k
10k20k
Frequency (Hz)
Frequency (Hz)
Noise vs. Frequency
FrequencyResponse
100m
+10
+9
+230
Gain
+220
+210
+200
+190
+180
+170
+160
VDD =12V
Ci=1mF
COUT=150mF
RL=10kW
AV=10dB
PO=0.18V
VAROUT
+8
+7
+6
+5
10m
VDD =12V
Ci=1mF
COUT=150mF
RL=10kW
AV=10dB
Phase
A-Weighting
VAROUT
+4
+150
1m
10
100
1k
10k
200k
20
100
1k
10k20k
Frequency (Hz)
Frequency (Hz)
Input Resistance vs. Gain
Supply Current vs. Output Power
1.2
1.0
0.8
0.6
0.4
0.2
160
RL=8W&33mH
fin=1kHz
Ci=1mF
Mono
AUX-0025
AES-17 (20kHz)
VAROUT
VDD=12V
140
120
100
80
VDD=14V
VDD=8.5V
60
40
20
0
0
-60
-45
-30
-15
0
15
30
0
2
4
6
8
10
12
Gain (dB)
Output Power (W)
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Rev. A.6 - Sep., 2009
APA3002
Typical Operating Characteristics (Cont.)
SupplyCurrent vs. Supply Voltage
30
No Load
25
20
15
10
5
0
5
10
15
0
Supply Voltage (V)
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Rev. A.6 - Sep., 2009
APA3002
Pin Description
PIN
I/O
FUNCTION
NO.
NAME
Shutdown mode control signal input. Pulling the voltage on SD below 0.8V makes the IC enter
1
I
SD
low-power shutdown mode with 10mA (typical) IDD
.
2
3
4
5
6
7
8
RIN-
RIN+
I
I
Right channel negative input.
Right channel positive input.
2.5V reference for analog circuits.
Left channel positive input.
Left channel negative input.
2.5VREF
LIN+
O
I
LIN-
I
LDOREF
VREF
O
I
5V reference output (5V LDO), connect it to VREF pin.
Gain control section’s reference voltage input.
Input pin to set the difference in gain between the VAROUT and Class-D outputs by using the DC
voltage. Connect this pin to the ground or LDOREF when the VAROUT is not used.
9
VARDIFF
I
Input pin to set the maximum gain of VAROUT by using the DC voltage. Connect this pin to
ground or LDOREF directly when the VAROUT is not used.
10
11
12
13
VARMAX
VOLUME
REFGND
LBS-
I
1
-
Input pin to set the gain of VAROUT and Class-D outputs by using the DC voltage.
Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect
the DAC ground to this terminal.
I/O Left channel bootstrap power input for negative high-side MOSFET.
14,15,22
,23
LPVDD
-
Power supply for left channel H-bridge.
16,17
18,19
20,21
24
LOUT-
LPGND
LOUT+
LBS+
O
-
Class-D left channel negative output.
Power ground for left channel H-bridge.
Class-D left channel positive output.
O
I/O Left channel bootstrap power input for positive high-side MOSFET.
25
LCLAMP
AGND
-
-
Left channel internal voltage supply output for bootstrap capacitor.
Analog ground.
26,30
27
ROSC
I/O Voltage of ROSC pin equal 0.125VDD, current setting resistor for internal ramp generator.
I/O Charge/Discharge capacitor for generating triangle wave.
28
COSC
29
5VLDO
LVAROUT
RVAROUT
O
O
O
Internal 5V regulator output for external headphone driver used.
Left channel variable audio output, for external headphone driver.
Right channel variable audio output, for external headphone driver.
31
32
33
AVDD
-
Analog power supply (8.5 to 14V).
Control pin for amplifier operation. A logic high places the amplifier in variable output mode, and
the Class-D output will disable; a logic low places the amplifier in variable output mode (line-level
output for external amplifier) and stereo Class-D outputs.
34
MODE
I
Inverse output of MODE pin, this pin can control the external headphone driver’s (APA4801) mute
pin for changing operation from speaker operation to headphone operation. Leave this pin
unconnected when the external headphone driver is not in using.
35
MODEOUT
O
-
36
37
RCLAMP
RBS+
Right channel internal voltage supply output for bootstrap capacitor.
I/O Right channel bootstrap voltage input for positive high-side MOSFET.
38,39,46
,47
RPVDD
-
Power supply for right channel H-bridge.
40,41
42,43
44,45
48
ROUT+
RPGND
ROUT-
RBS-
O
-
Class-D right channel positive output.
Power ground for right channel H-bridge.
Class-D right channel negative output.
O
I/O Right channel bootstrap voltage input for negative high-side MOSFET.
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Rev. A.6 - Sep., 2009
APA3002
Block Diagram
RCLAMP
VOLTAGE
CLAMP
GEN.
RBS-
RPVDD
ROUT-
Gate
Drive
RIN-
RPGND
RBS+
RPVDD
De-glitch &
Modulation
Logic
Gain
Adj.
RIN+
ROUT+
Gate
Drive
RPGND
Gain
Adj.
2.5VREF
Over-Current
Protection
RVAROUT
ROSC
Thermal
Shutdown
RAMP
GEN.
Biases
&
Reference
Startup
protection
logic
COSC
VREF
AVDD
AGND
5VLDO ok
AVDD ok
VARDIFF
Gain
Control
VARMAX
VOLUME
5VLDO
REFGND
SD
5VLDO
LDOREF
TTL Input
Buffer
Gain
Adj.
LCLAMP
LBS-
VOLTAGE
CLAMP
GEN.
LPVDD
LVAROUT
LIN-
LOUT-
Gate
Drive
LPGND
LBS+
LPVDD
De-glitch &
Modulation
Logic
Gain
Adj.
LIN+
LOUT+
Gate
Drive
LPGND
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Rev. A.6 - Sep., 2009
APA3002
Operating Mode Selection Table
SD
L
MODE
Operating mode
Shutdown mode
H
L
H
Class-D operation
H
H
Class-D disable, VAROUT output.
Class-D DC Volume Control Table
GAIN
Voltage range (% of VVREF)
Increasing VVOLUME
Decreasing VVOLMUE
(dB)
(%)
(%)
-75
0 -4.5
0 -2.9
-40
-37.5
-35
4.5 -6.7
6.7 -8.9
2.9 -5.1
5.1 -7.2
8.9 -11.1
11.1 -13.3
13.3 -15.5
15.5 -17.7
17.7 -19.9
19.9 -22.1
22.1 -24.3
24.3 -26.5
26.5 -28.7
28.7 -30.9
30.9 -33.1
33.1 -35.3
35.3 -37.5
37.5 -39.7
39.7 -41.9
41.9 -44.1
44.1 -46.4
46.4 -48.6
48.6 -50.8
50.8 -53
7.2 -9.4
-32.4
-29.9
-27.4
-24.8
-22.3
-19.8
-17.2
-14.7
-12.2
-9.6
-7.1
-4.6
-2
9.4 -11.6
11.6 -13.8
13.8 -16.0
16.0 -18.2
18.2 -20.4
20.4 -22.6
22.6 -24.8
24.8 -27.0
27.0 -29.1
29.1 -31.3
31.3 -33.5
33.5 -35.7
35.7 -37.9
37.9 -40.1
40.1 -42.3
42.3 -44.5
44.5 -46.7
46.7 -48.9
48.9 -51.0
51.0 -53.2
53.2 -55.4
55.4 -57.6
57.6 -59.8
59.8 -62.0
62.0 -64.2
64.2 -66.4
66.4 -68.4
>68.6
0.5
3.1
5.6
8.1
10.7
13.2
15.7
18.3
20.8
23.3
25.9
28.4
30.9
33.5
36
53 -55.2
55.2 -57.4
57.4 -59.6
59.6 -61.8
61.8 -64
64 -66.2
66.2 -68.4
68.4 -70.6
>70.6
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Rev. A.6 - Sep., 2009
APA3002
VAROUT VOLUME Control Table
GAIN
Voltage range (% of VVREF)
Increasing VVOLUME
Decreasing VVOLMUE
(dB)
(%)
(%)
-66
0 -4.5
0 -2.9
-56
-53.5
-50.9
-48.4
-45.9
-43.3
-40.8
-38.3
-35.7
-33.2
-30.7
-28.1
-25.6
-23.1
-20.5
-18.0
-15.5
-13.0
-10.4
-7.9
4.5 -6.7
6.7 -8.9
2.9 -5.1
5.1 -7.2
8.9 -11.1
11.1 -13.3
13.3 -15.5
15.5 -17.7
17.7 -19.9
19.9 -22.1
22.1 -24.3
24.3 -26.5
26.5 -28.7
28.7 -30.9
30.9 -33.1
33.1 -35.3
35.3 -37.5
37.5 -39.7
39.7 -41.9
41.9 -44.1
44.1 -46.4
46.4 -48.6
48.6 -50.8
50.8 -53
7.2 -9.4
9.4 -11.6
11.6 -13.8
13.8 -16.0
16.0 -18.2
18.2 -20.4
20.4 -22.6
22.6 -24.8
24.8 -27.0
27.0 -29.1
29.1 -31.3
31.3 -33.5
33.5 -35.7
35.7 -37.9
37.9 -40.1
40.1 -42.3
42.3 -44.5
44.5 -46.7
46.7 -48.9
48.9 -51.0
51.0 -53.2
53.2 -55.4
55.4 -57.6
57.6 -59.8
59.8 -62.0
62.0 -64.2
64.2 -66.4
66.4 -68.4
>68.6
-5.3
-2.8
-0.3
53 -55.2
2.3
55.2 -57.4
57.4 -59.6
59.6 -61.8
61.8 -64
4.8
7.3
9.9
12.4
14.9
17.5
20.0
64 -66.2
66.2 -68.4
68.4 -70.6
>70.6
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Rev. A.6 - Sep., 2009
APA3002
Typical Application Circuits
Right
channel
SPEAKER
1nF
1nF
VDD
Bead
Bead
VDD
10mF
CBS(R-)
10nF
CBS(R+)
10nF
0.1mF
0.1mF
CCLAMP(R)
1mF
SD
RCLAMP
36
1
2
3
4
SHUTDOWN
Ci(RIN+)
RIN-
LIN-
Ci(RIN-)
1mF
MODEOUT
MODE
RIN-
MODEOUT
35
34
1mF
VDD
RIN+
MODE
CB
AVDD
2.5VREF
LIN+
0.1mF
33
1mF
1mF
10mF
1mF
RVAROUT
LVAROUT
5
6
32
31
RVAROUT
LVAROUT
Ci(LIN+)
LIN-
TOP VIEW
APA3002
Ci(LIN-)
AGND
5VLDO
COSC
LDOREF
VREF
0.1mF
30
29
28
27
26
25
7
5V
8
COSC
VARDIFF
VARMAX
50kW
RVARDIFF
9
220pF
ROSC
10
50kW
ROSC
120kW
AGND
VOLUME
REFGND
11
12
50kW
RVOLUME
LCLAMP
1mF
CCLAMP(L)
RVARMAX
0.1mF
0.1mF
10mF
CBS(L-)
10nF
10nF
VDD
AGnd
PGnd
VDD
CBS(L+)
Bead
Bead
1nF
1nF
Left
channel
SPEAKER
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
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Rev. A.6 - Sep., 2009
APA3002
Typical Application Circuits (Cont.)
Right
SPEAKER
channel
1nF
1nF
VDD
CBS(R+)
Bead
Bead
10mF
VDD
CBS(R-)
10nF
10nF
0.1mF
0.1mF
CCLAMP(R)
1mF
120kW
SD
RIN-
RIN+
RCLAMP
Control
Pin
1
2
36
SHUTDOWN
Ci(RIN+)
RIN-
LIN-
220mF
Ring
Ci(RIN-)
1mF
MODEOUT
35
34
33
1mF
VDD
1mF
MODE
3
CB
AVDD
2.5VREF
10mF
RVAROUT
4
0.1mF
1mF
1mF
Sleeve
LIN+
LIN-
Tip
1kW
5
32
31
30
29
28
27
26
25
Ci(LIN+)
Ci(LIN-)
1mF
Headphone
Jack
LVAROUT
6
TOP VIEW
APA3002
0.1mF
AGND
5VLDO
COSC
ROSC
LDOREF
VREF
7
APA4801
8
COSC
10mF
VARDIFF
VARMAX
VOLUME
REFGND
1kW
9
50kW
220pF
RVARDIFF
50kW
10
11
12
220mF
R
120kW
1mF
AGND
OSC
50kW
4.7mF
LCLAMP
RVARMAX RVOLUME
1mF
CCLAMP(L)
0.1mF
CBS(L-) 0.1mF
10nF
10nF
10mF
VDD
VDD
CBS(L+)
AGnd
PGnd
Bead
1nF
Bead
1nF
Left
channel
SPEAKER
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.6 - Sep., 2009
APA3002
Application Information
Class-D Operation
Square Wave Into the Speaker
Output = 0V
To apply the square wave into the speaker may cause the
voice coil of speaker jumps out the air gap and defaces the
voice coil. However, this depends on if the amplitude of
square wave is high enough and the bandwidth of speaker
is higher than the square wave’s frequency. For 250kHz
switching frequency, this is not an issue for the
speaker because the frequency is beyond the audio band,
and can’t significantly move the voice coil, as cone move-
ment is proportional to 1/f2 for frequency out of audio band.
OUT+
OUT-
OUT
(OUT+)-(OUT-)
IOUT
Output > 0V
Input Resistor (Ri)
OUT+
In order to achieve the 32 steps gain setting, the Ri varies
the input resistance network (Ri & Rf) of amplifier. The
input resistor’s range from the smallest to the maximum
is about 15 times, therefore, the input high-pass filter’s
low cutoff frequency will change 15 times from low to
high. The cutoff frequency can be calculated by equation
1.
OUT-
OUT
(OUT+)-(OUT-)
IOUT
Output < 0V
OUT+
Input Capacitor (Ci)
In the typical application, an input capacitor, Ci, is required
to allow the amplifier to bias the input signal to the proper
DC level for optimum operation. In this case, Ci and the
minimum input impedance Ri form a high-pass filter with
the corner frequency is determined in the following
OUT-
(OUT+)-(OUT-)
OUT
IOUT
equation:
1
fC(highpass)
=
(1)
2pRiCi
Figure1. APA3002 Output Waveform (Voltage & Current)
The value of Ci must be considered carefully because
it directly affects the low frequency performance of the
circuit. Consider the example, where Ri is 10kW and
the specification calls for a flat bass response down
to 40Hz. The equation is reconfigured as below:
The APA3002 modulation scheme is shown in Figure 1,
the outputs OUT+ and OUT- are in phase with each other
when no input signals. When output > 0V, the duty cycle
of OUT+ is greater than 50% and OUT- is less than 50%;
on the contrary, when output <0V, the duty cycle of OUT+
is less than 50% and OUT- is greater than 50%. This
method reduces the switching current across the load
and reduces the I2R loss in the load that improves the
amplifier’s efficiency.
1
Ci =
(2)
2pRifc
When the input resistance variation is considered, the Ci
is 0.40mF, so a value in the range of 0.47mF to 1.0mF
would be chosen. A further consideration for this ca-
pacitor is the leakage path from the input source
through the input network (Ri + Rf, Ci) to the load.
This modulation scheme has very short pulses across
the load. This makes the small ripple current and very
little loss on the load, and the LC filter can be eliminated
in most applications. Adding the LC filter can increase the
efficiency by filter the ripple current.
This leakage current creates a DC offset voltage at
the input to the amplifier that reduces useful headroom,
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Rev. A.6 - Sep., 2009
APA3002
Application Information (Cont.)
Input Capacitor (Ci) (Cont.)
CLAMP Capacitor (CCLAMP
)
especially in high gain applications. For this reason, a
low-leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the positive
side of the capacitor should face the amplifier input in most
applications because the DC level of the amplifiers’ inputs
is held at 2.5VREF. Please note that it is important to
confirm the capacitor polarity in the application.
These capacitors are regulated the clamp voltage of N-
channel power MOSFET’s gate voltage, ensuring the
maximum gate-to-source voltage of the MOSFET not to
exceed. 1mF/25V capacitors are recommended.
Power SupplyDecoupling (Cs)
The APA3002 is a high-performance CMOS audio amplifier
that requires adequate power supply decoupling to en-
sure the output total harmonic distortion (THD+N) is
as low as possible. Power supply decoupling also pre-
vents the oscillations being caused by long lead
length between the amplifier and the speaker.
COSC & ROSC
The Class-D amplifier’s switching frequency is deter-
mined by the component that connected to ROSC (pin)
and COSC (pin). The frequency can be calculated by the
following equation:
The optimum decoupling is achieved by using two dif-
ferent types of capacitors that target on different types of
noise on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good low
equivalent-series-resistance (ESR) ceramic capacitor,
typically is 0.1mF which is placed as close as possible
to the device VDD lead to achieve the best performance.
For filtering lower frequency noise signals, a large alu-
minum electrolytic capacitor of 10mF or greater placed near
the audio power amplifier is recommended.
6.6
fosc
=
(3)
RoscCosc
BS+ &BS- Capacitor (CBS)
Since the Full-bridge output stages are only using the N-
channel power MOSFET, the high-side MOSFET’s driver
needs bootstrap circuit to turn on the high side power
MOSFET correctly. A 10nF/35V ceramic capacitor is
recommended.
The bootstrap capacitors are like floating power supply
for high side N-channel power MOSFET gate driver. The
bootstrap capacitors hold the gate-to-source voltage high
enough to keep the high-side N-channel power MOSFET
turn-on at high side switching cycle. At the high-side turn-
on cycle, the voltage of bootstrap capacitors will decrease
through the leakage path. The bootstrap voltage can de-
crease below the minimum Vgs that required to keep the
high-side N-channel power MOSFET turn-on, if driving
into heavy clipping with a less than 50Hz sine wave. When
this occurs, the output power MOSFET becomes source-
follower and the output drops from VDD to approximately
Vclamp.
Ferrite Bead Selection
If the traces from the APA3002 to speaker are short, the
ferrite bead filters can reduce the high frequency radiated
to meet the FCC & CE’s requirements.
A ferrite that has very low impedance at low frequencies
and high impedance at high frequencies (above 1 MHz)
is recommended.
Output LC Filter
If the traces from the APA3002 to speaker are short, it
doesn’t require output filter for FCC & CE standard. Fig-
ure 2 is an example for adding the LC filter, it’s recom-
mended for the situation that the trace from amplifier to
speaker is too long, and needed to eliminate the radiated
emission or EMI.
Driving a square wave at low frequencies is not a design
consideration for majority application, so the 10nf boot-
strap capacitor is recommended. If the low frequency is a
concern, please increase the bootstrap capacitor value to
hold the gate voltage for a longer period and the voltage
drop will not occur.
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Rev. A.6 - Sep., 2009
APA3002
Application Information (Cont.)
If a DAC controls the Class-D gain is used, VREF and
REFGND should be connected to the reference voltage
for the DAC and the GND terminal of the DAC respectively.
For the DAC application, LDOREF would be left
unconnected. The reference voltage of the DAC provides
the reference to the internal gain circuitry through the
VREF input and any fluctuations in the DAC output voltage
will not affect the Class-D gain.
Output LC Filter (Cont.)
33mH
OUT+
0.1mF
0.47mF
33mH
8 W
The percentages in the “Increasing VVOLUME” of table should
be used for setting the voltages of the DAC when the
voltage on the VOLUME pin is increased. The percent-
ages in the “ decreasing VVOLUME” of the table should be
used for the DAC voltages when decreasing the voltage
on the VOLUME pin. Two lookup tables should be used
in software to control the gain based on an increase or
decrease in the desired system volume.
0.1mF
OUT-
Figure 2. LC Output Filter
DC Volume
Decreasing VVOLUME
If using an analog potentiometer to control the gain, it
should be connected between VREF and REFGND.
VREF can be connected to LDODREF or an external
3.1
voltage source, if desired. The table of “Increasing VVOLUME
”
0.5
and “Decreasing VVOLUME” in “Class-D DC Volume Control
Table” should be used to determine the point at which
gain changes depending on the direction that the poten-
tiometer is turned. If the voltage on the center tap of the
Increasing VVOLUME
-2.0
(39.7% x VVREF
)
potentiometer is increasing, the table “Increasing VVOLUME
”
1.90
1.99 2.01
2.12
(41.9% x VVREF)
(37.9% x VVREF
)
(40.1% x VVREF
)
at “Class-D DC Volume Control Table” should be refer-
enced to determine the trip points. If the voltage is
Volume’s Voltage (V)
decreasing, the trip points in the ”Decreasing VVOLUME
should be referenced.
”
Figure 3. DC Volume Control Operation (VVREF=5V)
The Class-D’s gain is determined by the voltage of VOL-
UME control pin. “Class-DDC Volume Control Table” lists
the gain in Class-D that is determined by the VOLUME
pin’s voltage (VVOLUME) in reference to the VREF’s voltage
(VVREF). The maximum voltage of VOLUME should not
exceed the VREF’s voltage.
The trip point, where the gain actually changes, is various
depending on whether the voltage on the VOLUME pin is
increasing or decreasing as a result of hysteresis about
each trip point. The hysteresis ensures that the gain con-
trol is monotonic and does not oscillate from one gain
step to another. A pictorial representation of the volume
control can be found in Figure 3. The graph focuses on
three gain steps with the trip points defined in the table
“Increasing VVOLUME” and ”Decreasing VVOLUME” of “Class-
D DC Volume Control Table” for Class-D gain. The dotted
lines represent the hysteresis about each gain step.
If the resistor divider fixed the Class-D’s gain is used,
and then the resistor divider values to center the volt-
age between the two percentage points of the table’s
column “Increasing VVOLUME” need to be calculated, see
figure 3. The resistor can be connected between VREF
and REFGND, and then VREF and LDOREF are con-
nected together.
Copyright ã ANPEC Electronics Corp.
21
www.anpec.com.tw
Rev. A.6 - Sep., 2009
APA3002
Application Information (Cont.)
DC Volume
LDO Operation
The 5VLOD terminal is the output of an internal-gener-
ated 5V power supply that is used for oscillator, pream-
plifier and DC volume control circuitry. The regulator can
be powered the external headphone amplifier like the
APA4801, or other circuitry, up to the current limit of 5VLDO
pin (on specification table). With 10mF & 0.1mF capacitors
connected to the terminal are recommended if powered
by theAPA4801; however, if there is no other larger loading,
1mF and 0.1mF are sufficient enough.
VVARDIFF(V)
VVARMAX(V)
-
-
VVOLUME
VVARDIFF
-
YES
+
Is VVARMAX>(VVOLUME
-
VAROUT s VOLUME(V) =
VVOLUME(V)-VVARDIFF(V)
VVARDIFF
)
VVOLUME(V)
NO
VAROUT s VOLUME(V) = VVARMAX(V)
Figure 4. VAROUT Volume Control Flow
ShutdownFunction
In order to reduce power consumption when not in use,
the APA3002 contains a shutdown function to externally
turn off the amplifier bias circuitry. This shutdown feature
turns the amplifier off when logic low is placed on the SD
pin for the APA3002. The trigger point between a logic
high and logic low level is typically 1.2V. It will be the best
to switch between ground and the supply voltage VDD to
provide maximum device performance. By switching the
SD pin to low level, the amplifier enters a low-consump-
tion-current state, IDD for the APA3002 is in shutdown
mode. Under normal operating, APA3002’s SD pin should
pull to a high level to keep the IC out of the shutdown
mode. The SD pin should be tied to a definite voltage to
avoid unwanted state change.
Three pins, VOLUME, VARMAX, and VARDIFF, determine
the VAROUT’s gain. The figure 4 shows the VAROUT vol-
ume control flow. All the values are DC voltage, and the
VAROUT channel gain can be determined by consulting the
table “VAROUT VOLUME Control Table”.
VARMAX
The VARMAX limits the maximum gain of VAROUT chan-
nels to avoid the un-comfortable listening of headphone.
VARDIFF
To avoid the uncomfortable listening when headphone is
plugging, the VARDIFF sets the different gain between
the Class-D and VAROUT channels. At initial (VVARDIFF=0V),
the difference gain between the Class-D and VAROUT is
16dB. When voltage of VARDIFF is increasing, the
VAROUT’s gain decreases.
Thermal Pad Consideration
The thermal pad must be connected to the ground. The
package with thermal pad of the APA3002 requires spe-
cial attention on thermal design. If the thermal design
issues are not properly addressed, the APA3002 will go
into thermal shutdown. The thermal pad on the bottom of
the APA3002 should be soldered down to a copper pad
on the circuit board. Heat can be conducted away from
the thermal pad through the copper plane to ambient. If
the copper plane is not on the top surface of the circuit
board, 10 to 16 vias of 15 mil or smaller in diameter should
be used to thermally couple the thermal pad to the bot-
tom plane. For good thermal conduction, the vias must
be plated through and solder filled. The copper plane
used to conduct heat away from the thermal pad should
MODE Operation
The mode controls the output mode of the APA3002, a
logic “HIGH” will disable the Class-D outputs; a logic
“LOW” will enable the Class-D outputs. This pin can con-
nect to the switch on the headphone jack to disable the
Class-D outputs when headphone plug is inserted. The
“Typical Application Circuit “ shows an example for this
application.
MODE_OUTOperation
The MODE_OUT is the inverting output of MODE, and it
controls the external headphone amplifier’s SD pin (like
the APA4801) for switching the Speaker mode or
headphone.
Copyright ã ANPEC Electronics Corp.
22
www.anpec.com.tw
Rev. A.6 - Sep., 2009
APA3002
Application Information (Cont.)
Thermal Pad Consideration (Cont.)
be as large as practical. If the ambient temperature is
higher than 25°C, a larger copper plane or forced-air cool-
ing will be required to keep the APA3002 junction tem-
perature below the thermal shutdown temperature
(150°C). In higher ambient temperature, higher airflow
rate and/or larger copper area will be required to keep the
IC out of thermal shutdown. See TQFP7x7-48 thermal
pad layout recommendation.
5.5mm
Via diameter
=0.3mm X16
1.7mm
4.5mm
Exposed
for thermal
PAD
Ground
plane for
Thermal
PAD
connected
Figure 5. TQFP7x7-48 thermal pad layout recommenda-
tion
Copyright ã ANPEC Electronics Corp.
23
www.anpec.com.tw
Rev. A.6 - Sep., 2009
APA3002
Package Information
TQFN7x7-48
D
A
Pin 1
A1
A3
D2
Pin 1 Corner
e
TQFN7x7-48
S
Y
M
B
O
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
0.028
0.000
MAX.
0.031
0.002
L
A
0.70
0.00
0.80
0.05
A1
A3
b
0.20 REF
0.008 REF
0.007
0.272
0.217
0.272
0.217
0.012
0.280
0.228
0.280
0.228
0.18
0.30
7.10
5.80
7.10
5.80
D
6.90
5.50
6.90
5.50
D2
E
E2
e
0.50 BSC
0.020 BSC
0.014
0.008
0.018
L
0.35
0.20
0.45
K
Note : 1. Followed from JEDEC MO-220 WKKD-4.
Copyright ã ANPEC Electronics Corp.
24
www.anpec.com.tw
Rev. A.6 - Sep., 2009
APA3002
Package Information
D
TQ
TQFP7x7-48P
D1
D2
EXPOSED
PAD
b
e
GAUGE PLANE
SEATING PLANE
L
TQFP7x7-48P
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
1.20
0.15
1.05
0.27
0.20
9.20
7.10
4.50
9.20
7.10
4.50
MIN.
MAX.
0.047
0.006
0.041
0.011
0.008
0.362
0.280
0.177
0.362
0.280
0.177
A
0.002
0.037
0.007
0.004
0.346
0.272
0.118
0.346
0.272
0.118
A1
A2
0.05
0.95
0.17
0.09
8.80
6.90
3.00
8.80
6.90
3.00
b
c
D
D1
D2
E
E1
E2
e
0.50 BSC
0.020 BSC
0.45
0o
0.75
7o
0.018
0o
0.030
7o
L
0
Note : 1. Followed from JEDEC MS-026 ABC.
2. Dimension "D1" and "E1" do not include mold protrusions.
Allowable protrusions is 0.25 mm per side. "D1" and "E1" are
maximun plasticbody size dimensions including mold mismatch.
Copyright ã ANPEC Electronics Corp.
25
www.anpec.com.tw
Rev. A.6 - Sep., 2009
APA3002
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
TQFP7x7-48P
Application
TQFN7x7-48
A
H
T1
16.4+2.00 13.0+0.50
-0.00 -0.20
P2 D0
C
d
D
W
E1
F
7.5±0.10
K0
330.0±2.00 50 MIN.
P0 P1
1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10
D1
1.5 MIN.
d
T
A0
9.4±0.20
W
B0
9.4±0.20
E1
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10 12.0±0.10 2.0±0.10
T1
1.8±0.20
F
A
H
C
D
16.4+2.00 13.0+0.50
-0.00 -0.20
330.0±2.00 50 MIN.
P0 P1
1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10
5.5±0.10
K0
P2 D0
D1
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10 12.0±0.10 2.0±0.10
1.5 MIN.
7.30±0.20 7.30±0.20 1.3±0.20
(mm)
Devices Per Unit
Package Type
TQFP7x7-48P
TQFN7x7-48
Unit
Quantity
Tape & Reel
Tape & Reel
2500
2500
Copyright ã ANPEC Electronics Corp.
26
www.anpec.com.tw
Rev. A.6 - Sep., 2009
APA3002
Taping Direction Information
TQFN7x7-48
USER DIRECTION OF FEED
TQFP7x7-48P
USER DIRECTION OF FEED
Copyright ã ANPEC Electronics Corp.
27
www.anpec.com.tw
Rev. A.6 - Sep., 2009
APA3002
Classification Profile
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Temperature min (Tsmin
)
Temperature max (Tsmax
)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
3 °C/second max.
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body Temperature
(Tp)*
See Classification Temp in table 1
20** seconds
See Classification Temp in table 2
30** seconds
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax
)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright ã ANPEC Electronics Corp.
28
www.anpec.com.tw
Rev. A.6 - Sep., 2009
APA3002
Classification Reflow Profiles
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
350
Package
Thickness
<2.5 mm
Volume mm3
<350
235 °C
220 °C
³ 2.5 mm
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
Volume mm3
Volume mm3
350-2000
260 °C
Volume mm3
<350
260 °C
260 °C
250 °C
>2000
260 °C
245 °C
245 °C
1.6 mm – 2.5 mm
³ 2.5 mm
250 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
PCT
TCT
HBM
MM
VMM≧200V
10ms, 1tr≧100mA
Latch-Up
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright ã ANPEC Electronics Corp.
Rev. A.6 - Sep., 2009
29
www.anpec.com.tw
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