2011A [ANPEC]

2.8W Mono Class D Audio Power Amplifier with AGC; 2.8W单声道D类音频功率放大器AGC
2011A
型号: 2011A
厂家: ANPEC ELECTRONICS COROPRATION    ANPEC ELECTRONICS COROPRATION
描述:

2.8W Mono Class D Audio Power Amplifier with AGC
2.8W单声道D类音频功率放大器AGC

放大器 功率放大器
文件: 总27页 (文件大小:684K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
APA2011/2011A  
2.8W Mono Class D Audio Power Amplifier with AGC  
Features  
General Description  
·
·
·
Operating Voltage: 2.4V-5.5V  
High Efficiencyup to 90%  
SupplyCurrent  
The APA2011/2011A is a mono, filter-free Class-D audio  
amplifier available in WLCSP1.5x1.5-9 or TDFN3x3-8  
package.  
IDD=3mA at VDD=5V  
IDD=2.5mA at VDD=3.6V  
Low Shutdown Current  
IDD=1mA at VDD=5V  
The default gains without the external input resistor is  
27dB. Besides, the gain can be low down by external  
input resistance. APA2011 provides an Dynamic-Range-  
Control (DRC) function, and this function can low down  
the dynamic range for large input signal. APA2011 can  
provide maximun 15dB gain control. APA2011A can pro-  
vide maximum 15dB gain decrease for non-clipping  
function, and this function can avoid output signal clipping.  
High PSRR and differential architecture provide increased  
immunity to noise and RF rectification. In addition to these  
features, a fast start-up time and small package size  
make the APA2011/2011A an ideal choice for portable  
devices.  
·
·
Output Power  
at 1%THD+N  
1.3W, at VDD=5V, RL=8W  
0.6W, at VDD=3.6V, RL=8W  
2.0W, at VDD=5V, RL=4W  
1.0W, at VDD=3.6V, RL=4W  
at 10%THD+N  
1.6W, at VDD=5V, RL=8W  
0.8W, at VDD=3.6V, RL=8W  
2.8W, at VDD=5V, RL=4W (WLCSP-9)  
2.4W, at VDD=5V, RL=4W  
The APA2011/2011A is capable of driving 1.6W at 5V or  
0.8W at 3.6V into 8W. It is also capable of driving 4W. The  
APA2011/2011A is designed with a Class-D architecture  
and operating with highly efficiency compared with Class-  
AB amplifier. It’s suitable for power sensitive application,  
such as battery-powered devices. The filter-free architec-  
ture eliminates the output filter, reduces the external com-  
ponent count, board area, and system costs, and simpli-  
fies the design.  
1.2W, at VDD=3.6V, RL=4W  
·
·
APA2011 Dynamic Range Control (DRC) Provide  
Maximum 15dB Control (2:1 Compression Ratio)  
APA2011A Non-Clip Function can Provide Maxi-  
mum 15dB Control (Gain Decreasing)  
Less External Components Required  
Fast Start-up Time (4ms)  
·
·
·
·
·
High PSRR: 70dB at 217Hz  
Moreover, the APA2011/2011A provides thermal and short  
circuit protection.  
Thermal and Over-Current Protections  
Space Saving Packages  
WLCSP1.5x1.5-9 Bump, TDFN3x3-8  
Lead Free and Green Devices Available  
(RoHS Compliant)  
Simplified Application Circuit  
·
INP  
OUTP  
Audio  
Speaker  
Audio Input  
Signals  
APA2011/2011A  
Applications  
INN  
OUTN  
·
·
·
·
Mobil Phones  
Handset  
PDAs  
Portable Multimedia Device  
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and  
advise customers to obtain the latest version of relevant information to verify before placing orders.  
Copyright ã ANPEC Electronics Corp.  
1
www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Ordering and Marking Information  
Package Code  
APA2011/2011A  
HA : WLCSP1.5x1.5-9 QB : TDFN3x3-8  
Operating Ambient Temperature Range  
I : - 40 to 85 oC  
Assembly Material  
Handling Code  
Handling Code  
Temperature Range  
Package Code  
TR : Tape & Reel  
Assembly Material  
G : Halogen and Lead Free Device  
A11  
X
APA2011 HA :  
X - Date Code  
X - Date Code  
A11A  
APA2011A HA :  
X
APA  
APA2011 QB :  
APA2011A QB :  
XXXXX - Date Code  
XXXXX - Date Code  
2011  
XXXXX  
APA  
2011A  
XXXXX  
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which  
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for  
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen  
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by  
weight).  
Pin Configuration  
OUTN  
(A3)  
PGND  
(B3)  
OUTP  
(C3)  
SD 1  
DR 2  
INP 3  
INN 4  
8 OUTN  
7 GND  
6 VDD  
A11 A11A  
X X  
GND  
(A2)  
VDD  
(B2)  
SD  
(C2)  
INP  
(A1)  
DR  
(B1)  
INN  
(C1)  
5 OUTP  
Marking  
Marking  
PIN A1  
Date Code  
TDFN3x3-8  
Top View  
WLCSP1.5x1.5-9  
Top View  
Absolute Maximum Ratings (Note 1)  
Symbol  
VPGND_GND  
VDD  
Parameter  
Rating  
Unit  
PGND to GND  
-0.3 to +0.3  
-0.3 to 6  
Supply Voltage (VDD to PGND, VDD to GND)  
Input Voltage (INN, INP to GND)  
Input Voltage (SD, DR to GND)  
Maximum Junction Temperature  
Storage Temperature Range  
V
VIN  
-0.3 to VDD+0.3  
-0.3 to VDD+0.3  
150  
VSD, VDR  
TJ  
oC  
TSTG  
-65 to +150  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Absolute Maximum Ratings (Cont.) (Note 1)  
Symbol  
Parameter  
Maximum Lead Soldering Temperature, 10 Seconds  
Power Dissipation  
Rating  
260  
Unit  
oC  
TSDR  
PD  
Internally Limited  
W
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are  
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under  
"recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods  
may affect device reliability.  
Thermal Characteristics  
Symbol  
Parameter  
Typical Value  
Unit  
Thermal Resistance -Junction to Ambient (Note 2)  
oC/W  
WLCSP1.5x1.5-9  
TDFN3x3-8  
165  
50  
qJA  
Thermal Resistance -Junction to Case (Note 3)  
qJC  
oC/W  
TDFN3x3-8  
10  
Note 2: Please refer to “ Layout Recommendation”, the Thermal Pad on the bottom of the IC should soldered directly to the PCB’s  
Thermal Pad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz  
copper thickness.  
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TDFN3x3-8 package.  
Recommended Operating Conditions  
Range  
Symbol  
Parameter  
Unit  
Min.  
2.4  
1
Max.  
5.5  
-
VDD  
VIH  
VIL  
VIC  
TA  
Supply Voltage  
High Level Threshold Voltage  
Low Level Threshold Voltage  
Common Mode Input Voltage  
Ambient Temperature Range  
Junction Temperature Range  
Speaker Resistance  
SD  
SD  
V
0.4  
VDD-1  
85  
-
-
-40  
-40  
2.8  
oC  
TJ  
125  
-
RL  
W
Electrical Characteristics  
VDD=5V, GND=0V, AV=15dB, TA=25oC (unless otherwise noted)  
APA2011/2011A  
Symbol  
Parameter  
Supply Current  
Test Conditions  
Unit  
mA  
mA  
Min.  
Typ.  
3
Max.  
6
IDD  
ISD  
-
-
Shutdown Current  
SD = 0V  
SD  
1
5
II  
Input Current  
0.1  
500  
4
1
-
FOSC  
twake-up  
Ri  
Oscillator Frequency  
Recovery Time from Shutdown  
Input Resistor  
400  
-
600  
8
kHz  
ms  
INN, INP  
23.75  
9.5  
25  
10  
26.25  
10.5  
kW  
RDR  
DR Pin Pull-high Resistor  
Static Drain-Source On-State  
Resistance  
(PMOSFET+NMOSFET)  
RDS(ON)  
VDD=5V, IL=0.8A  
WLCSP1.5x1.5-9  
780  
-
-
mW  
Copyright ã ANPEC Electronics Corp.  
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www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Electrical Characteristics (Cont.)  
VDD=5V, GND=0V, AV=15dB, TA= 25oC (unless otherwise noted)  
APA2011/2011A  
Symbol  
Parameter  
Test Conditions  
Unit  
Min.  
Typ.  
Max.  
VDD=3.6V,  
IL=0.6A  
WLCSP1.5x1.5-9  
-
-
-
-
900  
-
-
-
-
Static Drain-Source On-State  
Resistance  
(PMOSFET+NMOSFET)  
RDS(ON)  
mW  
VDD=2.4V,  
IL=0.4A  
WLCSP1.5x1.5-9  
WLCSP1.5x1.5-9  
WLCSP1.5x1.5-9  
1000  
90  
PO=1.2W,  
RL=8W+33mH  
Efficiency  
%
h
PO=2W,  
RL=4W+33mH  
82  
VDD=5V  
-
-
2.45  
2.2  
-
-
RL=3W  
RL=4W,  
WLCSP1.5x1.5-9  
THD+N=1%,  
fin=1kHz  
-
2.0  
1.3  
3.0  
-
-
-
RL=4W  
RL=8W  
RL=3W  
1
-
PO  
Output Power  
W
RL=4W,  
WLCSP1.5x1.5-9  
-
2.8  
-
THD+N=10%,  
fin=1kHz  
-
-
2.4  
1.6  
-
-
RL=4W  
RL=8W  
RL=4W  
PO=1.4W  
-
-
-
0.05  
0.04  
3
0.1  
0.1  
5
Total Harmonic Distortion Plus  
Noise  
RL=8W  
PO=0.9W  
THD+N  
fin=1kHz  
%
RL=8W  
PO=1.5W, VDR=VDD  
VOS  
Vn  
Output Offset Voltage  
Noise Output Voltage  
-
-
-
20  
mV  
RL=8W  
100  
200  
With A-weighting Filter, RL=8W  
mVrms  
With A-weighting Filter, PO=0.9W,  
RL=8W  
S/N  
Signal to Noise Ratio  
82  
89  
-
PSRR  
CMRR  
Power Supply Rejection Ratio  
Common Mode Rejection Ratio  
Shutdown Attenuation  
-
-
-
-70  
-60  
-60  
-50  
-90  
RL=8W, fin=217Hz,Vrr=0.5Vpp  
fin=1kHz, RL=8W, Vin=0.1Vpp  
fin=1kHz, RL=8W, Vin=1Vpp  
dB  
Attshutdown  
VDD=3.6V  
-100  
-
-
-
-
1.0  
0.6  
1.2  
0.8  
-
-
-
-
RL=4W  
THD+N=1%,  
fin=1kHz  
RL=8W  
PO  
Output Power  
W
%
RL=4W  
THD+N=10%,  
fin=1kHz  
RL=8W  
RL=4W  
PO=0.7W  
-
-
0.07  
0.05  
0.15  
Total Harmonic Distortion Plus  
Noise  
THD+N  
fin=1kHz  
RL=8W  
PO=0.4W  
0.1  
VOS  
Vn  
Output Offset Voltage  
Noise Output Voltage  
-
-
-
20  
mV  
RL=8W  
100  
200  
With A-weighting Filter, RL=8W  
mVrms  
Copyright ã ANPEC Electronics Corp.  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Electrical Characteristics (Cont.)  
VDD=5V, GND=0V, AV=15dB, TA= 25oC (unless otherwise noted)  
APA2011/2011A  
Symbol  
Parameter  
Test Conditions  
Unit  
Min.  
Typ.  
Max.  
VDD=3.6V (CONT.)  
With A-weighting Filter, PO=0.4W,  
RL=8W  
S/N  
Signal to Noise Ratio  
79  
85  
-
dB  
PSRR  
CMRR  
Power Supply Rejection Ratio  
Common Mode Rejection Ratio  
Shutdown Attenuation  
-
-
-
-70  
-60  
-60  
-50  
-90  
RL=8W, fin=217Hz,Vrr=0.2Vpp  
fin=1kHz, RL=8W, Vin=0.1Vpp  
fin=1kHz, RL=8W, Vin=1Vpp  
Attshutdown  
VDD=2.4V  
-100  
-
-
-
-
0.45  
0.3  
-
-
-
-
RL=4W  
THD+N=1%,  
fin=1kHz  
RL=8W  
PO  
Output Power  
W
%
0.55  
0.35  
RL=4W  
THD+N=10%,  
fin=1kHz  
RL=8W  
RL=4W  
PO=0.32W  
-
-
0.2  
0.1  
0.5  
0.3  
Total Harmonic Distortion Plus  
Noise  
THD+N  
fin=1kHz  
RL=8W  
PO=0.2W  
Vos  
Vn  
Output Offset Voltage  
Noise Output Voltage  
-
-
-
20  
mV  
RL=8W  
110  
220  
With A-weighting Filter, RL=8W  
mVrms  
With A-weighting Filter, PO=0.2W,  
RL=8W  
S/N  
Signal to Noise Ratio  
75  
81  
-
PSRR  
CMRR  
Power Supply Rejection Ratio  
Common Mode Rejection Ratio  
Shutdown Attenuation  
-
-
-
-65  
-60  
-60  
-50  
-90  
RL=8W, fin=217Hz,Vrr=0.1Vpp  
fin=1kHz, RL=8W, Vin=0.1Vpp  
fin=1kHz, RL=8W, Vin=1Vpp  
dB  
Attshutdown  
-100  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Typical Operating Characteristics  
Efficiency vs. Output Power (8W)  
Efficiency vs. Output Power (4W)  
90  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VDD=3.6V  
VDD=5V  
VDD=5V  
80  
VDD=3.6V  
70  
VDD=2.4V  
VDD=2.4V  
60  
50  
40  
RL=4W+33mH  
fin=1kHz  
Rin=75kW  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
RL=8W+33mH  
fin=1kHz  
Rin=75kW  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
30  
20  
10  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8  
Output Power (W)  
0
Output Power (W)  
Output Power vs. Load Resistance  
Output Power vs. Load Resistance  
3.0  
2.5  
2.0  
2.5  
2.0  
THD+N=1%  
fin=1kHz  
THD+N=10%  
fin=1kHz  
WLCSP1.5x1.5-9  
Rin=75kW  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
Rin=75kW  
AV=15dB  
WLCSP1.5x1.5-9  
AUX-0025  
AES-17(20kHz)  
1.5  
1.0  
0.5  
0
1.5  
1.0  
0.5  
0
VDD=5V  
VDD=5V  
VDD=3.6V  
VDD=3.6V  
VDD=2.4V  
VDD=2.4V  
TDFN3x3-8  
TDFN3x3-8  
4
8
12  
16  
20  
24  
28  
32  
4
8
12  
16  
20  
24  
28 32  
Load Resistance (W)  
Load Resistance (W)  
THD+N vs. Output Power  
THD+N vs. Output Power  
10  
1
10  
1
VDD=5.5V  
VDD=5.5V  
VDD=5V  
VDD=4.2V  
VDD=3.6V  
VDD=2.4V  
VDD=5V  
VDD=4.2V  
VDD=3.6V  
VDD=2.4V  
fin=1kHz  
fin=1kHz  
Rin=75kW  
RL=4W  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
TDFN3x3-8  
Rin=75kW  
RL=8W  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
TDFN3x3-8  
0.1  
0.1  
0.01  
0.01  
0
1
2
3
4
0
1
2
2.5  
Output Power (W)  
Output Power (W)  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Typical Operating Characteristics (Cont.)  
THD+N vs. Output Power  
THD+N vs. Output Power  
10  
1
10  
1
VDD=5.5V  
VDD=5V  
VDD=5.5V  
VDD=5V  
VDD=4.2V  
VDD=3.6V  
VDD=2.4V  
VDD=4.2V  
VDD=3.6V  
VDD=2.4V  
fin=1kHz  
fin=1kHz  
Rin=75kW  
RL=8W  
Rin=75kW  
RL=4W  
0.1  
0.1  
AV=15dB  
AV=15dB  
AUX-0025  
AUX-0025  
AES-17(20kHz)  
WLCSP1.5x1.5-9  
AES-17(20kHz)  
WLCSP1.5x1.5-9  
0.01  
0.01  
0
1
2
2.8  
0
1
2
3
4 4.5  
Output Power (W)  
Output Power (W)  
THD+N vs. Output Power  
THD+N vs. Frequency  
10  
1
10  
1
R
VDD=2.4V  
Ci=0.1mF  
Rin=75kW  
RL=8W  
VDD=5V  
DD=4.2V  
VDD=3.6V  
VDD=2.4V  
V
AV=15dB  
AUX-0025  
AES-17(20kHz)  
PO=0.2W  
fin=1kHz  
Rin=75kW  
RL=3W  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
WLCSP1.5x1.5-9  
0.1  
0.1  
0.01  
PO=0.1W  
0.01  
3
4
5
20  
100  
1k  
10k 20k  
0
1
2
Frequency (Hz)  
Output Power (W)  
THD+N vs. Frequency  
THD+N vs. Frequency  
10  
1
10  
1
VDD=5V  
VDD=3.6V  
Ci=0.1mF  
Rin=75kW  
RL=8W  
Ci=0.1mF  
Rin=75kW  
RL=8W  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
PO=0.5W  
0.1  
0.1  
PO=1W  
PO=0.3W  
PO=0.5W  
PO=0.3W  
PO=0.1W  
0.01  
0.01  
0.005  
0.005  
20  
100  
1k  
Frequency (Hz)  
10k 20k  
20  
100  
1k  
Frequency (Hz)  
10k 20k  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Typical Operating Characteristics (Cont.)  
THD+N vs. Frequency  
RVDDR =3.6V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
THD+N vs. Frequency  
10  
1
10  
1
VDD=2.4V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
AV=15dB  
PO=0.3W  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
PO=0.8W  
AUX-0025  
AES-17(20kHz)  
0.1  
PO=0.2W  
0.1  
PO=0.4W  
PO=0.2W  
0.01  
0.01  
0.005  
0.005  
20  
100  
1k  
Frequency (Hz)  
10k 20k  
20  
100  
1k  
Frequency (Hz)  
10k 20k  
THD+N vs. Frequency  
Frequency Response  
VDR D=5V  
10  
1
+18  
+16  
+14  
+12  
+10  
+8  
+180  
+160  
+120  
+80  
+40  
+0  
Ci=0.1mF  
Rin=75kW  
RL=4W  
Amplitude  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
PO=1.7W  
Phase  
VDD=5V  
0.1  
Ci=0.1mF  
-40  
Rin=75kW  
RL=8W  
PO=0.13W  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
+6  
-80  
PO=0.9W  
+4  
PO=0.5W  
0.01  
-120  
-160  
+2  
0.005  
-0  
20  
100  
1k  
Frequency (Hz)  
10k 20k  
20  
100  
1k  
10k  
100k  
Frequency (Hz)  
CMRR vs. Frequency  
PSRR vs. Frequency  
+0  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
+0  
VDD=5V  
VDD=5V  
Ci=0.1mF  
Rin=75kW  
RL=8W  
VO=1Vrms  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
Vrr=0.5Vpp  
Ci=0.1mF  
Rin=75kW  
RL=8W  
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
AV=15dB  
Inputs Short  
AUX-0025  
AES-17(20kHz)  
20  
100  
1k  
10k 20k  
20  
100  
1k  
10k 20k  
Frequency (Hz)  
Frequency (Hz)  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Typical Operating Characteristics (Cont.)  
Noise vs. Frequency  
Supply Current vs. Output Power  
1m  
100m  
10m  
0.40  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0
VDD=5V  
Ci=0.1mF  
Rin=75kW  
RL=8W  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
A-weighting  
VDD=5V  
VDD=3.6V  
VDD=2.4V  
VDD=5V  
Ci=1mF  
Rin=75kW  
RL=8W  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
20  
100  
1k  
Frequency (Hz)  
10k 20k  
0
0.3  
0.6  
0.9  
1.2  
1.5  
1.8  
Output Power (W)  
APA2011 Dynamic Range Control  
Function_TDFN  
Supply Current vs. Output Power  
0.7  
+16  
+15  
+14  
+13  
+12  
+11  
+10  
+9  
+8  
+7  
+6  
+5  
2.4  
VDD=5V  
VDD=5V  
VDR=4.5V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
2
1
0
VDD=3.6V  
AV=15dB  
VDD=2.4V  
VDD=5V  
Ci=1mF  
Rin=75kW  
RL=4W  
AV=15dB  
AUX-0025  
AES-17(20kHz)  
AUX-0025  
AES-17(20kHz)  
TDFN3x3-8  
+4  
+3  
+2  
+1  
-0  
0
0.5  
1.0  
1.5  
2.0  
2.5  
0.1  
1
2
3
Output Power (W)  
Input Voltage (Vrms)  
APA2011 Dynamic Range Control  
Function_WLCSP  
APA2011 Dynamic Range Control  
Function_TDFN  
+16  
+15  
+14  
+13  
+12  
+11  
+10  
+9  
1.6  
+16  
2.5  
2
VDD=5V  
VDD=5V  
+15  
+14  
+13  
+12  
+11  
+10  
+9  
VDR=4.23V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
VDR=4.5V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
AV=15dB  
AV=15dB  
1
+8  
+8  
+7  
+6  
+7  
+6  
1
+5  
+4  
+3  
+2  
+5  
+4  
+3  
+2  
AUX-0025  
AES-17(20kHz)  
WLCSP1.5x1.5-9  
AUX-0025  
AES-17(20kHz)  
TDFN3x3-8  
+1  
-0  
+1  
-0  
0
0
0.1  
1
2
3
1
2 2.5  
0.1  
Input Voltage (Vrms)  
Input Voltage (Vrms)  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Typical Operating Characteristics (Cont.)  
APA2011 Dynamic Range Control  
Function_WLCSP  
APA2011 Dynamic Range Control  
Function_TDFN  
+16  
+15  
+14  
+13  
+12  
+11  
+10  
+9  
+8  
+7  
+6  
+5  
1.6  
+16  
+15  
+14  
+13  
+12  
+11  
+10  
+9  
+8  
+7  
+6  
+5  
1.2  
1
VDD=5V  
VDD=5V  
VDR=4V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
VDR=4.23V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
AV=15dB  
AV=15dB  
1
AUX-0025  
AES-17(20kHz)  
TDFN3x3-8  
AUX-0025  
AES-17(20kHz)  
WLCSP1.5x1.5-9  
+4  
+3  
+2  
+1  
+4  
+3  
+2  
+1  
-0  
0
-0  
0
0.1  
1
2
0.1  
1
2
Input Voltage (Vrms)  
Input Voltage (Vrms)  
APA2011 Dynamic Range Control  
Function_WLCSP  
APA2011A Non-Clipping Function_TDFN  
+16  
+15  
+14  
+13  
+12  
+11  
+10  
+9  
1.6  
+16  
2.4  
2
VDD=5V  
VDR=4V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
+15  
+14  
+13  
+12  
+11  
+10  
+9  
VDD=5V  
VDR=4.5V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
AV=15dB  
1
AV=15dB  
+8  
+8  
+7  
+6  
+5  
+4  
+3  
+2  
+1  
-0  
+7  
+6  
+5  
+4  
+3  
+2  
+1  
-0  
1
0
AUX-0025  
AES-17(20kHz)  
WLCSP1.5x1.5-9  
AUX-0025  
AES-17(20kHz)  
TDFN-8  
0
0.1  
1
2
0.1  
1
3
Input Voltage (Vrms)  
Input Voltage (Vrms)  
APA2011A Non-Clipping Function_WLCSP  
APA2011A Non-Clipping Function_TDFN  
+16  
1.6  
+16  
2.4  
2
+15  
+14  
+13  
+12  
+11  
+10  
+9  
+15  
+14  
+13  
+12  
+11  
+10  
+9  
VDD=5V  
VDD=5V  
VDR=4.23V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
VDR=4.5V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
1
AV=15dB  
AV=15dB  
+8  
+7  
+6  
+5  
+4  
+3  
+2  
+1  
+8  
+7  
+6  
+5  
+4  
+3  
+2  
+1  
1
0
AUX-0025  
AES-17(20kHz)  
WLCSP-9  
AUX-0025  
AES-17(20kHz)  
TDFN-8  
-0  
0
-0  
0.1  
1
2
0.1  
1
2
3
Input Voltage (Vrms)  
Input Voltage (Vrms)  
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APA2011/2011A  
Typical Operating Characteristics (Cont.)  
APA2011A Non-Clipping Function_TDFN  
APA2011A Non-Clipping Function_WLCSP  
+16  
1.6  
+16  
+15  
+14  
+13  
+12  
+11  
+10  
+9  
1.2  
1
+15  
+14  
+13  
+12  
+11  
+10  
+9  
+8  
+7  
+6  
VDD=5V  
VDD=5V  
VDR=4V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
VDR=4.23V  
Ci=0.1mF  
Rin=75kW  
RL=4W  
1
AV=15dB  
AV=15dB  
+8  
+7  
+6  
+5  
+5  
+4  
+3  
+2  
+1  
+4  
+3  
+2  
+1  
AUX-0025  
AES-17(20kHz)  
TDFN-8  
AUX-0025  
AES-17(20kHz)  
WLCSP-9  
-0  
0
-0  
0
0.1  
1
2
0.1  
1
2
Input Voltage (Vrms)  
Input Voltage (Vrms)  
APA2011A Non-Clipping Function_WLCSP  
Supply Current vs. Supply Voltage  
+16  
1.2  
5
4
3
2
1
0
+15  
+14  
+13  
+12  
No load  
VDD=5V  
VDR=4V  
Ci=0.1mF  
1
+11 Rin=75kW  
RL=4W  
AV=15dB  
+10  
+9  
+8  
+7  
+6  
+5  
+4  
+3  
+2  
+1  
-0  
AUX-0025  
AES-17(20kHz)  
WLCSP-9  
0
0.01  
1
2
0
1
2
3
5
5.5  
4
Input Voltage (Vrms)  
Supply Voltage (V)  
VDR vs. Output Power (8W)  
Shutdown Current vs. Supply Voltage  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
2
1
0
No load  
Typ  
Max  
Min  
VDD=5V  
0
1
2
3
4
5 5.5  
3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0  
VDR (V)  
Supply Voltage (V)  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Typical Operating Characteristics (Cont.)  
VDR vs. Output Power (4W)  
4
Typ  
Max  
Min  
3
VDD=5V  
2
1
0
3.94.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0  
VDR(V)  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Operating Waveforms  
Power On  
Power Off  
VDD  
VDD  
1
1
M1  
M1  
VOUT  
VOUT  
VOUTP & VOUTN  
VOUTP & VOUTN  
2&3  
2&3  
CH1: VDD, 5V/Div, DC  
CH1: VDD, 5V/Div, DC  
CH2: VOUTP, 1V/Div, DC  
CH3: VOUTN, 1V/Div, DC  
CHM1: VOUT(CH2-CH3), 100mV/Div, DC  
TIME: 40ms/Div  
CH2: VOUTP, 1V/Div, DC  
CH3: VOUTN, 1V/Div, DC  
CHM1: VOUT(CH2-CH3), 100mV/Div, DC  
TIME: 2ms/Div  
Shutdown Release  
Shutdown  
VDD  
VDD  
1
1
M1  
M1  
VOUT  
VOUT  
VOUTP & VOUTN  
VOUTP & VOUTN  
2&3  
2&3  
CH1: VSD, 5V/Div, DC  
CH1: VSD, 5V/Div, DC  
CH2: VOUTP, 1V/Div, DC  
CH3: VOUTN, 1V/Div, DC  
CHM1: VOUT(CH2-CH3), 100mV/Div, DC  
TIME: 20ms/Div  
CH2: VOUTP, 1V/Div, DC  
CH3: VOUTN, 1V/Div, DC  
CHM1: VOUT(CH2-CH3), 100mV/Div, DC  
TIME: 1ms/Div  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Pin Description  
PIN  
NO.  
I/O/P  
FUNCTION  
NAME  
WLCSP1.5x1.5-9  
TDFN3x3-8  
A1  
A2  
A3  
3
7
8
INP  
GND  
OUTN  
I
Positive Input of Power Amplifier.  
P
O
Ground Connection for Circuitry.  
Negative Output of Power Amplifier.  
Setting the Maximum Output Power; Disable the DRC/Non-clipping,  
when VDR<0.2VDD, and if the 0.2VDD<VDR<0.55VDD, the VDR is set to  
0.55VDD by internal, this is maximum power limit (Minimum the  
output power).  
R1  
VDR  
=
=
´ VDD  
R1 + 10kW  
B1  
2
DR  
I
2
2(VDR - 0.5VDD  
)
P
*
RSPK: Speaker Resistor  
O
RSPK  
Note: The setting value has 15% variation by IC process and this equation only for  
WLCSP1.5x1.5-9 package, the TDFN3x3-8 package's output power will less than the  
calculation.  
B2  
6
VDD  
P
Supply Voltage Input Pin.  
B3  
C1  
-
PGND  
INN  
P
I
Ground Connection for Power Stage  
Negative Input of Power Amplifier.  
4
Shutdown Mode Control Input, Place entire IC in shutdown mode  
when held low.  
SD  
C2  
C3  
1
5
I
OUTP  
O
Positive Output of Power Amplifier.  
Block Diagram  
AV=27dB(22.4V/V)  
AV=15dB (5.6V/V)  
100kW  
Gate  
Drive  
OUTN  
25kW  
INN  
VDD  
AGC  
INP  
25kW  
Gate  
Drive  
OUTP  
PGND  
100kW  
GND  
AGC  
Setting  
DR  
VDD  
OSC  
VDD  
Shutdown  
Control  
Bias &  
Reference  
Protection  
Function  
SD  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Typical Application Circuit  
Differential input mode (TDFN3x3-8)  
VDD  
CS2  
CS1  
0.1mF  
10mF  
Shutdown  
Control  
SD  
DR  
OUTN  
GND  
1
2
3
4
8
7
6
5
*R1  
VDD  
APA2011/  
2011A  
Ci1  
INP  
INN  
VDD  
0.1mF  
0.1mF  
Differential  
Signals  
4W  
Ci2  
OUTP  
*R1: Setting the Maximum Output Power  
2
R1  
2(VDR - 0.5VDD  
)
VDR  
=
´ VDD  
RSPK: Speaker Resistor  
* PO  
=
R1 +10kW  
RSPK  
Note : *The setting value has 15% variation by IC process and this equation only for WLCSP1.5x1.5-9 package, the TDFN3x3-8  
package’s output power will less than the calculation.  
Single-Ended input mode (TDFN3x3-8) and AV=15dB  
VDD  
CS2  
0.1mF  
CS1  
10mF  
Shutdown  
Control  
OUTN  
GND  
SD  
DR  
1
2
3
4
8
7
6
5
*R1  
Ri1  
VDD  
APA2011/  
2011A  
Ci1  
Single-ended  
Signals  
INP  
75kW  
INN  
VDD  
4W  
0.022mF  
Ri2  
Ci2  
0.022mF  
OUTP  
75kW  
*R1: Setting the Maximum Output Power  
2
R1  
2(VDR - 0.5VDD  
)
VDR  
AV  
=
=
´ VDD  
* PO  
RSPK: Speaker Resistor  
=
R1 +10kW  
RSPK  
100kW  
75kW (Ri1 &Ri2 )+ 25kW  
´ 5.6 = 5.6(V/V), AV = 20Log5.6 = 15dB  
Note : *The setting value has 15% variation by IC process and this equation only for WLCSP1.5x1.5-9 package, the TDFN3x3-8  
package’s output power will less than the calculation.  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Function Description  
Fully Differential Amplifier  
The APA2011/2011A modulation scheme is shown in fig-  
ure 1. The outputs VOUTP and VOUTN are in phase with each  
other when no input signals. When output > 0V, the duty  
cycle of VOUTP is greater than 50% and VOUTN is less than  
50%; when output <0V, the duty cycle of VOUTP is less than  
50% and VOUTN is greater than 50%. This method reduces  
the switching current across the load and reduces the I2R  
losses in the load that improves the amplifier’s efficiency.  
This modulation scheme has very short pulses across  
the load, this making the small ripple current and very  
little loss on the load, and the LC filter can be eliminated  
in most applications. Added the LC filter can increase the  
efficiency by filter the ripple current.  
The APA2011/2011A is a fully differential amplifier with  
differential inputs and outputs. The fully differential has  
some advantages versus traditional amplifier. First, don’t  
need the input coupling capacitors because the com-  
mon-mode feedback will compensate the input bias. The  
inputs can biased from 0.5V to VDD-0.5V, and the outputs  
still be biased at mid-supply of APA2011/2011A. If the in-  
puts are biased out of the input range, the coupling ca-  
pacitors are required. Second, don’t need the mid-sup-  
ply capacitor (CB) because any shift of the mid-supply of  
APA2011/2011A will have the same affect for both positive  
& negative channel, and will cancel at the differential  
outputs. Third, the fully differential amplifier will cancel  
the GSM RF transmitter’s signal (217Hz).  
Non-ClippingFunction(APA2011A)  
Maximum Output Power  
Class D Operation  
Output = 0V  
AV=0dB  
VOUTP  
VOUTN  
AV=15dB  
VOUT  
(VOUTP-VOUTN  
)
VIN  
IOUT  
Figure 2. APA2011A Non-Clipping Control Function  
Output > 0V  
The APA2011A provides the 15 steps Non-Clipping  
Control, and the range is from 15dB to 0dB, 1dB/step.  
When the output reaches the maximum power setting  
value, the internal Programmable Gain Amplifier (PGA)  
will decrease the gain for prevent the output waveform  
clipping. This feature prevents speaker damage from  
occurring clipping.  
VOUTP  
VOUTN  
VOUT  
(VOUTP-VOUTN  
)
IOUT  
Output < 0V  
Using the DR pin to set the non-clipping function and  
limit the output power. Disable the AGC, when VDR<0.2VDD,  
and if the 0.2VDD<VDR<0.55VDD, the VDR is set to 0.55VDD by  
internal, this is maximum power limit (Minimum the out-  
put power).  
VOUTP  
VOUTN  
VOUT  
(VOUTP-VOUTN  
R1  
)
(1)  
VDR  
=
´ VDD  
R1 +10kW  
IOUT  
2
2(VDR - 0.5VDD  
)
*PO =  
RSPK: Speaker Resistor (2)  
RSPK  
Figure 1. APA2011/2011 Output Waveform (Voltage &  
Current)  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Function Description (Cont.)  
Non-Clipping Function (APA2011A) (Cont.)  
Attack Time and Release Time  
Note: *The setting value has 15% variation by IC process and  
this equation only for WLCSP1.5x1.5-9 package, the TDFN3x3-8  
package’s output power will less than the calculation.  
Attack Time  
Release  
Time  
Gain  
Dynamic Range Control Function  
Limit Level  
Maximum Output Power  
AV=15dB  
Time  
Power Limit  
AGC Start Point  
AV=0dB  
Limit Level  
A
B
C
D
VIN  
Figure 4. APA2011 Output Signal vs. Time  
Figure 3. APA2011 Auto Gain Control Function  
A. The output level excesses the AGC start point.  
B. A to B is the attack time (32ms), but the Gain needs to  
change at output signal zero crossing.  
The APA2011 provides the 15 steps Dynamic Range Con-  
trol (DRC), and the range is from 15dB to 0dB, 1dB/step.  
DRC provides continuous automatic gain adjustment to  
the amplifier through an internal Programmable Gain  
Amplifier (PGA). This feature enhances the perceived  
audio loudness and prevents speaker damage from oc-  
curring clipping at the same time.  
C. The output level is under the limit level.  
D. D to E is release time (512ms), but the Gain needs to change  
at output signal zero crossing..  
When the APA2011/2011A senses the input signal ex-  
cesses the start point of DRC/Non-clipping, it needs 32ms  
to decrease the gain, this calls “Attack Time”. And if the  
input signal is small than the threshold about 512ms, the  
gain will be recovery, this time calls “ release time”.  
The APA2011’s compress ratio is 2:1, it means when the  
input signal has the 2dB change, the output signal will  
change 1dB. Because most small form speakers have  
only small dynamic range, the compress allows input  
signal with large dynamic range to fit into a small speaker  
with small dynamic rage.  
The equations 1 & 2 are the method that set the maxi-  
mum output power. If the R1=40kW, the VDR is 4V.  
Therefore, the maximum output power is 1.125W  
(RL=4W), and the output voltage swing is limited at 3Vpp  
(1.5Vp) [The limited voltage can be calculated by 4V(VDR)-  
2.5V(Internal Bypass Voltage)=1.5V]. The AGC start point  
is 0.536VPP (1.5Vp/5.6(AV)=0.268VP) at output, it means  
when the output power excesses 0.036W, the AGC will  
start work and decrease the gain by 1dB. If the input sig-  
nal increase un-limit, the gain will be decreased until the  
maximum gain attenuation (15dB).  
And the APA2011A is just decrease the gain to avoid the  
output signal clipping, and the maximum control is 15dB  
gain.  
Limit Level  
Time  
Shutdown Operation  
In order to reduce power consumption while not in use,  
the APA2011/2011A contains a shutdown function to ex-  
ternally turn off the amplifier bias circuitry. This shutdown  
feature turns the amplifier off when logic low is placed on  
the SD pin for APA2011/2011A. The trigger point between  
Limit Level  
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Rev. A.4 - Aug., 2013  
APA2011/2011A  
Function Description (Cont.)  
Shutdown Operation (Cont.)  
a logic high and logic low level is typically 1.4V. It is best to  
switch between the ground and the supply voltage VDD to  
provide maximum device performance. By switching the  
SD pin to a low level, the amplifier enters a low-consump-  
tion- current state, IDD for APA2011/2011A is in shutdown  
mode. On normal operating, APA2011/2011A’s SD pin  
should pull to a high level to keep the IC out of the shut-  
down mode. The SD pin should be tied to a definite volt-  
age to avoid unwanted state changes.  
Over-Current Protection  
The APA2011/2011A monitors the output current. When  
the current exceeds the current-limit threshold, the  
APA2011/2011A turns off the output stage to prevent the  
output device from damages in over-current or short-cir-  
cuit condition. The IC will turn on the output buffer after  
1ms, but if the over-current or short-circuits condition still  
remains, it enters the Over-Current protection again. The  
situation will circulate until the over-current or short-cir-  
cuits has be removed.  
Thermal Protection  
The over-temperature circuit limits the junction tempera-  
ture of the APA2011/2011A. When the junction tempera-  
ture exceeds TJ = +150 oC, a thermal sensor turns off the  
output buffer, allowing the devices to cool. The thermal  
sensor allows the amplifier to start-up after the junction  
temperature down about 125 oC. The thermal protection  
is designed with a 25 oC hysteresis to lower the average  
TJ during continuous thermal overload conditions, in-  
creasing lifetime of the IC.  
Copyright ã ANPEC Electronics Corp.  
18  
www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Application Information  
Square Wave Into The Speaker  
tor is the leakage path from the input source through the  
input network (Ri + Rf, Ci) to the load. This leakage current  
creates a DC offset voltage at the input to the amplifier  
that reduces useful headroom, especially in high gain  
applications. For this reason, a low-leakage tantalum or  
ceramic capacitor is the best choice. When polarized ca-  
pacitors are used, the positive side of the capacitor should  
face the amplifier input in most applications because the  
DC level of the amplifier input is held at VDD/2. Please note  
that it is important to confirm the capacitor polarity in the  
application.  
Apply the square wave into the speaker may cause the  
voice coil of speaker jump out the air gap and deface the  
voice coil. However, this depends on the amplitude of  
square wave is high enough and the bandwidth of speaker  
is higher than the square wave’s frequency. For 500kHz  
switching frequency, this is not issued for the speaker  
because the frequency is beyond the audio band and  
can’t significantly move the voice coil, as cone movement  
is proportional to 1/f2 for frequency out of audio band.  
Input Resistor, Ri  
Ferrite Bead Selection  
The APA2011/2011A’s input resistor is fixed and the value  
is 25kW. The input resistance has wide variation (+/-5%)  
is caused by manufacture. The gain also can be set by  
the external resistors (Riexr).  
If the traces form APA2011/2011A to speaker is short, the  
ferrite bead filters can reduce the high frequency radiated  
to meet the FCC & CE required.  
A ferrite that has very low impedance at low frequencies  
100kW  
100kW  
AV  
=
´ 5.6 =  
´ 5.6  
(3)  
and high impedance at high frequencies (above 1 MHz)  
is recommended.  
Ri + Riexr  
25kW + Riexr(Ri1 & Ri2)  
For fully differential operating, the Riexr (Ri1& Ri2) match is  
very important for CMRR, PSRR, and harmonic distortion  
performance. It’s recommended to use 1% tolerance re-  
sistor or better. Keep the input trace as short as possible  
to limit the noise injection. The gain is recommended to  
set 5.6V/V or lower for optimal the APA2011/2011A’s  
performance.  
Output Low-Pass Filter  
If the traces form APA2011/2011A to speaker are short, it  
don’t require output filter for FCC & CE standard.  
A ferrite bead may be needed if it’s failing the test for FCC  
or CE tested without the LC filter. The figure 5 is the sample  
for added ferrite bead; the ferrite show choosing high  
impedance in high frequency.  
Input Capacitor, Ci  
In the typical application, an input capacitor, Ci, is required  
to allow the amplifier to bias the input signal to the proper  
DC level for optimum operation. In this case, Ci and the  
input impedance Ri form a high-pass filter with the corner  
Ferrite  
Bead  
VON  
frequency determined in the following equation:  
1
1nF  
fC(highpass )  
=
(4)  
Ferrite  
Bead  
2pRiCi  
4W  
The value of Ci must be considered carefully because it  
directly affects the low frequency performance of the circuit.  
Where Ri is 25kW (minimum) and the specification calls  
for a flat bass response down to 100Hz. Equation is  
VOP  
1nF  
reconfigured as below:  
1
Figure 5. Ferrite Bead Output Filter  
Ci =  
(5)  
2pRifc  
Figure 6 and 7 and are examples for added the LC filter  
(Butterworth), it’s recommended for the situation that the  
trace form amplifier to speaker is too long, and needs to  
eliminate the radiated emission or EMI.  
When the input resistance variation is considered, the Ci  
is 0.064mF, so a value in the range of 0.1mF to 0.22mF  
would be chosen. A further consideration for this capaci-  
Copyright ã ANPEC Electronics Corp.  
19  
www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Application Information (Cont.)  
Output Low-Pass Filter (Cont.)  
typically 0.1mF placed as close as possible to the device  
VDD pin for works best. For filtering lower frequency noise  
signals, a large aluminum electrolytic capacitor of 10mF  
or greater placed near the audio power amplifier is  
recommended.  
36mH  
OUTP  
Layout Recommendation  
1mF  
9XF 0.275mm  
36mH  
1mF  
8W  
OUTN  
.
Figure 6. LC output filter for 8W speaker  
18mH  
OUTP  
2.2mF  
0.5mm  
18mH  
2.2mF  
4W  
OUTN  
Figure 8. WLCSP1.5x1.5-9 Land Pattern Recommenda-  
tion  
Ground Plane for  
ThermalVia Diamater  
ThermalPAD  
12milx5  
0.275mm  
1.2mm  
0.35mm  
Figure 7. LC Output Filter for 4W Speaker  
Figure 6 and 7’s low pass filter cut-off frequency are 25kHz  
(FC).  
1
2p LC  
fC(lowpass)  
=
(6)  
0.65mm  
Power-Supply Decoupling Capacitor, CS  
The APA2011/2011A is a high-performance CMOS audio  
amplifier that requires adequate power supply decoupling  
to ensure the output total harmonic distortion (THD) is as  
low as possible. Power supply decoupling also prevents  
the oscillations being caused by long lead length be-  
tween the amplifier and the speaker.  
1.8mm  
Figure 9. TDFN3x3-8 Land Pattern Recommendation  
1. All components should be placed close to theAPA2011/  
2011A. For example, the input capacitor (Ci) should be  
close to APA2011/2011A’s input pins to avoid causing  
noise coupling to APA2011/2011A’s high impedance  
inputs; the decoupling capacitor (CS) should be placed  
by the APA2011’s power pin to decouple the power rail  
noise.  
The optimum decoupling is achieved by using two differ-  
ent types of capacitors that targets on different types of  
noise on the power supply leads. For higher frequency  
transients, spikes, or digital hash on the line, a good low  
equivalent-series-resistance (ESR) ceramic capacitor,  
Copyright ã ANPEC Electronics Corp.  
20  
www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Application Information (Cont.)  
Layout Recommendation (Cont.)  
2. The output traces should be short, wide (>50mil) and  
symmetric.  
3. The input trace should be short and symmetric.  
4. The power trace width should greater than 50mil.  
5. The TDFN3x3-8 Thermal PAD should be soldered on  
PCB, and the ground plane needs soldered mask (to  
avoid short circuit) except the Thermal PAD area.  
Copyright ã ANPEC Electronics Corp.  
21  
www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Package Information  
WLCSP1.5x1.5-9  
PIN A1  
D
A2  
A1  
A
e
WLCSP1.5x1.5-9  
S
Y
M
B
O
MILLIMETERS  
MIN. MAX.  
INCHES  
MIN.  
MAX.  
0.026  
0.009  
0.017  
0.012  
0.060  
0.060  
L
A
0.53  
0.67  
0.24  
0.43  
0.31  
1.53  
1.53  
0.021  
0.008  
0.013  
0.011  
0.058  
0.058  
A1  
A2  
b
0.20  
0.33  
0.29  
1.47  
1.47  
D
E
e
0.50 BSC  
0.020 BSC  
Copyright ã ANPEC Electronics Corp.  
22  
www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Package Information  
TDFN3x3-8  
A
D
Pin 1  
D2  
A1  
A3  
Pin 1 Corner  
e
TDFN3x3-8  
S
Y
M
B
O
L
MILLIMETERS  
INCHES  
MIN.  
MAX.  
MIN.  
MAX.  
0.031  
0.002  
A
0.70  
0.00  
0.80  
0.05  
0.028  
0.000  
A1  
A3  
0.20 REF  
0.008 REF  
0.010  
0.114  
0.075  
0.114  
0.055  
0.014  
0.122  
0.094  
0.122  
0.069  
b
0.25  
0.35  
3.10  
2.40  
3.10  
1.75  
D
2.90  
1.90  
2.90  
1.40  
D2  
E
E2  
e
0.65 BSC  
0.026 BSC  
0.012  
0.008  
0.020  
L
0.30  
0.20  
0.50  
K
Copyright ã ANPEC Electronics Corp.  
23  
www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Carrier Tape & Reel Dimensions  
P0  
P2  
P1  
OD0  
A
K0  
A0  
A
OD1  
B
B
SECTION A-A  
SECTION B-B  
d
T1  
Application  
WLCSP1.5x1.5-9  
Application  
A
H
T1  
8.4+2.00 13.0+0.50  
-0.00 -0.20  
P2 D0  
C
d
D
W
E1  
F
178.0±2.00 50 MIN.  
1.5 MIN.  
D1  
20.2 MIN. 8.0±0.30 1.75±0.10  
3.5±0.05  
K0  
P0  
4.0±0.10  
A
P1  
4.0±0.10  
H
T
A0  
B0  
1.5+0.10  
-0.00  
0.6+0.00  
-0.40  
2.0±0.05  
1.5 MIN.  
d
1.70±0.20 1.70±0.20 0.90±0.20  
T1  
C
D
W
E1  
F
12.4+2.00 13.0+0.50  
-0.00 -0.20  
178.0±2.00 50 MIN.  
1.5 MIN.  
D1  
20.2 MIN. 12.0±0.30 1.75±0.10  
5.5±0.05  
K0  
TDFN3x3-8  
P0  
P1  
P2 D0  
T
A0  
B0  
1.5+0.10  
-0.00  
0.6+0.00  
-0.40  
4.0±0.10  
8.0±0.10  
2.0±0.05  
1.5 MIN.  
3.30±0.20 3.30±0.20 1.30±0.20  
(mm)  
Devices Per Unit  
Package Type  
WLCSP1.5x1.5-9  
TDFN3x3-8  
Unit  
Quantity  
3000  
Tape & Reel  
Tape & Reel  
3000  
Copyright ã ANPEC Electronics Corp.  
24  
www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Taping Direction Information  
WLCSP1.5x1.5-9  
USER DIRECTION OF FEED  
TDFN3x3-8  
USER DIRECTION OF FEED  
Copyright ã ANPEC Electronics Corp.  
25  
www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Classification Profile  
Classification Reflow Profiles  
Profile Feature  
Sn-Pb Eutectic Assembly  
Pb-Free Assembly  
Preheat & Soak  
100 °C  
150 °C  
60-120 seconds  
150 °C  
200 °C  
60-120 seconds  
Temperature min (Tsmin  
)
Temperature max (Tsmax  
)
Time (Tsmin to Tsmax) (ts)  
Average ramp-up rate  
(Tsmax to TP)  
3 °C/second max.  
3°C/second max.  
Liquidous temperature (TL)  
Time at liquidous (tL)  
183 °C  
60-150 seconds  
217 °C  
60-150 seconds  
Peak package body Temperature  
(Tp)*  
See Classification Temp in table 1  
20** seconds  
See Classification Temp in table 2  
30** seconds  
Time (tP)** within 5°C of the specified  
classification temperature (Tc)  
Average ramp-down rate (Tp to Tsmax  
)
6 °C/second max.  
6 °C/second max.  
6 minutes max.  
8 minutes max.  
Time 25°C to peak temperature  
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.  
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.  
Copyright ã ANPEC Electronics Corp.  
26  
www.anpec.com.tw  
Rev. A.4 - Aug., 2013  
APA2011/2011A  
Classification Reflow Profiles (Cont.)  
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)  
Volume mm3  
350  
Package  
Thickness  
<2.5 mm  
³ 2.5 mm  
Volume mm3  
<350  
235 °C  
220 °C  
220 °C  
220 °C  
Table 2. Pb-free Process – Classification Temperatures (Tc)  
Package  
Thickness  
<1.6 mm  
Volume mm3  
Volume mm3  
350-2000  
260 °C  
Volume mm3  
<350  
260 °C  
260 °C  
250 °C  
>2000  
260 °C  
245 °C  
245 °C  
1.6 mm – 2.5 mm  
³ 2.5 mm  
250 °C  
245 °C  
Reliability Test Program  
Test item  
SOLDERABILITY  
HOLT  
Method  
JESD-22, B102  
JESD-22, A108  
JESD-22, A102  
JESD-22, A104  
MIL-STD-883-3015.7  
JESD-22, A115  
JESD 78  
Description  
5 Sec, 245°C  
1000 Hrs, Bias @ Tj=125°C  
168 Hrs, 100%RH, 2atm, 121°C  
500 Cycles, -65°C~150°C  
VHBM2KV  
PCT  
TCT  
HBM  
MM  
VMM200V  
10ms, 1tr100mA  
Latch-Up  
Customer Service  
Anpec Electronics Corp.  
Head Office :  
No.6, Dusing 1st Road, SBIP,  
Hsin-Chu, Taiwan, R.O.C.  
Tel : 886-3-5642000  
Fax : 886-3-5642050  
Taipei Branch :  
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,  
Sindian City, Taipei County 23146, Taiwan  
Tel : 886-2-2910-3838  
Fax : 886-2-2917-3838  
Copyright ã ANPEC Electronics Corp.  
Rev. A.4 - Aug., 2013  
27  
www.anpec.com.tw  

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