PEEL18LV8ZJ-35L [ANACHIP]
CMOS Programmable Electrically Erasable Logic Device; CMOS可编程电可擦除逻辑器件
| 型号： | PEEL18LV8ZJ-35L |
| 厂家： | 
ANACHIP CORP |
| 描述： | CMOS Programmable Electrically Erasable Logic Device |
| 文件： | 总10页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PEEL™ 18LV8Z-25 / I-35
CMOS Programmable Electrically Erasable Logic Device
Features
•
Low Voltage, Ultra Low Power Operation
•
Architectural Flexibility
- Vcc = 2.7 to 3.6 V
- Enhanced architecture fits in more logic
- 113 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- Icc = 5 µA (typical) at standby
- Icc = 1.5 mA (typical) at 1 MHz
- Meets JEDEC LV Interface Spec (JEDSD8-A)
- 5 Volts tolerant inputs and I/O’s
- 12 possible macrocell configurations
- Asynchronous clear, Synchronous preset
- Independent output enables
•
•
CMOS Electrically Erasable Technology
- Superior factory testing
- Programmable clock; pin 1 or p-term
- Programmable clock polarity
- Reprogrammable in plastic package
- Reduces retrofit and development costs
- 20 Pin DIP/SOIC/TSSOP and PLCC
- Schmitt triggers on clock and data inputs
Application Versatility
•
Schmitt Trigger Inputs
- Replaces random logic
- Eliminates external Schmitt trigger devices
- Ideal for encoder designs
- Super set of standard PLDs
- Pin and JEDEC compatible with 16V8
- Ideal for battery powered systems
- Replaces expensive oscillators
General Description
The PEEL18LV8Z is a Programmable Electrically Erasable The differences between the PEEL18LV8Z and
Logic (PEEL) SPLD (Simple Programmable Logic Device) PEEL18CV8 include the addition of programmable clock
that operates over the supply voltage range of 2.7V-3.6V polarity, p-term clock, and Schmitt trigger input buffers on
and features ultra-low, automatic "zero" power-down all inputs, including the clock. Schmitt trigger inputs allow
operation. The PEEL18LV8Z is logically and functionally direct input of slow or noisy signals.
similar to Anachip's 5V PEEL18CV8 and PEEL18CV8Z.
Like the PEEL18CV8, the PEEL18LV8Z is a logical
The "zero power" (25 µA max. Icc) power-down mode
superset of the industry standard PAL16V8 SPLD. The
makes the PEEL18LV8Z ideal for a broad range of battery-
PEEL18LV8Z provides additional architectural features that
powered portable equipment applications, from hand-held
allow more logic to be incorporated into the design.
meters to PCMCIA modems. EE-reprogrammability
Anachip's JEDEC file translator allows easy conversion of
provides both the convenience of fast reprogramming for
existing 20 pin PLD designs to the PEEL18LV8Z
product development and quick product personalization in
architecture without the need for redesign. The
manufacturing, including Engineering Change Orders.
PEEL18LV8Z architecture allows it to replace over twenty
standard 20-pin DIP, SOIC, TSSOP and PLCC packages.
I/CLK1
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
I/CLK1
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
CLK MUX (Optional)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ª
9
10
9
10
GND
GND
I
DIP
TSSOP
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
I/CLK1
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
3
2
1
19
20
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
4
5
6
7
8
18
17
16
15
14
9
10 11 12 13
10
GND
PLCC-J
SOIC
Figure 2 - Block Diagram
Figure 1 - Pin Configuration
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights
under any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10
(O p tio na l)
I/ C LK*
I*
I*
I*
I*
I*
I*
I*
I*
* Schmitt
Trigger
Inputs
I*
Figure 3 - PEEL18LV8Z Logic Array Diagram
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Function Description
The PEEL18LV8Z implements logic functions as sum-of- When programming the PEEL18LV8Z, the device
products expressions in a programmable-AND/fixed-OR programmer first performs a bulk erase to remove the
logic array. Programming the connections of input signals previous pattern. The erase cycle opens every logical
into the array creates user-defined functions. User- connection in the array. The device is configured to
configurable output structures in the form of I/O macrocells perform the user-defined function by programming selected
further increase logic flexibility.
connections in the AND array. (Note that PEEL device
programmers automatically program all of the connections
on unused product terms so that they will have no effect on
the output function).
Architecture Overview
The PEEL18LV8Z architecture is illustrated in the block
diagram of Figure 14. Ten dedicated inputs and 8 I/Os
provide up to 18 inputs and 8 outputs for creation of logic Variable Product Term Distribution
functions. At the core of the device is a programmable
The PEEL18LV8Z provides 113 product terms to drive the
electrically erasable AND array that drives a fixed OR array.
With this structure, the PEEL18LV8Z can implement up to
8 sum-of-products logic expressions.
8 OR functions. These product terms are distributed
among the outputs in groups of 8, 10, 12, 14, and 16 to
form logical sums (see Figure 15). This distribution allows
Associated with each of the 8 OR functions is an I/O optimum use of the device resources.
macrocell that can be independently programmed to one of
12 different configurations. The programmable macrocells
allow each I/O to be used to create sequential or
combinatorial logic functions of active-high or active-low
polarity, while providing three different feedback paths into
the AND array.
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides
complete control over the architecture of each output. The
ability to configure each output independently lets you to
tailor the configuration of the PEEL18LV8Z to the precise
requirements of your design.
AND/OR Logic Array
The programmable AND array of the PEEL18LV8Z (shown
in Figure 15) is formed by input lines intersecting product
terms. The input lines and product terms are used as
follows:
Macrocell Architecture
Each I/O macrocell, as shown in Figure 4, consists of a D-
type flip-flop and two signal-select multiplexers. The four
EEPROM bits controlling these multiplexers determine the
configuration of each macrocell. These bits determine
output polarity, output type (registered or non-registered)
and input-feedback path (bidirectional I/O, combinatorial
feedback). Refer to Table 1 for details.
•
36 Input Lines:
- 20 input lines carry the true and complement of
the signals applied to the 10 input pins
- 16 additional lines carry the true and complement
values of feedback or input signals from the 8
I/Os
Equivalent circuits for the twelve macrocell configurations
are illustrated in Figure 5. In addition to emulating the four
PAL-type output structures (configurations 3, 4, 9, and 10),
the macrocell provides eight additional configurations.
When creating a PEEL device design, the desired
macrocell configuration is generally specified explicitly in
the design file. When the design is assembled or compiled,
the macrocell configuration bits are defined in the last lines
of the JEDEC programming file.
•
113 product terms:
- 102 product terms are used to form sum of
product functions
- 8 output enable terms (one for each I/O)
- 1 global synchronous preset term
- 1 global asynchronous clear term
- 1 programmable clock term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not
there is a logical connection at that intersection. Each
product term is essentially a 36-input AND gate. A product
term that is connected to both the true and complement of
an input signal will always be FALSE and thus will not
affect the OR function that it drives. When all the
connections on a product term are opened, a "don't care"
state exists and that term will always be TRUE.
Output Type
The signal from the OR array can be fed directly to the
output pin (combinatorial function) or latched in the D-type
flip-flop (registered function). The D-type flip-flop latches
data on the rising edge of the clock and is controlled by the
global preset and clear terms. When the synchronous
preset term is satisfied, the Q output of the register is set
HIGH at the next rising edge of the clock input. Satisfying
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the asynchronous clear sets Q LOW, regardless of the Combinatorial Feedback
clock state. If both terms are satisfied simultaneously, the
The signal-select multiplexer gives the macrocell the ability
clear will override the preset.
to feedback the output of the OR gate, bypassing the
output buffer, regardless of whether the output function is
registered or combinatorial. This feature allows the creation
of asynchronous latches, even when the output must be
disabled. (Refer to configurations 5, 6, 7, and 8 in Figure 5.)
Output Polarity
Each macrocell can be configured to implement active-high
or active-low logic. Programmable polarity eliminates the
need for external inverters.
Registered Feedback
Output Enable
Feedback also can be taken from the register, regardless
of whether the output function is programmed to be
The output of each I/O macrocell can be enabled or
disabled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is switched into the high-impedance state.
combinatorial or registered. When implementing
a
combinatorial output function, registered feedback allows
for the internal latching of states without giving up the use
of the external output.
Programmable Clock Options
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bi- A unique feature of the PEEL18LV8Z is a programmable
directional I/O. Opening every connection on the output clock multiplexer that allows the user to select true or
enable term will permanently enable the output buffer and complement forms of either input pin or product-term clock
yield a dedicated output. Conversely, if every connection is sources.
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Operates in both 3 Volt and 3.3 Volt Systems
The PEEL18LV8Z is designed to operate with a V CC range
of 2.7 to 3.6 Volts D.C. This allows operation in both 3 Volt
Input/Feedback Select
The PEEL18LV8Z macrocell also provides control over the 10% (battery operated) and 3.3 Volt 10% (power supply
feedback path. The input/feedback signal associated with operated) systems. The propagation delay t PD is 5 ns
each I/O macrocell can be obtained from three different slower at the lower voltage, but this is typically not an issue
locations; from the I/O input pin, from the Q output of the in battery-operated systems (see
-
A.C. Electrical
flip-flop (registered feedback), or directly from the OR gate CharacteristicsTable 1 - Absolute Maximum Ratings- A.C.
(combinatorial feedback).
Electrical Characteristics).
Bi-directional I/O
Schmitt Trigger Inputs
The PEEL18LV8Z has Schmitt trigger input buffers on all
inputs, including the clock. Schmitt trigger inputs allow
direct input of slow signals such as biomedical and sine
waves or clocks. They are also useful in cleaning up noisy
signals. This makes the PEEL18LV8Z especially desirable
in portable applications where the environment is less
predictable.
The input/feedback signal is taken from the I/O pin when
using the pin as a dedicated input or as a bi-directional I/O.
(Note that it is possible to create a registered output
function with a bi-directional I/O, refer to Figure 4).
Zero Power Feature
The CMOS PEEL18LV8Z features "Zero-Power" standby
operation for ultra-low power consumption. With the "Zero-
Power" feature, transition-detection circuitry monitors the
inputs, I/Os (including CLK) and feedbacks. If these signals
do not change for a period of time greater than
approximately three t PD 's, the outputs are latched in their
current state and the device automatically powers down.
When the next signal transition is detected, the device will
"wake up" for active operation until the signals stop
Figure 4 - PEEL18LV8Z I/O Macro cell
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switching long enough to trigger the next power-down. When the PEEL18LV8Z is powered up, a built-in feature
(Note that the tPD is approximately 5 ns. slower on the first holds the outputs in tri-state until Vcc reaches 2.2V. This
transition from sleep mode.)
prevents output transitions during power-up.
As a result of the "Zero-Power" feature, significant power
savings can be realized for combinatorial or sequential
operations when the inputs or clock change at a modest
rate. See Figure 6.
Figure 5 - Equivalent Circuits for the twelve configurations of the PEEL18LV8Z I/O Macrocell
Configuration
Input/Feedback Select
Output Select
#
A
B
C
D
1
2
3
4
5
6
7
8
9
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Active Low
Register
Combinatorial
Register
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Bi-directional I/O
Combinatorial Feedback
Register Feedback
Combinatorial
Register
10
11
12
Combinatorial
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100
10
programmed. Once the security bit is set it is impossible to
verify (read) or program the PEEL until the entire device
has first been erased with the bulk-erase function.
Signature Word
ICC
The signature word feature allows a 64-bit code to be
programmed into the PEEL18LV8Z if the software option is
used. The code can be read back even after the security
bit has been set. The signature word can be used to
identify the pattern programmed into the device or to
record the design revision, etc.
in
1
mA
0.1
Programming Support
0.01
0.01
0.1
1
10
100
Anachip's JEDEC file translator allows easy conversion of
existing 20 pin PLD designs to the PEEL18LV8Z, without
the need for redesign. Anachip also offers (for free) its
proprietary WinPLACE software, an easy-to-use entry level
PC-based software development system.
Frequency in MHz
Figure 6 - Typical ICC vs. Input Clock Frequency for
the 18LV8Z
Design Security
Programming support includes all the popular third party
programmers such as BP Microsystems, System General,
The PEEL18LV8Z provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs
programmed into the device. The PLD programmer sets
the security bit, either at the conclusion of the programming
cycle or as a separate step, after the device has been
Logical
Devices,
and
numerous
others.
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This device has been designed and tested for the specified
operating ranges. Improper operation outside of these
levels is not guaranteed. Exposure to absolute maximum
ratings may cause permanent damage.
Table 1 - Absolute Maximum Ratings
Symbol
Parameter
Conditions
Rating
Unit
VCC
VI, VO
IO
Supply Voltage
Relative to Ground
-0.5 to + 6.0
-0.5 to 5.5
± 25
V
V
2
1
Voltage Applied to Any Pin
Output Current
Relative to Ground
Per Pin (I OL , I OH )
mA
°C
°C
TST
Storage Temperature
Lead Temperature
-65 to +150
+300
TLT
Soldering 10 Seconds
Table 2 - Operating Range
Symbol
Vcc
Parameter
Conditions
Min
Max
Unit
V
3
Commercial / Industrial
2.7
3.6
Supply Voltage
Commercial
Industrial
See Note 4
0
-40
+70
+85
250
TA
Ambient Temperature
VCC Rise Time
°C
TRVCC
ms
Table 3 - D. C. Electrical Characteristics Over the operating range (unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Unit
VOH
VOHC
VOL
VOLC
VIH
Output HIGH Voltage - TTL
Output HIGH Voltage - CMOS
Output LOW Voltage - TTL
Output LOW Voltage - CMOS
Input HIGH Voltage
VCC = Min, IOH = -2.0 mA
VCC - 0.5
VCC - 0.3
V
V
V
V
V
V
V
VCC = Min, IOH = -10 A
VCC = Min, IOL = 8.0 mA
VCC = Min, IOL = 10 A
VCC = 3.3 V
0.4
0.15
5.5
2.0
-0.3
0.2
VIL
Input LOW Voltage
VCC = 3.3 V
0.8
VH
Input Voltage Hysteresis
+/- 1
25
VCC = Max, GND ≤ VIN ≤ VCC, I/O = High Z
VCC = Min, GND ≤ VIN ≤ 5.5V, I/O = High Z
VCC = Max, GND ≤ VIN ≤ VCC, I/O = High Z
VCC = Min, GND ≤ VIN ≤ 5.5V, I/O = High Z
µA
µA
µA
µA
µA
mA
PF
PF
Input Leakage Current
I/O Leakage Current
IIN
+/- 1
500
25
5
ICCS
VCC Current, Standby
VCC Current, f=1MHz
Input Capacitance
5 (typ)
VIN = 0V or VCC, All Outputs disabled
11
5
1.5 (typ)
3
ICC
VIN = 0V or VCC, All Outputs disabled
8
6
CIN
TA = 25°C, VCC = Max @ f = 1 MHz
8
Output Capacitance
12
COUT
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Table 4 - A.C. Electrical Characteristics
Over the operating range9
-25
I-35
3V±10% 3.3V±10% 3V±10% 3.3V±10%
Symbol
Parameter
Units
Min Max Min Max Min Max Min Max
tPD
tOE
Input6 to non-registered output in continuous mode13
Input6 to output enable7
30
30
30
20
25
25
25
15
40
40
40
28
35
35
35
25
ns
ns
ns
ns
tOD
Input6 to output disable7
tCO1
Clock to Output
Clock to comb output delay via internal registered
tCO2
40
14
35
9
56
20
49
13
ns
feedback
tCF
tSC
Clock to Feedback
ns
ns
Input6 or feedback setup to clock
Input6 hold after clock
20
0
15
0
28
0
21
0
tHC
ns
tCL, tCH
tCP
Clock low time, clock high time9
Min clock period Ext (tSC + tCO1 )
Internal feedback 1/ (tSC + tCF) 12
External Feedback (1/ tCP) 12
No Feedback 1/ (tCL + tCH) 12
Asynchronous Reset Pulse Width
Input to Asynchronous Reset
20
40
29.4
25
25
30
13
28
18
ns
30
56
39
ns
fMAX1
fMAX2
fMAX3
tAW
41.6
33.3
38.4
25
20.8
17.9
17.9
40
29.4
25.6
27.7
35
MHz
MHz
MHz
ns
tAP
30
30
5
25
25
5
40
40
5
35
35
5
ns
tAR
Asynchronous Reset recovery time
Power-on reset time for registers in clear state14
ns
tRESET
µs
Inputs I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Figure 7 - Switching Waveforms
Notes:
1.
Minimum DC input is -0.5V, however, inputs may undershoot to
-2.0V for periods less than 20 ns.
8.
9.
Capacitances are tested on a sample basis.
Test conditions assume: signal transition times of 3ns or less
from the 10% and 90% points, timing reference levels of 1.5V
(Unless otherwise specified).
2.
3.
VI and VO are not specified for program / verify operation.
The Supply Voltage range of 2.7 to 3.6V was chosen to allow
this part to be used in both 3V ±10% and 3.3V ±10%
applications.
10.
11.
Test one output at a time for duration of less than 1 second.
ICC for a typical application: This parameter is tested with the
device programmed as an 8-bit Counter.
4.
Test Points for Clock and VCC in tR and tF are referenced at
the 10% and 90% levels.
12.
Parameters are not 100% tested. Specifications are based on
initial characterization and are tested after any design process
modification that might affect operational frequency.
tPD , tOE , tOD , tCO , tSC , and tAP are approximately 5 ns.
slower on the first transaction from sleep mode.
All inputs at GND.
5.
6.
7.
I/O pins are 0V and VCC .
"Input" refers to an input pin signal.
13.
14.
tOE is measured from input transition to V REF± 0.1V, TOD is
measured from input transition to VOH -0.1V or VOL +0.1V;
VREF =VL.
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3.15V
VL
Standard
Load
Thevenin
Equivalent
R1
R2
RL
Output
Output
CL
CL
Figure 8 - PEEL™ Device and Array Test Loads
Technology
R1
R2
RL
VL
CL
CMOS
TTL
1.275V
1.840V
33 pF
33 pF
284 kΩ
308 Ω
258 kΩ
433 Ω
113 kΩ
180 Ω
Ordering Information
Part Number
Speed
Temperature
Package
PEEL18LV8ZP-25 (L)
PEEL18LV8ZPI-35 (L)
PEEL18LV8ZJ-25 (L)
PEEL18LV8ZJI-35 (L)
PEEL18LV8ZS-25 (L)
PEEL18LV8ZSI-35 (L)
PEEL18LV8ZT-25 (L)
PEEL18LV8ZTI-35 (L)
25ns
35ns
25ns
35ns
25ns
35ns
25ns
35ns
Commercial
Industrial
20-pin Plastic DIP
20-pin Plastic DIP
20-pin PLCC
Commercial
Industrial
20-pin PLCC
Commercial
Industrial
20-pin SOIC
20-pin SOIC
Commercial
Industrial
20-pin TSSOP
20-pin TSSOP
Part Number
Device
Suffix
PEELTM18LV8Z PI-35X
Lead Free
L : Lead Free Package
Blank : Normal
Package
P = 20-pin Plastic 300 mil DIP
Speed
J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
S = 20-pin SOIC 300 mil Gullwing
T = 20-pin TSSOP 170mil
-25 = 25ns tpd
-35 = 35ns tpd
Temperature Range
(Blank) = Commercial 0 to 70oC
I = Industrial -40 to 85oC
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Anachip Corp.
Head Office
Anachip USA
,
780 Montague Expressway, #201
San Jose, CA 95131
Tel: (408) 321-9600
Fax: (408) 321-9696
2F, No. 24-2, Industry E. Rd. IV, Science-Based
Industrial Park, Hsinchu, 300, Taiwan
Tel: +886-3-5678234
Fax: +886-3-5678368
Email: sales_usa@anachip.com
Website: http://www.anachip.com
©2004 Anachip Corporation
Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by
Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip
for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted
under any patents or patent rights of Anachip. Anachip’s products are not authorized for use as critical components in life
support devices or systems.
Marks bearing © or ™ are registered trademarks and trademarks of Anachip Corp.
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