PEEL18CV8ZP-25 [ANACHIP]
CMOS Programmable Electrically Erasable Logic Device; CMOS可编程电可擦除逻辑器件
| 型号： | PEEL18CV8ZP-25 |
| 厂家： | 
ANACHIP CORP |
| 描述： | CMOS Programmable Electrically Erasable Logic Device |
| 文件： | 总10页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PEEL™ 18CV8Z-25
CMOS Programmable Electrically Erasable Logic Device
Features
Ultra Low Power Operation
Architectural Flexibility
- Vcc = 5 Volts ±10%
-
-
-
-
-
-
-
-
-
Enhanced architecture fits in more logic
113 product terms x 36 input AND array
10 inputs and 8 I/O pins
- Icc = 10 µA (typical) at standby
- Icc = 2 mA (typical) at 1 MHz
CMOS Electrically Erasable Technology
12 possible macrocell configurations
Asynchronous clear, Synchronous preset
Independent output enables
- Superior factory testing
-
Reprogrammable in plastic package
-
Reduces retrofit and development costs
Programmable clock; pin 1 or p-term
Programmable clock polarity
Application Versatility
-
-
-
-
Replaces random logic
20 Pin DIP/SOIC/TSSOP and PLCC
Super set of standard PLDs
Pin and JEDEC compatible with 16V8
Ideal for use in power-sensitive systems
General Description
The PEEL™18CV8Z is logically and functionally similar to
Anachip’s 5 Volt PEEL™18CV8 and 3 Volt PEEL™18LV8Z.
The PEEL™18CV8Z is a Programmable Electrically Erasable
Logic (PEEL™) SPLD (Simple Programmable Logic Device)
that features ultra-low, automatic “zero” power-down operation.
The “zero power” (100 µA max. Icc) power-down mode makes the
PEEL™18CV8Z ideal for a broad range of battery-powered
portable equipment applications, from hand-held meters to PCM-
CIA modems. EE-reprogrammability provides both the conve-
nience of fast reprogramming for product development and quick
product personalization in manufacturing, including Engineering
Change Orders.
The
differences
between
the
PEEL™18CV8Z
and
PEEL™18CV8 include the addition of programmable clock
polarity, a product term clock, and variable width product terms in
the AND/OR Logic Array.
Like the PEEL™18CV8, the PEEL™18CV8Z is logical superset
of the industry standard PAL16V8 SPLD. The PEEL™18CV8Z
provides additional architectural features that allow more logic to
be incorporated into the design. Anachip’s JEDEC file translator
allows easy conversion of existing 20 pin PLD designs to the
PEEL™18CV8Z architecture without the need for redesign. The
PEEL™18CV8Z architecture allows it to replace over twenty
standard 20-pin DIP, SOIC, TSSOP and PLCC packages.
Figure 7 Pin Configuration
I/CLK
1
20
VCC
I
I
2
3
19
18
I/O
I/O
Figure 8 Block Diagram
I
I
4
5
17
16
I/O
I/O
I
I
6
7
15
14
I/O
I/O
I
I
8
9
13
12
11
I/O
I/O
I
CLK MUX (Optional)
GND
10
™
TSSOP
DIP
SOIC
PLCC
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under
any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10
Anachip Corp.
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Rev. 1.0 Dec 16, 2004
2/10
effect on the output function).
Function Description
Variable Product Term Distribution
The PEEL™18CV8Z implements logic functions as sum-of-
products expressions in a programmable-AND/fixed-OR logic
array. User-defined functions are created by programming the
connections of input signals into the array. User-configurable
output structures in the form of I/O macrocells further increase
logic flexibility.
The PEEL™18CV8Z provides 113 product terms to drive the
eight OR functions. These product terms are distributed among the
outputs in groups of 8, 10, 12, 14, and 16 to form logical sums
(see Figure 9). This distribution allows optimum use of the
device resources.
Architecture Overview
Programmable I/O Macrocell
The PEEL™18CV8Z architecture is illustrated in the block dia-
gram of Figure 8. Ten dedicated inputs and 8 I/Os provide up to
18 inputs and 8 outputs for creation of logic functions. At the core
of the device is a programmable electrically-erasable AND array
The unique twelve-configuration output macrocell provides com-
plete control over the architecture of each output. The ability to
configure each output independently lets you to tailor the config-
uration of the PEEL™18CV8Z to the precise requirements of
your design.
that drives
a fixed OR array. With this structure, the
PEEL™18CV8Z can implement up to eight sum-of-products
logic expressions.
Macrocell Architecture
Associated with each of the eight OR functions is an I/O macro-
cell that can be independently programmed to one of 12 different
configurations. The programmable macrocells allow each I/O to be
used to create sequential or combinatorial logic functions of
active-high or active-low polarity, while providing three different
feedback paths into the AND array.
Each I/O macrocell, as shown in Figure 9, consists of a D-type
flip-flop and two signal-select multiplexers. The configuration of
each macrocell is determined by the four EEPROM bits control-
ling these multiplexers. These bits determine output polarity, out-
put type (registered or non-registered) and input-feedback path
(bidirectional I/O, combinatorial feedback). Refer to Table 1 for
details.
AND/OR Logic Array
The programmable AND array of the PEEL™18CV8Z (shown in
Figure 9) is formed by input lines intersecting product terms. The
input lines and product terms are used as follows:
Equivalent circuits for the twelve macrocell configurations are
illustrated in Figure 11. In addition to emulating the four PAL-
type output structures (configurations 3, 4, 9, and 10), the macro-
cell provides eight additional configurations. When creating a
PEEL™ device design, the desired macrocell configuration is
generally specified explicitly in the design file. When the design is
assembled or compiled, the macrocell configuration bits are
defined in the last lines of the JEDEC programming file.
36 Input Lines:
– 20 input lines carry the true and complement of the signals
applied to the 10 input pins
– 16 additional lines carry the true and complement values of
feedback or input signals from the 8 I/Os
Output Type
113 product terms:
The signal from the OR array can be fed directly to the output pin
(combinatorial function) or latched in the D-type flip-flop (regis-
tered function). The D-type flip-flop latches data on the rising
edge of the clock and is controlled by the global preset and clear
terms. When the synchronous preset term is satisfied, the Q out-
put of the register is set HIGH at the next rising edge of the clock
input. Satisfying the asynchronous clear sets Q LOW, regardless of
the clock state. If both terms are satisfied simultaneously, the clear
will override the preset.
–
102 product terms are used to form sum of product functions
– 8 output enable terms (one for each I/O)
– 1 global synchronous preset term
– 1 global asynchronous clear term
– 1 programmable clock term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not there is a
logical connection at that intersection. Each product term is
essentially a 36-input AND gate. A product term that is con-
nected to both the true and complement of an input signal will
always be FALSE and thus will not affect the OR function that it
drives. When all the connections on a product term are opened, a
“don’t care” state exists and that term will always be TRUE. When
programming the PEEL™18CV8Z, the device program- mer first
performs a bulk erase to remove the previous pattern. The erase
cycle opens every logical connection in the array. The device is
configured to perform the user-defined function by pro- gramming
selected connections in the AND array. (Note that PEEL™
device programmers automatically program all of the connections
on unused product terms so that they will have no
Output Polarity
Each macrocell can be configured to implement active-high or
active-low logic. Programmable polarity eliminates the need for
external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled
under the control of its associated programmable output enable
product term. When the logical conditions programmed on the
output enable term are satisfied, the output signal is propagated to
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tion, registered feedback allows for the internal latching of states
without giving up the use of the external output.
the I/O pin. Otherwise, the output buffer is switched into the
high-impedance state.
Under the control of the output enable term, the I/O pin can func-
tion as a dedicated input, a dedicated output, or a bi-directional I/ O.
Opening every connection on the output enable term will per-
manently enable the output buffer and yield a dedicated output.
Conversely, if every connection is intact, the enable term will
always be logically false and the I/O will function as a dedicated
input.
Programmable Clock Options
A unique feature of the PEEL™18CV8Z is a programmable
clock multiplexer that allows the user to select true or comple-
ment forms of either input pin or product-term clock sources.
Zero Power Feature
The CMOS PEEL™18CV8Z features “Zero-Power” standby
operation for ultra-low power consumption. With the “Zero-
Power” feature, transition-detection circuitry monitors the inputs,
I/Os (including CLK) and feedbacks. If these signals do not
change for a period of time greater than approximately two tPD’s,
the outputs are latched in their current state and the device auto-
matically powers down. When the next signal transition is
detected, the device will “wake up” for active operation until the
signals stop switching long enough to trigger the next power-
down. (Note that the tPD is approximately 5 ns. slower on the first
transition from sleep mode.)
Input/Feedback Select
The PEEL™18CV8Z macrocell also provides control over the
feedback path. The input/feedback signal associated with each I/ O
macrocell can be obtained from three different locations; from the
I/O input pin, from the Q output of the flip-flop (registered
feedback), or directly from the OR gate (combinatorial feed-
back).
Bi-directional I/O
The input/feedback signal is taken from the I/O pin when using the
pin as a dedicated input or as a bi-directional I/O. (Note that it is
possible to create a registered output function with a bi-direc-
tional I/O, refer to Figure 9).
As a result of the “Zero-Power” feature, significant power sav-
ings can be realized for combinatorial or sequential operations
when the inputs or clock change at a modest rate. See Figure 5.
Combinatorial Feedback
Figure 10 Typical ICC vs. Input Clock Frequency
for the 18CV8Z
The signal-select multiplexer gives the macrocell the ability to
feedback the output of the OR gate, bypassing the output buffer,
regardless of whether the output function is registered or combi-
natorial. This feature allows the creation of asynchronous latches,
even when the output must be disabled. (Refer to configurations
5, 6, 7, and 8 in Figure 11.)
100
10
Figure 9 Block Diagram of the PEEL™18CV8Z
I/O Macrocell
1
Registered Feedback
0.1
Feedback also can be taken from the register, regardless of
whether the output function is programmed to be combinatorial
or registered. When implementing a combinatorial output func-
0.01
0.001
0.001
0.01
0.1
1
10
Frequency in MHz
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Configuration
Input/Feedback Select
Output Select
#
1
A
B
0
0
1
1
0
0
1
1
0
0
1
1
C
D
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
0
0
1
1
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Register
2
Bi-directional I/O
3
Combinatorial
Register
4
5
6
Combinatorial Feedback
Register Feedback
7
Combinatorial
Register
8
9
10
11
12
Combinatorial
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Design Security
Programming Support
The PEEL™18CV8Z provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs pro-
grammed into the device. The security bit is set by the PLD pro-
grammer, either at the conclusion of the programming cycle or as a
separate step, after the device has been programmed. Once the
security bit is set it is impossible to verify (read) or program the
PEEL™ until the entire device has first been erased with the
bulk-erase function.
Anachip’s JEDEC file translator allows easy conversion of exist-
ing 20 pin PLD designs to the PEEL™18CV8Z, without the need
for redesign. Anachip also offers (for free) its proprietary Win-
PLACE software, an easy-to-use entry level PC-based software
development system.
Programming support includes all the popular third party pro-
grammers such as BP Microsystems, System General, Logical
Devices, and numerous others.
Signature Word
The signature word feature allows a 64-bit code to be pro-
grammed into the PEEL™18CV8Z if the software option is used.
The code can be read back even after the security bit has been set.
The signature word can be used to identify the pattern pro-
grammed into the device or to record the design revision, etc.
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Rev. 1.0 Dec 16, 2004
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This device has been designed and tested for the specified
operating ranges. Improper operation outside of these levels is
not guaranteed. Exposure to absolute maximum ratings may
cause permanent damage.
Absolute Maximum Ratings
Symbol
Parameter
Conditions
Rating
Unit
VCC
VI , VO
IO
TST
TLT
Supply Voltage
Relative to Ground
-0.5 to +7.0
-0.5 to VCC+0.6
±25
V
V
mA
oC
oC
Voltage Applied to Any Pin2
Output Current
Relative to Ground1
Per Pin (IOL, IOH)
Storage Temperature
Lead Temperature
-65 to +150
Soldering 10 Seconds
+300
Operating Range
Symbol
Parameter
Conditions
Min
Max
Unit
Commercial
Industrial
Commercial
Industrial
See Note 3.
See Note 3.
See Note 3.
4.75
4.5
0
5.25
5.5
+70
+85
20
V
V
VCC
Supply Voltage
oC
oC
ns
ns
ms
TA
Ambient Temperature
-40
TR
TF
TRVCC
Clock Rise Time
Clock Fall Time
VCC Rise Time
20
250
D.C. Electrical Characteristics Over the operating range (Unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Unit
VOH
VOHC
VOL
VOLC
VIH
Output HIGH Voltage – TTL
Output HIGH Voltage – CMOS VCC = Min, IOH = -10.0µA
Output LOW Voltage – TTL
Output LOW Voltage – CMOS
Input HIGH Voltage
VCC = Min, IOH = -4.0 mA
2.4
VCC-0.3
V
V
V
V
V
VCC = Min, IOL = 16.0 mA
VCC = Min, IOL = 10.0µA
0.5
0.15
VCC+0.3
0.8
2.0
-0.3
VIL
Input LOW Voltage
V
IIL
ISC
Input and I/O Leakage Current
Output Short Circuit Current
VCC Current, Standby
VCC Current, f=1MHz
Input Capacitance
µA
mA
µA
mA
pF
pF
VCC=Max, GND≤VIN ≤VCC, I/O = High Z
VCC = Max, VO = 0.5V, TA = 25oC
±10
-135
100
5
6
12
9
-30
10 (typ)
2 (typ)
ICCS
VIN = 0V or VCC, All Outputs disabled4
VIN = 0V or VCC, All Outputs disabled4
10
ICC
7
CIN
COUT
TA = 25oC, VCC = Max @ f = 1 MHz
7
Output Capacitance
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Rev. 1.0 Dec 16, 2004
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-25 / I-25
Symbol
Parameter
Input5 to non-registered output
Units
Min
Max
25
25
tPD
tOE
tOD
ns
ns
ns
Input5 to output enable6
Input5 to output disable6
25
tCO1
tCO2
tCF
tSC
tHC
tCL, tCH
tCP
fMAX1
fMAX2
fMAX3
tAW
Clock to Output
15
35
9
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
Clock to comb. output delay via internal registered feedback
Clock to Feedback
Input5 or feedback setup to clock
Input5 hold after clock
15
0
13
Clock low time, clock high time8
Min clock period Ext (tSC + tCO1
Internal feedback (1/tSC + tCF)11
External feedback (1/tCP)11
No feedback (1/tCL + tCH)11
)
30
41.6
33.3
38.4
25
Asynchronous Reset Pulse Width
tAP
tAR
tRESET
Input5 to Asynchronous Reset
25
25
5
Asynchronous Reset recovery time
Power-on reset time for registers in clear state12
µs
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes:
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for peri-
ods less than 20 ns.
8. Test conditions assume: signal transition times of 3ns or less from the 10% and
90% points, timing reference levels of 1.5V (Unless otherwise specified).
9. Test one output at a time for a duration of less than 1 second.
10. ICC for a typical application: This parameter is tested with the device pro-
grammed as an 8-bit Counter.
2. VI and VO are not specified for program/verify operation.
3. Test Points for Clock and VCC in t
R and tF are referenced at the 10% and 90%
levels.
4. I/O pins are 0V and VCC
.
11. Parameters are not 100% tested. Specifications are based on initial character-
ization and are tested after any design process modification that might affect oper-
ational frequency.
5. “Input” refers to an input pin signal.
6. tOE is measured from input transition to VREF±0.1V,
TOD is measured from input transition to VOH-0.1V or VOL+0.1V; VREF=VL.
12. All input at GND.
7. Capacitances are tested on a sample basis.
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Rev. 1.0 Dec 16, 2004
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PEEL™ Device and Array Test Loads
Technology
R1
R2
RL
VL
CL
CMOS
TTL
480kΩ
235Ω
480kΩ
159Ω
228Ω
95Ω
2.375V
2.02V
33 pF
33 pF
Ordering Information
Part Number
Speed
Temperature
Package
PEEL18CV8ZP-25 (L)
PEEL18CV8ZJ-25 (L)
PEEL18CV8ZS-25 (L)
PEEL18CV8ZT-25 (L)
PEEL18CV8ZPI-25 (L)
PEEL18CV8ZJI-25 (L)
PEEL18CV8ZSI-25 (L)
PEEL18CV8ZTI-25 (L)
25ns
25ns
25ns
25ns
25ns
25ns
25ns
25ns
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
20-pin Plastic DIP
20-pin PLCC
20-pin SOIC
20-pin TSSOP
20-pin Plastic DIP
20-pin PLCC
20-pin SOIC
20-pin TSSOP
Part Number
Device
Suffix
PEELTM18CV8Z PI-25X
Lead Free
L : Lead Free Package
Blank : Normal
Package
P = 20-pin Plastic 300mil DIP
Speed
J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
S = 20-pin SOIC 300 mil Gullwing
T = 20-pin TSSOP 170mil
-25 = 25ns tpd
Temperature Range
(Blank) = Commercial 0 to 70oC
I = Industrial -40 to +85oC
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Rev. 1.0 Dec 16, 2004
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Anachip Corp.
Anachip USA
Head Office,
780 Montague Expressway, #201
San Jose, CA 95131
Tel: (408) 321-9600
Fax: (408) 321-9696
2F, No. 24-2, Industry E. Rd. IV, Science-Based
Industrial Park, Hsinchu, 300, Taiwan
Tel: +886-3-5678234
Fax: +886-3-5678368
Email: sales_usa@anachip.com
Website: http://www.anachip.com
©2004 Anachip Corp.
Anachip reserves the right to make changes in specifications at any time and without notice. The
information furnished by Anachip in this publication is believed to be accurate and reliable. However,
there is no responsibility assumed by Anachip for its use nor for any infringements of patents or other
rights of third parties resulting from its use. No license is granted under any patents or patent rights of
Anachip. Anachip’s products are not authorized for use as critical components in life support devices or
systems.
Marks bearing © or ™ are registered trademarks and trademarks of Anachip Corp.
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Rev. 1.0 Dec 16, 2004
10/10
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