AS1312 [AMSCO]
Ul t ra Low Quiescent Cur rent , Hysteret ic DC-DC Step-Up Conver ter; UL吨RA低静态姜黄素租金， Hysteret IC DC- DC升压器CONVER
| 型号： | AS1312 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Ul t ra Low Quiescent Cur rent , Hysteret ic DC-DC Step-Up Conver ter |
| 文件： | 总20页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS1312
Ultra Low Quiescent Current, Hysteretic DC-DC Step- Up Converter
1 General Description
The AS1312 is an ultra low IQ hysteretic step-up DC-DC converter.
2 Key Features
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Input voltage range: 0.7V to 5.0V
Fixed output voltage range: 2.5V to 5.0V
Peak output current: 200mA
The AS1312 achieves an efficiency of up to 94% and is designed to
operate from a +0.7V to +5.0V supply, the output voltage is fixed in
50mV steps from +2.5V to 5.0V.
Quiescent current: 1µA
In order to save power the AS1312 features a shutdown mode,
where it draws less than 100nA. In shutdown mode the battery is not
connected to the output.
Shutdown current: < 100nA
Up to 94% efficiency
If the input voltage exceeds the output voltage the device is in a
feedthrough mode and the input is directly connected to the output
voltage.
Output disconnect in shutdown
Feedthrough mode when VIN > VOUT
Adjustable low battery detection or Power-OK output selectable
No external diode or transistor required
Over temperature protection
In light load operation, the device enters a sleep mode when most of
the internal operating blocks are turned off in order to save power.
This mode is active approximately 50µs after a current pulse
provided that the output is in regulation.
Packages:
The AS1312 also offers an adjustable low battery detection. If the
battery voltage decreases below a threshold defined by two external
resistors on pin LBI, the LBO output is pulled to logic low. LBO is
working as Power-OK when LBI is connected to GND.
- 8-pin (2x2) TDFN
- 8-pin WL-CSP with 0.4mm pitch
The AS1312 is available in a 8-pin (2x2) TDFN and a 0.4mm pitch 8-
pin WL-CSP package.
3 Applications
The AS1312 is an ideal solution for handheld devices and battery
powered products.
Figure 1. AS1312 - Typical Application Diagram
L1 = 6.8µH
LX
V
IN
0.7V to 5.0V
Low Battery Detect
VIN
LBI
LBO
R
3
R
1
C1 = 22µF
V
OUT
2.5V to 5.0V
AS1312
VOUT
REF
R
2
C2 = 10µF
On
Off
EN
C
REF = 100nF
GND
www.ams.com/DC-DC_Step-Up
Revision 1.12
1 - 20
AS1312
Datasheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
8-pin WL-CSP
8-pin (2x2) TDFN
LBI
GND
1
2
3
4
8
7
6
5
VIN
EN
AS1312
LX
LBO
REF
VOUT
9
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Number
Pin Name
Description
WL-CSP
TDFN
Low Battery Comparator Input. 0.6V Threshold. May not be left floating. If connected to
GND, LBO is working as Power Output OK.
A1
1
LBI
Ground
A2
A3
2
3
GND
LX
External Inductor Connector.
Output Voltage. Decouple VOUT with a ceramic capacitor as close as possible to VOUT
and GND.
A4
4
VOUT
Reference Pin. Connect a 100nF ceramic capacitor to this pin.
Low Battery Comparator Output. Open-drain output.
B4
B3
5
6
REF
LBO
Enable Pin. Logic controlled shutdown input.
1 = Normal operation;
B2
7
EN
0 = Shutdown; shutdown current <100nA.
Battery Voltage Input. Decouple VIN with a ceramic capacitor as close as possible to VIN
and GND.
B1
-
8
9
VIN
NC
Exposed Pad. This pad is not connected internally. Can be left floating or connect to GND
to achieve an optimal thermal performance.
www.ams.com/DC-DC_Step-Up
Revision 1.12
2 - 20
AS1312
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Electrical Parameters
Min
Max
Units
Comments
VIN, VOUT, EN, LBI, LBO to GND
LX, REF to GND
-0.3
-0.3
-100
+7
V
V
V
OUT + 0.3
Input Current (latch-up immunity)
100
mA
Norm: JEDEC 78
Electrostatic Discharge
Electrostatic Discharge HBM
Temperature Ranges and Storage Conditions
TDFN
±2
kV
Norm: MIL 883 E method 3015
60
97
Junction-to-ambient thermal resistance is very
dependent on application and board-layout. In
situations where high maximum power dissipation
exists, special attention must be paid to thermal
dissipation during board design.
Thermal Resistance θJA
ºC/W
WL-CSP
Junction Temperature
+125
+150
+125
ºC
ºC
ºC
-55
-55
for 8-pin (2x2) TDFN
for 8-pin WL-CSP
Storage Temperature Range
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/
JEDEC J-STD-020“Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State Surface
Mount Devices”.
Package Body Temperature
+260
85
ºC
%
The lead finish for Pb-free leaded packages is matte
tin (100% Sn).
Humidity non-condensing
Moisture Sensitive Level
5
1
Represents a maximum floor life time of unlimited
www.ams.com/DC-DC_Step-Up
Revision 1.12
3 - 20
AS1312
Datasheet - Electrical Characteristics
6 Electrical Characteristics
All limits are guaranteed. The parameters with Min and Max values are guaranteed by production tests or SQC (Statistical Quality Control)
methods.
V
IN = 1.5V, C1 = C2 = 22µF, CREF = 100nF, Typical values are at TAMB = +25ºC. Unless otherwise specified. All limits are guaranteed. The
parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods.
Table 3. Electrical Characteristics
Symbol
Parameter
Conditions
Min
-40
-40
Typ
Max
85
Units
°C
TAMB
Operating Temperature Range
Operating Junction Temperature Range
T
J
125
°C
Input
V
IN
Input Voltage Range
0.7
5.0
V
V
Minimum Startup Voltage
TAMB = +25°C
0.9
Regulation
V
OUT
Output Voltage Range
2.5
-2
5.0
+2
+4
V
%
%
I
LOAD = 0mA to 10mA, TAMB = +25°C
ILOAD = 0mA to 10mA
-4
Output Voltage Tolerance
I
T
LOAD = 0mA to 30mA,
AMB = -20°C to +60°C
-2
+2
%
V
V
OUT Lockout Threshold1
Quiescent Current VIN
Rising Edge
2.45
Operating Current
V
OUT = 1.02xVOUTNOM,
100
nA
REF = 0.99xVOUTNOM, TAMB = +25°C
OUT = 5V, No load, TAMB = +25°C
AMB = +25ºC
IQ
Quiescent Current VOUT
V
0.7
1
1.3
µA
nA
ISHDN
Shutdown Current
T
100
Switches
NMOS
PMOS
0.4
0.45
4.0
Ω
Ω
R
ON
VOUT = 5V
NMOS maximum on-time
Peak current limit
Zero crossing current
3.3
5
4.6
35
µs
mA
mA
I
PEAK
400
20
Enable, Reference
V
ENH
ENL
EN input voltage ‘high’
EN input voltage ‘low’
EN input bias current
REF input bias current
0.7
V
V
V
0.1
100
100
IEN
EN = 5V, TAMB = +25°C
nA
nA
IREF
REF = 0.99xVOUTNOM, TAMB = +25°C
Low Battery & Power-OK
VLBI
LBI threshold
LBI hysteresis
Falling edge
0.57
0.6
25
0.63
V
mV
LBI ≤ VIN or VOUT (which ever is higher),
ILBI
LBI leakage current
LBO voltage low2
100
20
nA
T
AMB = +25°C
VLBO
ILBO = 1mA
5
mV
www.ams.com/DC-DC_Step-Up
Revision 1.12
4 - 20
AS1312
Datasheet - Electrical Characteristics
Table 3. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
91
Max
100
95
Units
nA
ILBO
LBO leakage current
Power-OK threshold
T
AMB = +25°C
LBI = 0V, Falling Edge
87
%
Thermal Protection
Thermal shutdown3
10°C Hysteresis
150
°C
1. The regulator is in startup mode until this voltage is reached.
Caution: Do not apply full load current until the device output > 2.5V
2. LBO goes low in startup mode as well as during normal operation if,
(i) The voltage at the LBI pin is higher than LBI threshold.
(ii) The voltage at the LBI pin is below 0.1V (connected to GND) and VOUT is below 92.5% of its nominal value.
3. Further switching is inhibited.
www.ams.com/DC-DC_Step-Up
Revision 1.12
5 - 20
AS1312
Datasheet - Typical Operating Characteristics
7 Typical Operating Characteristics
V
OUT = 5.0V, TAMB = +25°C, unless otherwise specified.
Figure 3. Efficiency vs. Output Current
Figure 4. Efficiency vs. Output Current
L1: LPS4018-682M
L1: XPL2010-682M
Figure 5. Efficiency vs. Input Voltage
Figure 6. Maximum Output Current vs. Input Voltage
L1: XPL2010-682M
Figure 7. Start-up Voltage vs. Output Current
Figure 8. Output Voltage Ripple; VIN = 2V, Rload = 100Ω
5µs/Div
www.ams.com/DC-DC_Step-Up
Revision 1.12
6 - 20
AS1312
Datasheet - Detailed Description
8 Detailed Description
8.1 Hysteretic Boost Converter
Hysteretic boost converters are so called because comparators are the active elements used to determine on-off timing via current and voltage
measurements. There is no continuously operating fixed oscillator, providing an independent timing reference. As a result, a hysteretic or
comparator based converter has a very low quiescent current. In addition, because there is no fixed timing reference, the operating frequency is
determined by external component (inductor and capacitors) and also the loading on the output.
Ripple at the output is an essential operating component. A power cycle is initiated when the output regulated voltage drops below the nominal
value of VOUT (0.99 x VOUT).
Inductor current is monitored by the control loop, ensuring that operation is always dis-continuous.
The application circuit shown in Figure 1 will support many requirements. However, further optimization may be useful, and the following is
offered as a guide to changing the passive components to more closely match the end requirement.
8.1.1 Input Loop Timing
The input loop consists of the source dc supply, the input capacitor, the main inductor, and the N-channel power switch. The on timing of the N-
channel switch is determined by a peak current measurement or a maximum on time. In the AS1312, peak current is 400mA (typ) and maximum
on time is 4.2µs (typ). Peak current measurement ensures that the on time varies as the input voltage varies. This imparts line regulation to the
converter.
The fixed on-time measurement is something of a safety feature to ensure that the power switch is never permanently on. The fixed on-time is
independent of input voltage changes. As a result, no line regulation exists.
Figure 9. Simplified Boost DCDC Architecture
L1
SW2
VIN
VOUT
Q
SW1
CIN
Q
COUT
FB
RLOAD
IPK
GND
0V
0V
On time of the power switch (Faraday’s Law) is given by:
LIPK
-----------------------------------------------------------------
TON
=
sec [volts, amps, ohms, Henry]
(EQ 1)
(EQ 2)
VIN – (IPKRSW1 + IPKRL1
)
Applying Min and Max values and neglecting the resistive voltage drop across L1 and SW1;
LMIN IPK _ MIN
TON _ MIN
=
=
VIN _ MAX
LMAX IPK _ MAX
VIN _ MIN
TON _ MAX
(EQ 3)
www.ams.com/DC-DC_Step-Up
Revision 1.12
7 - 20
AS1312
Datasheet - Detailed Description
Figure 10. Simplified Voltage and Current Waveforms
V
0.99VOUT_NOM
VOUT
VOUT Ripple
VIND_TOFF
B
C
B
C
VIN
0
VIND_TON
D
A
D
T
TOFF TWAIT
TON
TOFF TWAIT
IL
SW1_on
SW2_off
IPK
0
T
SW2_on
SW1_off
T
T
Another important relationship is the “volt-seconds” law. Expressed as following:
VONTON = VOFFTOFF
(EQ 4)
Voltages are those measured across the inductor during each time segment. Figure 10 shows this graphically with the shaded segments marked
“A & B”. Re-arranging (EQ 4):
TON
------------
TOFF
VOUT – VIN
----------------------------
VIN
=
(EQ 5)
The time segment called T
in Figure 10 is a measure of the “hold-up” time of the output capacitor. While the output voltage is above the
WAIT
threshold (0.99xVOUT), the output is assumed to be in regulation and no further switching occurs.
8.1.2 Inductor Choice Example
For the AS1312 V
= 0.9V, V
= 3.3V, (EQ 5) gives Ton=2.66T
.
IN_MIN
OUT_MAX
OFF
Let the maximum operating on-time = 1µs.
Note that this is shorter than the minimum limit on-time of 3.6µs. Therefore from (EQ 5), T
= 0.376µs. Using (EQ 3), L
is obtained:
MAX
OFF
L
MAX
= 1.875µH. The nearest preferred value is 2.2µH.
This value provides the maximum energy storage for the chosen fixed on-time limit at the minimum VIN
.
www.ams.com/DC-DC_Step-Up
Revision 1.12
8 - 20
AS1312
Datasheet - Detailed Description
Energy stored during the on time is given by:
2
E = 0,5L(IPK
)
Joules (Region A in Figure 10)
(EQ 6)
(EQ 7)
If the overall time period (T + T ) is T, the power taken from the input is:
ON
OFF
2
0,5L(IPK
--------------------------
Watts
)
PIN
=
T
Assume output power is 0.8 P to establish an initial value of operating period T.
IN
T
is determined by the time taken for the output voltage to fall to 0.99xV . The longer the wait time, the lower will be the supply current of
OUT
WAIT
the converter. Longer wait times require increased output capacitance. Choose T
= 10% T as a minimum starting point for maximum energy
WAIT
transfer. For very low power load applications, choose T
≥ 50% T.
WAIT
8.1.3 Output Loop Timing
The output loop consists of the main inductor, P-channel synchronous switch (or diode if fitted), output capacitor and load. When the input loop is
interrupted, the voltage on the LX pin rises (Lenz’s Law). At the same time a comparator enables the synchronous switch, and energy stored in
the inductor is transferred to the output capacitor and load. Inductor peak current supports the load and replenishes the charge lost from the
output capacitor. The magnitude of the current from the inductor is monitored, and as it approaches zero, the synchronous switch is turned off.
No switching action continues until the output voltage falls below the output reference point (0.99 x VOUT).
Output power is composed of the dc component (Region C in Figure 10):
IPKTOFF
IN-------------------
PREGION_C = V
(EQ 8)
(EQ 9)
2
T
Output power is also composed of the inductor component (Region B in Figure 10), neglecting efficiency loss:
2
0,5L(IPK
)
--------------------------
=
PREGION_B
T
Total power delivered to the load is the sum of (EQ 8) and (EQ 9):
2
IPKTOFF 0,5L(IPK
)
------------------- --------------------------
PTOTAL = VIN
+
(EQ 10)
(EQ 11)
2
T
T
From (EQ 3) (using nominal values) peak current is given by:
TONVIN
-------------------
L
IPK
=
Substituting (EQ 11) into (EQ 10) and re-arranging:
V2INT
ON
---------------------
PTOTAL
=
(0,9T)
(EQ 12)
2TL
0.9T incorporates a wait time T
= 10% T
WAIT
Output power in terms of regulated output voltage and load resistance is:
V2
RLOAD
OUT
----------------
POUT
=
(EQ 13)
(EQ 14)
Combining (EQ 12) and (EQ 13):
V2INT
V2
OUT
ON
----------------
---------------------
(0,9T)η
=
RLOAD
2TL
Symbol
η reflects total energy loss between input and output and is approximately 0.8 for these calculations. Use (EQ 14) to plot duty cycle
(T /T) changes for various output loadings and changes to VIN
ON
.
www.ams.com/DC-DC_Step-Up
Revision 1.12
9 - 20
AS1312
Datasheet - Detailed Description
8.1.4 Input Capacitor Selection
The input capacitor supports the triangular current during the on-time of the power switch, and maintains a broadly constant input voltage during
this time. The capacitance value is obtained from choosing a ripple voltage during the on-time of the power switch. Additionally, ripple voltage is
generated by the equivalent series resistance (ESR) of the capacitor. For worst case, use maximum peak current values from the datasheet.
IPEAKTON
-------------------------
CIN
=
(EQ 15)
VRIPPLE
= 50mV, EQ 15 yields:
Using T = 1µs, and I
= 400mA (typ), and V
RIPPLE
ON
PEAK
CIN = 8.0µF
Nearest preferred would be 10µF.
VPK _ RIPPLE _ ESR = IPK RESR
(EQ 16)
Typically, the ripple due to ESR is not dominant. ESR for the recommended capacitors (Murata GMR), ESR = 5m
Ω
to 10mΩ
. For the AS1312,
maximum peak current is 400mA. Ripple due to ESR is 2.0mV to 4.0mV.
Ripple at the input propagates through the common supply connections, and if too high in value can cause problems elsewhere in the system.
The input capacitance is an important component to get right.
8.1.5 Output Capacitor Selection
The output capacitor supports the triangular current during the off-time of the power switch (inductor discharge period), and also the load current
during the wait time (Region D in Figure 10) and on-time (Region A in Figure 10) of the power switch.
ILOAD (TON +TWAIT
)
COUT
=
(1− 0.99)VOUT _ NOM
(EQ 17)
Note: There is also a ripple component due to the equivalent series resistance (ESR) of the capacitor.
8.2 Summary
User Application Defines:
V
INmin, VINmax, VOUTmin, VOUTmax, I
min, I
max
LOAD
LOAD
Inductor Selection:
Select Max on-time = 0.5µs to 3µs for AS1312. Use (EQ 3) to calculate inductor value.
Use (EQ 5) to determine off-time.
Use (EQ 6) to check that power delivery matches load requirements assume 70% conversion efficiency.
Use (EQ 13) to find overall timing period value of T at min V and max V for maximum load conditions.
IN
OUT
Input Capacitor Selection: Choose a ripple value and use (EQ 14) to find the value.
Output Capacitor Selection: Determine T
via (EQ 6) or (EQ 13), and use (EQ 16) to find the value.
WAIT
www.ams.com/DC-DC_Step-Up
Revision 1.12
10 - 20
AS1312
Datasheet - Application Information
9 Application Information
The AS1312 is available with fixed output voltages from 2.5V to 5.0V in 50mV steps.
Figure 11. AS1312 - Block Diagram
0.7 to 5.0V
6.8µH
Zero
2.5V to 5.0V
Output
Input
Crossing
LX
VOUT
Detector
C
22µF
OUT
C
22µF
IN
Startup
Circuitry
Driver
and
R
3
VIN
LBI
Control
Logic
–
+
LBO
REF
Imax
Detection
V
REF
AS1312
EN
C
REF
100nF
GND
9.1 AS1312 Features
Shutdown.
The part is in shutdown mode while the voltage at pin EN is below 0.1V and is active when the voltage is higher than 0.7V.
Note: EN can be driven above VIN or VOUT, as long as it is limited to less than 5.0V.
Output Disconnect.
During shutdown VOUT is going to 0V and no current from the input source is running through the device.
Feedthrough Mode.
If the input voltage is higher than the output voltage (and the AS1312 is enabled) the supply voltage is connected to the load through the device.
To guarantee a proper function of the AS1312 it is not allowed that the supply exceeds the maximum allowed input voltage (5.0V).
In this feedthrough mode the quiescent current is 35µA (typ.). The device goes back into step-up mode when the output voltage is 4% (typ.)
below VOUTNOM
.
www.ams.com/DC-DC_Step-Up
Revision 1.12
11 - 20
AS1312
Datasheet - Application Information
9.1.1 Power-OK and Low-Battery-Detect Functionality
LBO goes low in startup mode as well as during normal operation if:
- The voltage at the LBI pin is below LBI threshold (0.6V). This can be used to monitor the battery voltage.
- LBI pin is connected to GND and VOUT is below 92.5% of its nominal value. LBO works as a power-OK signal in this case.
The LBI pin can be connected to a resistive-divider to monitor a particular definable voltage and compare it with a 0.6V internal reference. If LBI
is connected to GND an internal resistive-divider is activated and connected to the output. Therefore, the Power-OK functionality can be realized
with no additional external components.
The Power-OK feature is not active during shutdown and provides a power-on-reset function that can operate down to VIN = 0.7V. A capacitor to
GND may be added to generate a power-on-reset delay. To obtain a logic-level output, connect a pull-up resistor R
3
from pin LBO to pin VOUT
.
Larger values for this resistor will help to minimize current consumption; a 100kΩ resistor is perfect for most applications (see Figure 13 on page
12).
For the circuit shown in the left of Figure 12, the input bias current into LBI is very low, permitting large-value resistor-divider networks while
maintaining accuracy. Place the resistor-divider network as close to the device as possible. Use a defined resistor for R
2 and then calculate R1
as:
VIN
----------
R1 = R2
– 1
(EQ 18)
VLBI
Where:
is 0.6V
V
LBI
Figure 12. Typical Application with adjustable Battery Monitoring
L1
6.8µH
LX
3
VIN
0.7V to 5.0V
Low Battery Detect
8
6
VIN
LBO
R
3
C1
R1
22µF
V
OUT
4
1
2.5V to 5.0V
AS1312
VOUT
LBI
C
22µF
2
R
2
5
On
Off
7
REF
EN
C
REF
100nF
GND
2
Figure 13. Typical Application with LBO working as Power-OK
L1
6.8µH
LX
3
V
IN
0.7V to 5.0V
Low Battery Detect
8
6
VIN
LBO
R
3
C1
22µF
V
OUT
4
1
2.5V to 5.0V
AS1312
VOUT
LBI
C
2
22µF
5
On
Off
7
REF
EN
CREF
100nF
GND
2
www.ams.com/DC-DC_Step-Up
Revision 1.12
12 - 20
AS1312
Datasheet - Application Information
9.1.2 Thermal Shutdown
To prevent the AS1312 from short-term misuse and overload conditions the chip includes a thermal overload protection. To block the normal
operation mode all further switching is inhibited for output voltage above VOUT lockout threshold. The device is in thermal shutdown when the
junction temperature exceeds 150°C. To resume the normal operation the temperature has to drop below 140°C.
A good thermal path has to be provided to dissipate the heat generated within the package. Otherwise it’s not possible to operate the AS1312 at
its usable maximal power. To dissipate as much heat as possible from the package into a copper plane with as much area as possible, it’s
recommended to use multiple vias in the printed circuit board. It’s also recommended to solder the Exposed Pad (pin 9) to the GND plane.
Note: Continuing operation in thermal overload conditions may damage the device and is considered bad practice.
9.2 Component Selection
Only four components are required to complete the design of the step-up converter. The low peak currents of the AS1312 allow the use of low
value, low profile inductors and tiny external ceramic capacitors.
9.3 Inductor Selection
For best efficiency, choose an inductor with high frequency core material, such as ferrite, to reduce core losses. The inductor should have low
DCR (DC resistance) to reduce the I²R losses, and must be able to handle the peak inductor current without saturating. A 6.8µH inductor with a
> 500mA current rating and < 500mΩ DCR is recommended.
Table 4. Recommended Inductors
Part Number
L
DCR
Current Rating
0.62A
Dimensions (L/W/T)
2.0x1.9x1.0mm
2.0x2.0x1.4mm
3.0x3.0x1.5mm
3.3x3.3x1.3mm
3.9x3.9x1.7mm
3.2x2.5x1.55mm
3.0x3.0x1.1mm
4.0x4.0x1.1mm
Manufacturer
XPL2010-682M
EPL2014-682M
6.8µH
6.8µH
6.8µH
6.8µH
6.8µH
6.8µH
6.8µH
6.8µH
421m
287m
300m
240m
150m
250m
210m
143m
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
0.59A
Coilcraft
www.coilcraft.com
LPS3015-682M
0.86A
LPS3314-682M
0.9A
LPS4018-682M
1.3A
LQH32CN6R8M53L
LQH3NPN6R8NJ0L
LQH44PN6R8MJ0L
0.54A
Murata
www.murata.com
0.7A
0.72A
9.4 Capacitor Selection
The convertor requires three capacitors. Ceramic X5R or X7R types will minimize ESL and ESR while maintaining capacitance at rated voltage
over temperature. The VIN capacitor should be 22µF. The VOUT capacitor should be between 22µF and 47µF. A larger output capacitor should
be used if lower peak to peak output voltage ripple is desired. A larger output capacitor will also improve load regulation on VOUT. See Table 5
for a list of capacitors for input and output capacitor selection.
Table 5. Recommended Input and Output Capacitors
Part Number
C
TC Code
X5R
Rated Voltage
6.3V
Dimensions (L/W/T)
0805, T=1.25mm
1206, T=1.6mm
Manufacturer
GRM21BR60J226ME99
GRM31CR61C226KE15
GRM31CR60J475KA01
22µF
22µF
47µF
Murata
www.murata.com
X5R
16V
X5R
6.3V
1206, T=1.6mm
On the pin REF a 100nF capacitor with an Insulation resistance >1GΩ is recommended.
Table 6. Recommended Capacitors for REF
Insulation
Resistance
Rated
Voltage
Part Number
C
TC Code
Dimensions (L/W/T)
Manufacturer
Murata
www.murata.com
GRM188R71C104KA01
100nF
X7R
>5GΩ
16V
0603, T=0.8mm
www.ams.com/DC-DC_Step-Up
Revision 1.12
13 - 20
AS1312
Datasheet - Application Information
9.5 Layout Considerations
Relatively high peak currents of 400mA (typ) circulate during normal operation of the AS1312. Long printed circuit tracks can generate additional
ripple and noise that mask correct operation and prove difficult to “de-bug” during production testing. Referring to Figure 1, the input loop formed
by C1, VIN and GND pins should be minimized. Similarly, the output loop formed by C2, VOUT and GND should also be minimized. Ideally both
loops should connect to GND in a “star” fashion. Finally, it is important to return CREF to the GND pin directly.
www.ams.com/DC-DC_Step-Up
Revision 1.12
14 - 20
AS1312
Datasheet
10 Package Drawings and Markings
The device is available in a 8-pin (2x2) TDFN and 8-pin WL-CSP package.
Figure 14. 8-pin (2x2) TDFNMarking
XXX
YY
Figure 15. 8-pin WL-CSP Marking
YY
XXXX
Table 7. Packaging Code
XXX
XXXX
encoded datecode for WL-CSP
YY
encoded datecode for TDFN
marketing code
www.ams.com/DC-DC_Step-Up
Revision 1.12
15 - 20
AS1312
Datasheet - Package Drawings and Markings
Figure 16. 8-pin (2x2) TDFN Drawings and Dimensions
Symbol
A
Min
0.51
0.00
Nom
0.55
Max
0.60
0.05
A1
A3
L
0.02
0.15 REF
0.325
0.25
0.225
0.18
0.425
0.30
b
D
2.00 BSC
2.00 BSC
0.50 BSC
1.60
E
e
D2
E2
aaa
bbb
ccc
ddd
eee
fff
1.45
1.70
0.75
0.90
1.00
-
-
0.15
-
-
-
-
-
-
0.10
0.10
-
-
-
0.05
0.08
0.10
N
8
Notes:
1. Dimensioning & tolerancing conform to ASME Y14.5M-1994
.
2. All dimensions are in millimeters. Angles are in degrees.
3. Coplanarity applies to the exposed heat slug as well as the terminal.
4. Radius on terminal is optional.
5. N is the total number of terminals.
www.ams.com/DC-DC_Step-Up
Revision 1.12
16 - 20
AS1312
Datasheet - Package Drawings and Markings
Figure 17. 8-pin WL-CSP Drawings and Dimensions
www.ams.com/DC-DC_Step-Up
Revision 1.12
17 - 20
AS1312
Datasheet - Package Drawings and Markings
Revision History
Revision
1.0
Date
Owner
Description
Initial revision
1.5
Updated Detailed Description and Application Information sections
26 Mar, 2012
1.6
Detailed Description section updated
1.7
27 Apr, 2012
19 Jul, 2012
afe
Added info on Thermal resistance, conditions for Output Voltage Tolerance.
Updated ordering table.
1.8
Updated storage temp values for WL-CSP
1.9
10 Aug, 2012
17 Aug, 2012
14 Sep, 2012
14 Oct, 2013
Updated (EQ 17)
1.10
1.11
1.12
Updated conditions for ‘Output Voltage Tolerance’ parameter (see page 4)
Update Green & ROHS logo, update ordering information
tka
Note: Typos may not be explicitly mentioned under revision history.
www.ams.com/DC-DC_Step-Up
Revision 1.12
18 - 20
AS1312
Datasheet - Ordering Information
11 Ordering Information
The device is available as the standard products listed below.
Table 8. Ordering Information
Ordering Code
AS1312-BTDT-50
AS1312-BTDT-33
AS1312-BWLT-50
AS1312-BWLT-45
Marking
BE
V
OUT
Description
Delivery Form
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Package
5.0V
3.3V
5.0V
4.5V
8-pin (2x2) TDFN
8-pin (2x2) TDFN
8-pin WL-CSP
8-pin WL-CSP
BX
Ultra Low Quiescent Current, Hysteretic DC-DC
Step-Up Converter
BF
BQ
1
tbd
xx
Tape and Reel
tbd
AS1312
1. Non-standard devices from 2.5V to 5.0V are available in 50mV steps.
For more information and inquiries contact http://www.ams.com/contact
All products are RoHS compliant and ams green.
Buy our products or get free samples online at www.ams.com/ICdirect
Technical Support is available at www.ams.com/Technical-Support
For further information and requests, email us at sales@ams.com
(or) find your local distributor at www.ams.com/distributor
www.ams.com/DC-DC_Step-Up
Revision 1.12
19 - 20
AS1312
Datasheet - Ordering Information
Copyrights
Copyright © 1997-2012, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights
reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the
copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal
commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability
applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing
by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third
party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other
services.
Contact Information
Headquarters
ams AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel : +43 (0) 3136 500 0
Fax : +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.ams.com/contact
www.ams.com/DC-DC_Step-Up
Revision 1.12
20 - 20
相关型号：
©2020 ICPDF网 联系我们和版权申明