N04Q1618C2BW-70C [AMI]
Standard SRAM, 256KX16, 70ns, CMOS, WAFER;![N04Q1618C2BW-70C](http://pdffile.icpdf.com/pdf2/p00238/img/icpdf/N04Q1618C2BB_1397549_icpdf.jpg)
型号: | N04Q1618C2BW-70C |
厂家: | ![]() |
描述: | Standard SRAM, 256KX16, 70ns, CMOS, WAFER 静态存储器 内存集成电路 |
文件: | 总13页 (文件大小:305K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AMI Semiconductor, Inc.
N04Q1618C2B
ULP Memory Solutions
670 North McCarthy Blvd. Suite 220
Milpitas, CA 95035
Advance Information
PH: 408-935-7777, FAX: 408-935-7770
4Mb Ultra-Low Power Asynchronous CMOS SRAM w/ Dual
Vcc and VccQ for Ultimate Power Reduction
256K×16 bit POWER SAVER TECHNOLOGY
Overview
Features
The N04Q16yyC2B are ultra-low power memory
devices containing a 4 Mbit Static Random Access
Memory organized as 262,144 words by 16 bits.
The device is designed and fabricated using AMI
Semiconductor’s advanced CMOS technology to
provide ultra-low active and standby power. The
device operates with two chip enable (CE1 and
CE2) controls and output enable (OE) to allow for
easy memory expansion. Byte controls (UB and
LB) allow the upper and lower bytes to be
• Multiple Power Supply Ranges
1.1V - 1.3V
1.65V - 1.95V
• Dual Vcc / VccQ Power Supplies
1.2V Vcc with 3V VccQ
1.8V Vcc with 3V VccQ
• Very low standby current
50nA typical for 1.2V operation
• Very low operating current
accessed independently. The 4Mb SRAM is
optimized for the ultimate in low power and is
suited for various applications where ultra-low-
power is critical such as medical applications,
battery backup and power sensitive hand-held
devices. The unique page mode operation saves
active operating power and the dual power supply
rails allow very low voltage operation while
400µA typical for 1.2V operation at 1µs
• Very low Page Mode operating current
80µA typical for 1.2V operation at 1µs
• Simple memory control
Dual Chip Enables (CE1 and CE2)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
maintaining 3V I/O capability. The device can
• Automatic power down to standby mode
• BGA, TSOP and KGD options
• RoHS Compliant
o
operate over a very wide temperature range of 0 C
o
to +70 C for the lowest power and is also available
o
o
in the industrial range of -40 C to +85 C. The
devices are available in standard BGA and TSOP
packages. The devices are also available as
Known Good Die (KGD) for embedded package
applications.
Product Options
Typical
Vcc
(V)
VccQ
Speed
(nS)
Typical
Operating
Part Number
Standby
Current
(V)
Operating Current Temperature
N04Q1612C2Bx-15C1
N04Q1618C2Bx-15C1
N04Q1618C2Bx-70C
N04Q1618C2Bx-85C
50nA
50nA
1.2
1.2, 1.8, 3.0
150ns
150ns
70ns
0.4 mA @ 1MHz
0.4 mA @ 1MHz
0oC to +70oC
0.6 mA @ 1MHz
200nA
200nA
1.8
1.8, 3.0
85ns
0.6 mA @ 1MHz
1. Part numbers are under development. Please contact your local sales representative for details.
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
1
N04Q1618C2B
AMI Semiconductor, Inc.
Pin Configurations (4Mb)
Advance Information
1
2
3
A0
4
A1
5
A2
6
A4
1
PIN
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
2
ONE
A6
LB
OE
CE2
A
B
C
D
E
F
A2
3
A7
A1
4
OE
I/O8
A3
A4
A6
A7
I/O0
UB
CE1
A0
5
UB
CE1
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
6
LB
7
I/O15
I/O14
I/O13
I/O12
VSS
VCCQ
I/O11
I/O10
I/O9
I/O8
CE2
A8
I/O9 I/O10 A5
VSS I/O11 A17
I/O1 I/O2
I/O3 VCC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VCCQ I/O12
I/O14 I/O13 A14
A16 I/O4 VSS
A15 I/O5 I/O6
NC
I/O15
NC
A12
A9
A13
A10
I/O7
NC
NC
A8
WE
A11
G
H
A9
A10
A11
48 Pin BGA (top)
A17
TSOP II
Pin Descriptions
Pin Name
A0-A17
WE
CE1
CE2
OE
Pin Function
Address Inputs
Write Enable Input
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
LB
UB
I/O0-I/O7
Lower Byte Enable Input
Upper Byte Enable Input
Lower Byte Data Input/Output
I/O8-I/O15
VCC
Upper Byte Data Input/Output
Core Power
VCCQ
VSS
Power for I/O
Core Ground
NC
Not Connected
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
2
N04Q1618C2B
AMI Semiconductor, Inc.
Functional Block Diagram
Advance Information
Word
Address
Inputs
Address
Decode
Logic
(A1 - A4)
Input/
Address
Inputs
Page
4Mb
Output
Mux
I/O0 - I/O7
Address
Decode
Logic
RAM Array
and
(A0, A5 - A17)
Buffers
I/O8 - I/O15
CE1
CE2
WE
OE
Control
Logic
UB
LB
Functional Description
1
UB1
LB1
CE1
CE2
WE
OE
MODE
POWER
I/O0 - I/O15
Standby2
Standby2
H
X
L
L
L
L
X
L
H
H
H
H
X
X
X
L
X
X
X
X3
L
X
X
H
L1
L1
L1
X
X
H
L1
L1
L1
High Z
High Z
High Z
Data In
Data Out
High Z
Standby
Standby
Standby
Active
Standby
Write3
Read
Active
H
H
Active
H
Active
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
1
Capacitance
Item
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN = 0V, f = 1 MHz, TA = 25oC
VIN = 0V, f = 1 MHz, TA = 25oC
Input Capacitance
I/O Capacitance
CI/O
8
pF
1. These parameters are verified in device characterization and are not 100% tested
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
3
N04Q1618C2B
AMI Semiconductor, Inc.
Advance Information
1
Absolute Maximum Ratings
Item
Symbol
VIN,OUT
VCC
Rating
Unit
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
–0.3 to VCC+0.3
–0.3 to 4
V
V
PD
500
mW
oC
oC
oC
TSTG
Storage Temperature
–40 to 125
TA
Operating Temperature
-40 to +85
260oC, 10sec
TSOLDER
Soldering Temperature and Time
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
o
o
Operating Characteristics (Over Specified Temperature Range, 0 - 70 C)
Item
Symbol
Device
Conditions
Min.
Typ
Max
Unit
N04Q1612...
N04Q1618...
N04Q1612...
N04Q1618...
1.2V Core Device
1.8V Core Device
1.2V Core Device
1.8V Core Device
1.1
1.65
1.1
1.65
0.8 x
VCCQ
1.2
1.8
1.3
1.95
3.3
VCC
Core Supply Voltage
V
VCCQ
I/O Supply Voltage
V
V
3.3
VIH
VIL
VCC+0.3
Input High Voltage
Input Low Voltage
0.2 x
VCCQ
–0.3
VOH
VOL
ILI
IOH = -100uA
IOL = 100uA
VCC–0.2
Output High Voltage
Output Low Voltage
Input Leakage Current
V
V
0.2
0.5
VIN = 0 to VCC
µA
OE = VIH or Chip
Disabled
ILO
Output Leakage Current
0.5
µA
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
4
N04Q1618C2B
AMI Semiconductor, Inc.
Advance Information
Power Consumption (TA = 0oC - 70oC)
Typ1
Device PN
Speed
Max
Chip Disabled
Standby Current2
N04Q1612C2Bx-
Isb
Icc
50
500
nA
V
CC = 1.3V, VIN = VCC or 0
1us
150ns
1us
0.4
2
80
300
0.5
3
100
450
Chip Enabled, IOUT = 0
VCC=1.3V, VIN=VIH or VIL
Read/Write Current3
15C
mA
Chip Enabled, IOUT = 0
VCC=1.3V, VIN=VIH or VIL
Page Mode Current
Iccp
µA
150ns
Chip Disabled
Standby Current
Isb
Icc
50
500
nA
V
CC = 1.9V, VIN = VCC or 0V
1us
150ns
1us
0.4
2
80
400
0.5
3
100
500
Chip Enabled, IOUT = 0
CC=1.9V, VIN=VIH or VIL
N04Q1618C2Bx-
Read/Write Current
mA
V
15C
Chip Enabled, IOUT = 0
VCC=1.9V, VIN=VIH or VIL
Page Mode Current
Iccp
µA
150ns
Chip Disabled
Standby Current
Isb
Icc
0.2
0.6
6
1.5
0.9
7
µA
V
CC = 1.9V, VIN = VCC or 0
1us
70ns
85ns
Chip Enabled, IOUT = 0
VCC=1.9V, VIN=VIH or VIL
Read/Write Current
N04Q1618C2Bx-
mA
70C/85C
1us
70ns
85ns
0.1
0.8
0.2
1
Chip Enabled, IOUT = 0
VCC=1.9V, VIN=VIH or VIL
Page Mode Current
Iccp
mA
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested.
2. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all
inputs must be within 0.2 volts of either VCC or VSS. This applies to all ISB values.
3. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system. This applies to all Icc and Iccp values.
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
5
N04Q1618C2B
AMI Semiconductor, Inc.
Advance Information
Power Savings with Page Mode Operation (WE = V )
IH
Page Address
Open page
(A0, A5-A17)
Word Address
...
Word 16
Word 1
Word 2
(A1-A4)
CE1
CE2
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A1 - A4 as the least
significant bits and addressing the 16 words within the open page, power is reduced to the page mode
value which is considerably lower than standard operating currents for low power SRAMs.
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
6
N04Q1618C2B
AMI Semiconductor, Inc.
Timing Test Conditions
Advance Information
Item
0.1VCC to 0.9 VCC
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
5ns
0.5 VCC
CL = 30pF
0 to +70oC
Operating Temperature
Timing
-70
-85
-150
Max.
Units
Item
Symbol
Min.
Max.
Min.
Max.
Min.
tRC
tAA
Read Cycle Time
70
85
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
70
70
70
35
70
85
85
85
45
85
150
150
150
75
tAAP
tCO
tOE
tBE
Page Mode Address Access Time
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
150
tLZ
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
10
5
10
5
10
5
tOLZ
tBZ
10
0
10
0
10
0
tHZ
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
20
20
20
20
20
20
20
20
20
tOHZ
tBHZ
tOH
0
0
0
0
0
0
10
10
10
ns
tWC
tCW
tAW
tBW,
tWP
tAS
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
70
50
50
50
40
0
85
60
60
60
50
0
150
120
120
120
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
tWR
tWHZ
tDW
tDH
Write Recovery Time
0
0
0
Write to High-Z Output
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
20
20
20
40
0
50
0
100
0
tOW
5
5
5
ns
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
7
N04Q1618C2B
AMI Semiconductor, Inc.
Timing of Read Cycle (CE1 = OE = V , WE = CE2 = V )
Advance Information
IL
IH
t
RC
Address
t
AA
t
OH
Previous Data Valid
Data Valid
Data Out
Timing Waveform of Read Cycle (WE=V )
IH
t
RC
Address
t
AA
t
HZ
CE1
CE2
t
CO
t
LZ
t
OHZ
t
OE
OE
t
OLZ
t
BE
LB, UB
t
t
BHZ
BLZ
High-Z
Data Valid
Data Out
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
8
N04Q1618C2B
AMI Semiconductor, Inc.
Timing Waveform of Page Mode Read Cycle (WE = V )
Advance Information
IH
t
RC
Page Address
Word Address
t
AAP
t
AA
t
HZ
CE1
CE2
t
CO
t
OHZ
t
OE
OE
t
OLZ
t
LB, UB
BE
t
BHZ
t
BLZ
High-Z
Data Out
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
9
N04Q1618C2B
AMI Semiconductor, Inc.
Advance Information
Timing Waveform of Write Cycle (WE control)
t
WC
Address
t
WR
t
AW
CE1
CE2
t
CW
t
BW
LB, UB
WE
t
t
AS
WP
t
t
DH
DW
High-Z
Data Valid
Data In
t
WHZ
t
OW
High-Z
Data Out
Timing Waveform of Write Cycle (CE1 Control)
t
WC
Address
t
t
AW
WR
t
CE1
CW
(for CE2 Control, use
inverted signal)
t
AS
t
BW
LB, UB
WE
t
t
WP
t
t
DH
DW
Data Valid
Data In
t
LZ
WHZ
High-Z
Data Out
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
10
N04Q1618C2B
AMI Semiconductor, Inc.
Advance Information
44-Lead TSOP II Package (T44)
18.41±0.13
11.76±0.20
10.16±0.13
0.80mm REF
0.45
0.30
SEE DETAIL B
DETAIL B
1.10±0.15
o
o
0 -8
0.20
0.00
0.80mm REF
Note:
1. All dimensions in inches (Millimeters)
2. Package dimensions exclude molding flash
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
11
N04Q1618C2B
AMI Semiconductor, Inc.
Ball Grid Array Package
Advance Information
0.28±0.05
1.24±0.10
D
A1 BALL PAD
CORNER (3)
1. 0.35±0.05 DIA.
E
2. SEATING PLANE - Z
0.15
Z
0.05
Z
TOP VIEW
SIDE VIEW
1. DIMENSION IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER.
PARALLEL TO PRIMARY Z.
A1 BALL PAD
CORNER
SD
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
e
SE
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
K TYP
J TYP
e
BOTTOM VIEW
Dimensions (mm)
e = 0.75
BALL
D
E
MATRIX
TYPE
SD
SE
J
K
6±0.10
8±0.10
0.375
0.375
1.125
1.375
FULL
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
12
N04Q1618C2B
AMI Semiconductor, Inc.
Ordering Information
Advance Information
N04Q16 XX C2B X - XX X
C = 0oC - 70oC
Temperature
70 = 70ns
85 = 85ns
Performance
15 = 150ns (under development)
T2 = 44-pin TSOP II Green (RoHS Compliant)
B2 = 48-ball BGA Green (RoHS Compliant)
W = Wafer (KGD)
Package Type
12 = 1.2V (under development)
18 = 1.8V
Operating Voltage
Q = Low Power SRAM with VccQ for dual rail operation
Revision History
Revision
Date
Change Description
A
October 2005
Initial Advanced Release
Raised maximum Vcc to 3.6V for 3V device
B
February 2006
Added green packages
Changed dual rail to ‘Q’ part designator
Seperated 1,8V dual rail and 3V single rail
C
D
July 2006
Updated VccQ for TSOP
September 2006
Converted to AMI Semiconductor
© 2006 AMI Semiconductor, Inc. All rights reserved.
AMI Semiconductor, Inc. ("AMIS") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.
AMIS does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur-
poses only and they vary depending upon specific applications.
AMIS makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does AMIS assume any liability arising out of the application or use of
any product or circuit described herein. AMIS does not authorize use of its products as critical components in any application in which the failure of the AMIS product may be
expected to result in significant injury or death, including life support systems and critical medical instruments.
Stock No. 23451-D 11/06
The specification is ADVANCE INFORMATION and subject to change without notice.
13
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AMI
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![](http://pdffile.icpdf.com/pdf1/p00107/img/page/N04Q1612C2BB-15I_578803_files/N04Q1612C2BB-15I_578803_2.jpg)
N04Q1625C2BB-15C
4Mb Ultra-Low Power Asynchronous CMOS SRAM w/ Dual Vcc and VccQ for Ultimate Power Reduction 256K】16 bit POWER SAVER TECHNOLOGY
NANOAMP
![](http://pdffile.icpdf.com/pdf1/p00107/img/page/N04Q1612C2BB-15I_578803_files/N04Q1612C2BB-15I_578803_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00107/img/page/N04Q1612C2BB-15I_578803_files/N04Q1612C2BB-15I_578803_2.jpg)
N04Q1625C2BB-15I
4Mb Ultra-Low Power Asynchronous CMOS SRAM w/ Dual Vcc and VccQ for Ultimate Power Reduction 256K】16 bit POWER SAVER TECHNOLOGY
NANOAMP
![](http://pdffile.icpdf.com/pdf1/p00107/img/page/N04Q1612C2BB-15I_578803_files/N04Q1612C2BB-15I_578803_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00107/img/page/N04Q1612C2BB-15I_578803_files/N04Q1612C2BB-15I_578803_2.jpg)
N04Q1625C2BB-70C
4Mb Ultra-Low Power Asynchronous CMOS SRAM w/ Dual Vcc and VccQ for Ultimate Power Reduction 256K】16 bit POWER SAVER TECHNOLOGY
NANOAMP
![](http://pdffile.icpdf.com/pdf1/p00107/img/page/N04Q1612C2BB-15I_578803_files/N04Q1612C2BB-15I_578803_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00107/img/page/N04Q1612C2BB-15I_578803_files/N04Q1612C2BB-15I_578803_2.jpg)
N04Q1625C2BB-70I
4Mb Ultra-Low Power Asynchronous CMOS SRAM w/ Dual Vcc and VccQ for Ultimate Power Reduction 256K】16 bit POWER SAVER TECHNOLOGY
NANOAMP
![](http://pdffile.icpdf.com/pdf1/p00107/img/page/N04Q1612C2BB-15I_578803_files/N04Q1612C2BB-15I_578803_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00107/img/page/N04Q1612C2BB-15I_578803_files/N04Q1612C2BB-15I_578803_2.jpg)
N04Q1625C2BB2-15C
4Mb Ultra-Low Power Asynchronous CMOS SRAM w/ Dual Vcc and VccQ for Ultimate Power Reduction 256K】16 bit POWER SAVER TECHNOLOGY
NANOAMP
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