11995-203 [AMI]
Processor Specific Clock Generator, 133.33MHz, CMOS, PDSO48, 6.10 MM, TSSOP-48;
| 型号： | 11995-203 |
| 厂家： | 
AMI SEMICONDUCTOR |
| 描述： | Processor Specific Clock Generator, 133.33MHz, CMOS, PDSO48, 6.10 MM, TSSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总14页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
Figure 1: Block Diagram
1.0 Features
XIN
VDD_R
REF_0:1
VSS_R
•
Generates all clocks required for single-processor
Crystal
platforms, including:
Oscillator
XOUT
M
M
M
M
M
M
Two differential current-mode Host clock pairs
Three 66.67MHz 3.3V CK66 clock outputs
Ten 33.3MHz 3.3V PCI clock outputs
Two 3.3V Memory Reference clock outputs
Two 48MHz 3.3V CK48 clock outputs
adjust
ISEL_0:1
IREF
VDD_H
HOST_P1:2
÷1
÷2
PWR_DWN#
SS_EN#
HOST_N1:2
VSS_H
VDD_66
CK66_0:2
VSS_66
SSCG
PLL
÷3
÷4
Two buffered copies of the crystal reference
SEL133/100#
SEL_A:B
•
•
•
Control of current-mode Host clocks via IREF current
Control
programming pin and ISEL_0:1 current multiplier pins
VDD_P
PCI_0:7
VSS_P
delay
÷2
Host clock frequency selection via the SEL_A,
SEL_B, and SEL133/100# pins
Active-low PWR_DWN# signal allows one complete
clock cycle on each clock outputs and then shuts
down the crystal oscillator, PLLs, and outputs
VDD_M
MREF_P
MREF_N
VSS_M
VDD_48
CK48_0:1
VSS_48
÷4
PLL
•
•
•
Spread-spectrum modulation (-0.5% at 31.5kHz) of
SSCG PLL clocks, enabled via SS_EN# input
FS6233
Supports test mode and tristate output control to fa-
cilitate board testing
Available in a 48-pin SSOP and TSSOP
Figure 2: Pin Configuration
REF_1 / ISEL_1
VDD_R
XIN
1
2
3
4
5
6
7
8
9
48 REF_0 / ISEL_0
47 VSS_R
Table 1: Clock Parameters
46 VDD_M
45 MREF_P
44 MREF_N
43 VSS_M
42 SS_EN#
41 HOST_P1
40 HOST_N1
39 VDD_H
38 HOST_P2
37 HOST_N2
36 VSS_H
CLOCK
#
SUPPLY
SUPPLY FREQ.
XOUT
PHASE SKEW
GROUP PINS VOLTAGE GROUP
(MHz)
VSS_P
PCI_0
HOST_P
HOST_N
2
2
0°
150ps
133.33
100.00
PCI_1
3.3V
3.3V
VDD_H
VDD_M
Pair to
180°
VDD_P
PCI_2
Pair
MREF_P
MREF_N
CK66
PCI
CK48
1
1
3
10
2
2
0°
180°
0°
66.67
50.00
PCI_3 10
VSS_P 11
-
PCI_4 12
3.3V
3.3V
3.3V
3.3V
VDD_66
VDD_P
VDD_48 48.008
VDD_R 14.318
66.67
33.33
250ps
PCI_5 13
0°
300ps
VDD_P 14
35 IREF
0°
0°
-
-
PCI_6 15
34 VDD
REF
PCI_7 16
33 VSS
VSS_P 17
32 PWR_DWN#
31 VDD_66
30 CK66_0
29 CK66_1
28 VSS_66
27 CK66_2
26 VDD_66
25 VDD_48
PCI_8 18
Table 2: Clock Offsets
PCI_9 19
VDD_P 20
RELATION
PHASE
MIN
TYP
MAX
SEL133/100# 21
VSS_48 22
CK48_0 / SEL_A 23
CK48_1 / SEL_B 24
CK66 leads PCI
0°
1.5ns
3.5ns
Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
9.18.00
IntRGR
ISO9001
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
Table 3: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
TYPE
NAME
DESCRIPTION
SUPPLY
CK48_0
SEL_A
CK48_1
SEL_B
CK66_0:3
HOST_P1
HOST_N1
One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL
One of two latched inputs that select the HOST and MREF output frequency
One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL
One of two latched inputs that select the HOST and MREF output frequency
Three 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL
48
DIO
VDD_48
24
DIO
VDD_48
30, 29, 27
41, 40
DO
AO
VDD_66
VDD_H
Host clock pair #1; one of two pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1
HOST_P2
HOST_N2
38, 37
35
AO
AI
Host clock pair #2; one of two pairs of current-steering differential current-mode outputs
VDD_H
VDD
A fixed precision resistor from this pin to ground provides a reference current used for the dif-
ferential current-mode HOST clock outputs
IREF
One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver
One clock in a pair of outputs provided as a reference clock to a memory clock driver
44
45
DO
DO
MREF_N
MREF_P
VDD_M
VDD_M
6, 7, 9, 10,
12, 13, 15,
16, 18, 19
DO
DI
PCI_0:9
Ten 3.3V 33.3MHz PCI clocks, lagging the CK66 clock by 1.5 to 3.5ns
VDD_P
Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins.
One of two 3.3V buffered copies of the crystal reference frequency clock
One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs
One of two 3.3V buffered copies of the crystal reference frequency clock
32
PWR_DWN#
REF_0
VDD_48
2
DIO
DIO
VDD_R
VDD_R
ISEL_0
REF_1
1
One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs
ISEL_1
21
42
34
25
DI
DI
P
P
P
P
P
P
P
P
P
P
P
P
P
P
AI
AO
SEL133/100# Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency
VDD_48
VDD_M
SS_EN#
VDD
Active low spread-spectrum enable turns on spread spectrum modulation
3.3V core power supply
-
-
-
-
-
-
-
-
-
VDD_48
VDD_66
VDD_H
VDD_M
VDD_P
VDD_R
VSS
3.3V power supply for CK48 clock outputs
3.3V power supply for CK66 clock outputs
3.3V power supply for the differential HOST clock outputs
3.3V power supply for MREF clock outputs
3.3V power supply for PCI clock outputs
3.3V power supply for the REF clock output and the crystal oscillator
Core ground
26, 31
39
46
8, 14, 20
2
33
22
28
36
43
VSS_48
VSS_66
VSS_H
VSS_M
VSS_P
VSS_R
XIN
Ground for the CK48 clock outputs
Ground for the CK66 clock outputs
Ground for the differential HOST clock outputs
Ground for the MREF clock outputs
Ground for the PCI clock outputs
-
-
-
-
5, 11, 17
47
3
4
Ground for the REF clock outputs and the crystal oscillator
14.318MHz crystal oscillator input
VDD_R
VDD_R
XOUT
14.318MHz crystal oscillator output
9.18.00
ISO9001
2
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
2.0 Programming Information
Table 4: Function/Clock Enable Configuration
CONTROL INPUTS (1)
CLOCK OUTPUTS (MHz)
PWR_
DWN#
SEL
HOST_P
1:2
HOST_N
1:2
MREF_P,
MREF_N
CK66_
0:2
PCI_
0:9
CK48_
0:1
SEL_A SEL_B
REF
133/100#
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100.00
reserved
reserved
tristate
100.00
reserved
reserved
tristate
50.00
reserved
reserved
tristate
66.67
reserved
reserved
tristate
33.33
reserved
reserved
tristate
48.008
reserved
reserved
tristate
14.318
reserved
reserved
tristate
14.318
reserved
reserved
XIN
133.33
133.33
66.67
66.67
33.33
48.008
reserved
reserved
XIN ÷ 2
reserved
reserved
XIN ÷ 2
reserved
reserved
XIN ÷ 4
reserved
reserved
XIN ÷ 4
reserved
reserved
XIN ÷ 8
reserved
reserved
XIN ÷ 2
2 × IREF
0
X
X
X
tristate
low
low
low
low
low
1.
It is expected that the Control Inputs will be defined on power-up and will not change during normal operation.
Table 5: Synthesis Error
3.0 HOST Buffer Current Control
The current supplied at the HOST outputs is controlled by
TARGET
ACTUAL
(MHz)
DEVIATION
(ppm)
CLOCK
(MHz)
two parameters:
1) the value of the programming resistor from the IREF
pin to ground (VSS), and
100.0000
133.3333
50.0000
66.6667
66.6667
33.3333
48.000
99.9963
133.3072
49.9982
66.6536
66.6642
33.3321
48.008
-36.657
-195.924
-36.657
-195.924
-36.657
-36.657
+167
HOST_P1:2,
HOST_N1:2
2) the multiplier factor determined by the logic setting of
MREF_P,
MREF_N
the ISEL_0 and ISEL_1 pins.
CK66
PCI
3.1
Current Reference
The HOST output current is a mirrored and scaled copy
of the reference current flowing through the programming
resistor on the IREF pin. Conceptually, the circuit given in
Figure 2 shows how the mirror current is generated.
CK48 (1)
1.
2.
48MHz USB clock is required to be +167ppm off from 48.000MHz to conform to USB
standards.
Spread spectrum is disabled
The voltage that appears at the IREF pin is one-third of
the voltage at the VDD_I pin. The reference current is
1
× VDD_I
3
IREF
=
.
RIREF
3.2
Current Scaling
The mirrored reference current can be increased by
adding one or more copies of the mirror current together.
The additional current is controlled by the logic settings
on the ISEL_0 and ISEL_1 pins.
9.18.00
ISO9001
3
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
Table 6: Current Multiplier
Table 8: HOST Buffer Clock Outputs
ISEL_0
ISEL_1
MULTPLIER
HIGH DRIVE CURRENT (mA)
AT PRIMARY SYSTEM CONFIGURATION
Output
Voltage (V)
IO = 5 × IREF
IO = 6 × IREF
IO = 4 × IREF
IO = 7 × IREF
0
0
1
1
0
1
0
1
MIN.
TYP.
MAX.
3.30
3.14
2.97
2.81
2.64
2.48
2.31
2.14
1.98
1.81
1.65
1.48
1.32
1.15
0.99
0.82
0.66
0.49
0.33
0.16
0.00
0.00
-3.03
-5.66
-7.87
0.00
-4.22
-7.68
0.00
-5.76
-9.86
-10.30
-11.91
-12.56
-12.85
-13.07
-13.26
-13.42
-13.54
-13.64
-13.70
-13.73
-13.75
-13.76
-13.78
-13.79
-13.80
-13.81
-13.82
-11.85
-12.45
-12.84
-13.16
-13.45
-13.72
-13.96
-14.17
-14.36
-14.52
-14.64
-14.71
-14.74
-14.76
-14.78
-14.80
-14.82
-14.83
Figure 2: Current Reference Circuit
-9.67
VDD_I (3.3V)
-11.05
-11.98
-12.52
-12.77
-12.91
-12.99
-13.04
-13.07
-13.08
-13.09
-13.11
-13.12
-13.13
-13.13
-13.14
-13.15
Additional
Mirror
2R
R
1.1V
Current
Mirror
ISEL_0:1
Current
IREF
HOST_N
HOST_P
RS
RP
RS
RP
Reference
RIREF
Current IREF
Table 7: HOST Current Selection
PROGRAM REFERENCE
CURRENT
MULTIPLIER IMPEDANCE VOLTAGE
TRACE
OUTPUT
RESISTOR
RIREF
CURRENT
IREF
Output Voltage (V)
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
60Ω
50Ω
30Ω
25Ω
30Ω
25Ω
30Ω
25Ω
30Ω
25Ω
0.71V
0.59V
0.85V
0.71V
0.56V
0.47V
0.99V
0.82V
0.75V
0.62V
0.90V
0.75V
0.60V
0.50V
1.05V
0.84V
0
1
2
3
475Ω (1%)
475Ω (1%)
475Ω (1%)
475Ω (1%)
221Ω (1%)
221Ω (1%)
221Ω (1%)
221Ω (1%)
IO = 5 × IREF
IO = 6 × IREF
IO = 4 × IREF
IO = 7 × IREF
IO = 5 × IREF
IO = 6 × IREF
IO = 4 × IREF
IO = 7 × IREF
2.32mA
2.32mA
2.32mA
2.32mA
5mA
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
5mA
30Ω
50Ω
90Ω
5mA
Max VOH
5mA
NOTE: Shaded row indicates the Primary System Configuration
Data in this table represents nominal characterization data only
9.18.00
ISO9001
4
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
Table 9: Latency Table
4.0 Power Management
The PWR_DWN# signal is an asynchronous, active-low
LVTTL input that places the device in a low power inac-
tive state without removing power from the device. All
internal clocks are turned off, and all clock outputs are
held low.
Since PWR_DWN# is asynchronous, the signal is syn-
chronized internally to each individual clock. As shown in
Figure 3, a falling-rising-falling edge sequence on any
individual clock output is required before that clock output
is disabled low. This edge sequence ensures that one
complete clock cycle will occur before the clock stops.
LATENCY
MIN.
SIGNAL
STATE
SIGNAL
MAX.
Output:
Device:
2 clocks
3 clocks
Power
OFF
0
1
2× REF
3× REF clocks
PWR_
DWN#
clocks
Power
ON
3ms
Upon the release of PWR_DWN# (power-up), external
circuitry should allow a minimum of 3ms for the PLL to
lock before enabling any clocks.
Figure 3: PWR_DWN# Timing
Any Clock
(internal)
PWR_DWN#
Any Clock
(output)
After REF
3ms until clock is valid
output shuts off...
VCO
Crystal
Oscillator
Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.
Figure 4: I/O Pin Programming
5.0 Dual Function I/O Pins
Device Solder
Pads
Several pins on this device serve as dual function in-
put/output pins. During the initial application of VDD to
the device, this type of pin functions as an input pin.
Upon completion of power-up, the logic state present on
the pin is latched internally, and the pin is converted to an
output driver.
An external 10kΩ pull-down resistor to ground is required
for a logic low and a 10kΩ pull-up resistor to the clock
output VDD is required for a logic high. The 10kΩ resistor
presents an insignificant load to the output driver that
should not affect the output clock.
Termination
Resistor
Clock Trace
10k
Ω
Programming
Resistor
Ground or
Power Via
Note that the latching of the logic state occurs only on the
application of the chip supply voltage (VDD). The logic
state on the pin is not latched if the PWR_DWN# signal is
used to power-down the device with VDD still applied.
9.18.00
ISO9001
5
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
6.0 Electrical Specifications
Table 10: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage (VSS = ground)
Input Voltage, dc
Output Voltage, dc
Input Clamp Current, dc (VI < 0 or VI > VDD
Output Clamp Current, dc (VI < 0 or VI > VDD
Storage Temperature Range (non-condensing)
Ambient Temperature Range, Under Bias
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
VDD
VI
VO
IIK
IOK
TS
TA
TJ
VSS-0.5
VSS-0.5
VSS-0.5
-50
-50
-65
7
VDD+0.5
VDD+0.5
50
50
150
125
125
260
2
V
V
V
mA
mA
°C
°C
°C
°C
kV
)
)
-55
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.
Table 11: Operating Conditions
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
Core (VDD)
Clock Buffers (VDD_48, VDD_66, VDD_H,
VDD_M, VDD_P, VDD_R)
MIN.
TYP.
MAX.
UNITS
3.135
3.3
3.465
Supply Voltage
VDD
V
3.135
3.3
3.465
Operating Temperature Range
Crystal Resonator Frequency
Crystal Resonator Load Capacitance
TA
fXTAL
CXL
0
14.316
13.5
10
70
14.32
22.5
30
°C
MHz
pF
14.318
18
XIN, XOUT pins
MREF_P, MREF_N
PCI_0:9
10
30
Load Capacitance
CL
CK66_0:2
10
30
pF
CK48_0:1
10
20
REF_0:1
10
20
HOST_P1 to HOST_P2,
HOST_N1 to HOST_N2
Ω
Load Resistance
RL
20
105
HOST_P1 to HOST_P2,
HOST_N1 to HOST_N2
Maximum High-Level Output Voltage
VOH
1.20
V
9.18.00
ISO9001
6
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
Table 12: DC Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
fHOST = 133MHz; all supplies = 3.465V,
Supply Current, Dynamic, with Loaded
Outputs
IDD
mA
R
IREF= 475Ω, IOH = 6 × IREF
PWR_DWN# low, all supplies = 3.465V,
µA
Supply Current, Static
IDDs
RIREF= 475Ω, IOH = 6 × IREF
Digital Inputs (PWR_DWN#, SEL133/100#, SS_EN#)
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
VIH
VIL
IIL
2.0
VSS-0.3
-5
VDD+0.3
0.8
+5
V
V
µA
Crystal Oscillator Feedback (XIN)
Threshold Bias Voltage
High-Level Input Current
Low-Level Input Current
VTH
IIH
1.5
32
V
µA
µA
VIH = 3.3V
VIL = 0V
IIL
-32
As seen by an external crystal connected to
XIN and XOUT
As seen by an external clock driver on
XOUT; XIN unconnected
Crystal Loading Capacitance *
Input Loading Capacitance *
CL(xtal)
CL(XIN)
13.5
18
36
22.5
pF
pF
Crystal Oscillator Drive (XOUT)
High Level Output Source Current
Low Level Output Sink Current
Current Reference (IREF)
Bias Voltage
IOH
IOL
VI (XIN) = 3.3V, VO = 0V
VI (XIN) = 0V, VO = 3.3V
-8.0
8.7
mA
mA
VOH
IOH
no load
VO = 0V
1.1
V
mA
Short Circuit Output Source Current
MREF_P, MREF_N, CK66_0:2, PCI_0:9 Clock Outputs (Type 5)
VDD_M, VDD_66, VDD_P = 3.135V,
IOH min
IOH max
IOL min
IOL max
-33
30
VO = 1.0V
High Level Output Source Current
mA
VDD_M, VDD_66, VDD_P = 3.465V,
VO = 3.135V
VDD_M, VDD_66, VDD_P = 3.135V,
VO = 1.95V
VDD_M, VDD_66, VDD_P = 3.465V,
VO = 0.4V
-33
38
Low Level Output Sink Current
Output Impedance
mA
zOL
zOH
IOZ
IOSH
IOSL
Measured at 1.65V, output driving low
Measured at 1.65V, output driving high
12
12
-10
55
55
10
Ω
µA
mA
mA
Tristate Output Current
Short Circuit Output Source Current
Short Circuit Output Sink Current
VO = 0V; shorted for 30s, max.
VO = 3.3V; shorted for 30s, max.
-51
62
9.18.00
ISO9001
7
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
Table 13: DC Electrical Specifications, continued
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
HOST_P1:2, HOST_N1:2 Clock Outputs (Type X1)
RS = 33.2Ω, RP = 49.9Ω,
Crossover Voltage
VX
IOH
45
55
%VOH
mA
RIREF = 475Ω, IOH = 6 × IREF
VO = 0.65V, RIREF = 475Ω, IOH = 6 × IREF
VO = 0.74V, RIREF = 475Ω, IOH = 6 × IREF
VDD = 3.3V, over settings in Table 7
VDD_I = 3.3V±5%, over settings in Table 7
12.9
High-Level Output Source Current
14.9
+7
+12
-7
-12
∆IOH
Output Source Current Tolerance
%IOH
∆VO/∆IO, where VO1 = 1.0V, VO2 = VSS
,
Ω
Output Impedance
zOH
IOZ
3000
-10
RIREF = 475Ω, IOH = 6 × IREF
µA
Tristate Output Current
10
REF_0 / ISEL_0, REF_1 / ISEL_1 Clock Driver I/O, (Type 3)
CK48_0 / SEL_A, CK48_1 / SEL_B Clock Driver I/O (Type 3)
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
VIH
VIL
IIH
2.0
VSS-0.3
VDD+0.3
0.8
5
V
V
µA
µA
mA
mA
Low-Level Input Current (pull-up)
High Level Output Source Current
Low Level Output Sink Current
IIL
IOH
IOL
zOL
zOH
IOZ
IOSH
IOSL
VIL = 0.4V
-9
-32
13
VDD_R, VDD_48 = 3.465V, VO = 2.4V
VDD_R, VDD_48 = 3.465V, VO = 0.4V
Measured at 1.65V, output driving low
Measured at 1.65V, output driving high
20
20
-10
60
60
10
Ω
Output Impedance
µA
mA
mA
Tristate Output Current
Short Circuit Output Source Current
Short Circuit Output Sink Current
VO = 0V; shorted for 30s, max.
VO = 3.3V; shorted for 30s, max.
-41
40
Figure 5: DC Measurement Points
Figure 6: Timing Diagram
3.3V
tr
tf
VOH = 2.4V
3.3V
VIH = 2.0V
2.4V
1.5V
VIL = 0.8V
VOL = 0.4V
0.4V
dt
Figure 7: HOST Clock Measurement Point
Figure 8: HOST Clock Test Point
HOST_P
Test node
From output
under test
RS
VX
RP
HOST_N
9.18.00
ISO9001
8
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
Table 14: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Spread Spectrum Modulation
Frequency *
Spread Spectrum Modulation
Index *
fm
SS_EN# low
31.5
-0.5
kHz
%
δm
SS_EN# low
CK66 leads @ 1.5V, CL=30pF to PCI @ 1.5V,
CL = 30pF (measured on rising edges)
Clock Offset
tpd
1.5
3.5
ns
Output Tristate Enable Delay *
Output Tristate Disable Delay *
Power-up PLL Lock Time
tDZL, tDZH
tDLZ, tDHZ
tL
SEL_A:B = 00, SEL133/100# = 0
SEL_A:B = 11, SEL133/100# = 0
via PWR_DWN#
1.0
1.0
10
10
3.0
ns
ns
ms
HOST_P1:2, HOST_N1:2 Clock Outputs
HOST pair to HOST pair @ VX, RIREF = 475Ω,
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω
Clock Skew *
tsk(o)
dt
tj(∆P)
tr
150
55
ps
%
Ratio of high pulse width to one clock period at VX,
Duty Cycle *
45
RIREF = 475Ω, IOH = 6 × IREF, RS=33.2Ω, RP=49.9Ω
Rising edge to rising edge at VX, RIREF = 475Ω,
IOH = 6 × IREF RS = 33.2Ω, RP = 49.9Ω
Jitter, Period (peak-peak) *
Rise Time *
200
450
20
ps
ps
%
Measured at 20% – 80% of VOH; RIREF = 475Ω,
IOH = 6 × IREF RS = 33.2Ω, RP = 49.9Ω
175
Measured at 20% – 80% of VOH; RIREF = 475Ω,
IOH = 6 × IREF RS = 33.2Ω, RP = 49.9Ω
Rise/Fall Time Matching*
MREF_P, MREF_N Clock Outputs
Duty Cycle *
Ratio of high pulse width to one clock period,
measured at 1.5V
dt
45
55
%
tj(∆P)
tr min
tr max
tf min
tf max
Jitter, Period (peak-peak) *
From rising edge to rising edge at 1.5V, CL=30pF
Measured @ 0.4V – 2.4V; CL=10pF
Measured @ 0.4V – 2.4V; CL=30pF
Measured @ 2.4V – 0.4V; CL=10pF
Measured @ 2.4V – 0.4V; CL=30pF
250
ps
0.4
0.4
Rise Time *
Fall Time *
ns
ns
1.6
1.6
9.18.00
ISO9001
9
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
Table 15: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
PCI_0:9 Clock Outputs
Duty Cycle *
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Ratio of high pulse width to one clock period,
measured at 1.5V
dt
45
55
%
Clock Skew *
Jitter, Period (peak-peak) *
tsk(o)
tj(∆P)
tr min
tr max
tf min
tf max
One clock output relative to another at 1.5V
From rising edge to rising edge at 1.5V, CL = 30pF
Measured at 0.4V – 2.4V; CL = 10pF
Measured at 0.4V – 2.4V; CL = 30pF
Measured at 2.4V – 0.4V; CL = 10pF
Measured at 2.4V – 0.4V; CL = 30pF
500
500
ps
ps
0.5
0.5
Rise Time *
Fall Time *
ns
ns
2.0
2.0
CK66_0:2 Clock Outputs
Ratio of high pulse width to one clock period,
measured at 1.5V
Duty Cycle *
dt
45
55
%
Clock Skew *
Jitter, Period (peak-peak) *
tsk(o)
tj(∆P)
tr min
tr max
tf min
tf max
One clock output relative to another at 1.5V
From rising edge to rising edge at 1.5V, CL = 30pF
Measured at 0.4V – 2.4V; CL = 10pF
Measured at 0.4V – 2.4V; CL = 30pF
Measured at 2.4V – 0.4V; CL = 10pF
Measured at 2.4V – 0.4V; CL = 30pF
250
300
ps
ps
0.5
0.5
Rise Time *
Fall Time *
ns
ns
2.0
2.0
REF_0:1 Clock Outputs
Duty Cycle *
Ratio of high pulse width to one clock period,
measured at 1.5V
dt
45
55
%
tj(∆P)
tr min
tr max
tf min
tf max
Jitter, Period (peak-peak) *
From rising edge to rising edge at 1.5V, CL = 20pF
Measured at 0.4V – 2.4V; CL = 10pF
Measured at 0.4V – 2.4V; CL = 20pF
Measured at 2.4V – 0.4V; CL = 10pF
Measured at 2.4V – 0.4V; CL = 20pF
1000
ps
1.0
1.0
Rise Time *
Fall Time *
ns
ns
4.0
4.0
CK48_0:1 Clock Outputs
Duty Cycle *
Ratio of high pulse width to one clock period,
measured at 1.5V
dt
45
55
%
tj(∆P)
tr min
tr max
tf min
tf max
Jitter, Period (peak-peak) *
From rising edge to rising edge at 1.5V, CL = 20pF
Measured at 0.4V – 2.4V; CL = 10pF
Measured at 0.4V – 2.4V; CL = 20pF
Measured at 2.4V – 0.4V; CL = 10pF
Measured at 2.4V – 0.4V; CL = 20pF
350
ps
1.0
1.0
Rise Time *
Fall Time *
ns
ns
4.0
4.0
9.18.00
ISO9001
10
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
Table 16: MCLK_P, MCLK_N, PCI_0:9, CK66_0:2 Clock Outputs
High Drive Current (mA)
Low Drive Current (mA)
Voltage
(V)
Voltage
(V)
150
125
100
75
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0
0
0
0
24
45
64
79
92
103
112
117
120
121
122
123
123
124
124
124
125
0
-49
-48
-48
-47
-47
-46
-46
-45
-43
-41
-37
-33
-28
-22
-14
-6
-83
-83
-82
-81
-80
-79
-78
-76
-74
-70
-65
-59
-52
-43
-32
-20
-7
-132
-131
-130
-129
-127
-126
-124
-121
-117
-112
-105
-97
-87
-74
-60
-45
-27
-7
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
11
21
30
37
43
47
50
53
54
55
55
55
56
56
56
17
32
45
56
65
73
78
82
84
85
85
86
86
86
87
87
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
50
25
0
0
0.5
1
1.5
2
2.5
3
3.5
-25
-50
-75
-100
-125
-150
30Ω
50Ω
90Ω
Output Voltage (V)
Data in this table represents nominal characterization data only
Table 17: REF_0:1, CK48_0:1 Clock Outputs
High Drive Current (mA)
Low Drive Current (mA)
Voltage
(V)
Voltage
(V)
120
100
80
60
40
20
0
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0
0
8
0
0
0
-38
-37
-37
-37
-36
-36
-35
-34
-33
-31
-29
-25
-21
-17
-11
-5
-64
-64
-63
-63
-62
-61
-60
-59
-57
-54
-50
-46
-40
-33
-25
-16
-6
-102
-101
-100
-99
-98
-97
-95
-93
-90
-87
-81
-75
-67
-57
-47
-34
-21
-5
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
13
24
33
41
48
53
57
60
61
62
63
63
63
63
64
64
18
33
47
58
68
76
82
86
88
89
90
90
90
91
91
91
91
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
15
22
27
31
35
37
39
39
40
40
41
41
41
41
0
0.5
1
1.5
2
2.5
3
3.5
-20
-40
-60
-80
-100
-120
30Ω
50Ω
90Ω
Output Voltage (V)
Data in this table represents nominal characterization data only
9.18.00
ISO9001
11
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
7.0 Package Information
Table 18: 48-pin SSOP (0.300") Package Dimensions
48
DIMENSIONS
INCHES MILLIMETERS
MIN.
MAX.
MIN.
MAX.
A
A1
b
0.095
0.008
0.008
0.005
0.620
0.395
0.291
0.110
0.016
0.0135
0.010
0.630
0.420
0.299
2.41
0.20
0.20
2.79
0.41
0.34
E1
E
AMERICAN MICROSYSTEMS, INC.
c
0.13
0.25
D
E
E1
e
h
L
15.75
10.03
7.39
16.00
10.67
7.59
1
SEATING PLANE
A
b
e
h × 45°
0.025 BSC
0.64 BSC
0.015
0.020
0°
0.025
0.040
8°
0.38
0.51
0°
0.64
1.01
8°
c
L
D
θ
A1
θ
Table 19: 48-pin SSOP (0.300") Package Characteristics
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
TYP.
UNITS
ΘJA
L11
L12
L13
C11
C12
C13
Thermal Impedance, Junction to Free-Air
Lead Inductance, Self
Air flow = 0 m/s
Longest lead
93
5.5
3.0
°C/W
nH
Longest lead to any 1st adjacent lead
Longest lead to any 2nd adjacent lead
Longest lead to VSS
Lead Inductance, Mutual
Lead Capacitance, Bulk
Lead Capacitance, Mutual
nH
pF
pF
2.1
0.94
0.46
0.05
Longest lead to any 1st adjacent lead
Longest lead to any 2nd adjacent lead
9.18.00
ISO9001
12
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
Table 20: 48-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS
48
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
A
A1
b
c
D
E
-
0.047
0.006
0.011
0.008
0.496
-
1.20
0.15
0.27
0.20
12.60
0.002
0.0067
0.0035
0.488
0.05
0.17
0.09
12.40
E1
E
AMERICAN MICROSYSTEMS, INC.
0.318 BSC
8.10 BSC
E1
e
L
0.236
0.019 BSC
0.018
0.008
0°
0.244
6.00
0.50 BSC
0.45
0.20
0°
6.20
1
SEATING PLANE
0.030
-
8°
0.75
-
8°
b
e
S
θ2
θ3
c
S
A
θ1
θ2
θ3
L
θ1
D
A1
12° REF
12° REF
12° REF
12° REF
Table 21: 48-pin TSSOP (6.1mm) Package Characteristics
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
TYP.
UNITS
ΘJA
L11
L12
L13
C11
C12
C13
Thermal Impedance, Junction to Free-Air
Lead Inductance, Self
Air flow = 0 m/s
Longest lead
89
°C/W
nH
3.50
1.82
1.17
0.63
0.30
0.03
Longest lead to any 1st adjacent lead
Longest lead to any 2nd adjacent lead
Longest lead to VSS
Lead Inductance, Mutual
Lead Capacitance, Bulk
Lead Capacitance, Mutual
nH
pF
pF
Longest lead to any 1st adjacent lead
Longest lead to any 2nd adjacent lead
9.18.00
ISO9001
13
FS6233-01
AMERICAN MICROSYSTEMS, INC.
Motherboard Clock Generator IC
September 2000
8.0 Ordering Information
Table 22: Device Ordering Codes
OPERATING
TEMPERATURE RANGE
SHIPPING
CONFIGURATION
DEVICE NUMBER
ORDERING CODE
PACKAGE TYPE
11995-202
11995-212
11995-203
11995-213
Tape and Reel
Tubes
48-pin (0.300”) SSOP
0°C to 70°C (Commercial)
FS6233-01
Tape and Reel
Tubes
48-pin (6.1mm) TSSOP
Copyright © 2000 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-
serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-
ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-
mended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Address: http://www.amis.com E-mail: tgp@amis.com
9.18.00
ISO9001
14
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