LP62S2048AV-70LLIF [AMICC]
SRAM;
| 型号： | LP62S2048AV-70LLIF |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | SRAM 静态存储器 |
| 文件： | 总18页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP62S2048A-I Series
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Document Title
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
1.0
Initial issue
June 24, 2002
October 15, 2002
April 15, 2003
Preliminary
Change VCC range from 2.7V~3.3V to 2.7V~3.6V
Add 32-pin TSSOP reverse type package
Final version release
Final
1.1
1.2
Add 32L Pb-Free TSSOP package type
Add Pb-Free package type for all parts
June 16, 2003
August 19, 2004
(August, 2004, Version 1.2)
AMIC Technology, Corp.
LP62S2048A-I Series
256K X 8 BIT LOW VOLTAGE CMOS SRAM
General Description
Features
Power supply range: 2.7V to 3.6V
Access times: 55/70 ns (max.)
Current:
The LP62S2048A-I is a low operating current 2,097,152-bit
static random access memory organized as 262,144 words by
8 bits and operates on a low power supply range: 2.7V to 3.6V.
It is built using AMIC's high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and
device enable and an output enable input is included for easy
interfacing.
Very low power version: Operating: 55ns: 25mA (max.)
70ns: 20mA (max.)
Standby: 10μA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Output enable and two chip enable inputs for easy
application
Data retention is guaranteed at a power supply voltage as low
as 2V.
Data retention voltage: 2V (min.)
Available in 32-pin SOP, TSOP, TSSOP (8X13.4mm
forward & reverse type) and 36-pin CSP packages
Product Family
Power Dissipation
Data Retention Standby
(ISB1, Typ.) (ICC2, Typ.)
Operating
Temperature
VCC
Range
Package Type
Product Family
Speed
Operating
(ICCDR, Typ.)
32L SOP
32L TSOP
32L TSSOP
(Forward type)
LP62S2048A
2.7V~3.6V 55ns / 70ns
3mA
-40°C ~ +85°C
0.5μA
0.5μA
32L TSSOP
(Reverse type)
36L CSP
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
(August, 2004, Version 1.2)
1
AMIC Technology, Corp.
LP62S2048A-I Series
Pin Configurations
SOP
TSOP/(TSSOP)
TSSOP
CSP (Chip Size Package)
(forward type)
(reverse type)
36-pin Top View
1
VCC
A15
CE2
WE
A13
A8
32
31
30
29
28
27
26
A17
A16
A14
1
16
16
1
2
3
4
5
6
A12
A7
1
2
3
4
5
6
A8
A0
A1
A2
CE2
WE
A3
A4
A6
A7
A
B
A6
I/O
I/O
5
I/O
I/O
1
A5
A4
A3
A9
7
8
A11
OE
25
24
23
22
C
D
E
F
6
NC
A5
2
9
GND
VCC
VCC
GND
A10
10
11
A2
A1
A0
CE1
I/O
8
12
13
14
15
16
21
20
19
18
17
I/O
I/O
7
NC
CE1
A11
A17
A16
A12
I/O
I/O
3
I/O
I/O
I/O
1
2
3
I/O
I/O
I/O
I/O
7
4
G
H
8
OE
A15
A13
6
5
4
17
32
A9
A10
A14
32
17
GND
Pin No.
1
2
3
4
5
6
7
8
9
10
A16
26
11
A14
27
12
A12
28
13
A7
29
14
15
A5
16
A4
32
Pin
Name
A11
17
A9
18
A2
A8
19
A1
A13
20
WE
21
CE2
22
A15
23
VCC
24
A17
25
A6
30
Pin No.
31
Pin
Name
I/O
3
I/O8
A3
A0
I/O
1
I/O
2
GND
I/O
4
I/O5
I/O6
I/O7
CE1
A10
OE
Block Diagram
A0
VCC
GND
ROW
1024 X 2048
MEMORY ARRAY
A15
A16
A17
DECODER
I/O1
COLUMN I/O
INPUT DATA
CIRCUIT
I/O8
CE2
CE1
CONTROL
CIRCUIT
OE
WE
(August, 2004, Version 1.2)
2
AMIC Technology, Corp.
LP62S2048A-I Series
Pin Description - SOP
Pin Descriptions - TSOP/TSSOP
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1 - 4, 7,
9 - 20, 31
1 - 12, 23,
25 - 28, 31
A0 - A17
Address Inputs
A0 - A17
Address Inputs
Write Enable
5
WE
CE2
VCC
NC
13 - 15,
17 - 21
I/O1 - I/O8
Data Input/Outputs
6
8
9
Chip Enable
16
22
GND
CE1
OE
Ground
Power Supply
No Connection
Chip Enable
21 - 23,
25 - 29
24
29
Output Enable
Write Enable
I/O1 - I/O8
GND
Data Input/Outputs
WE
CE2
VCC
24
30
Ground
30
32
Chip Enable
Chip Enable
CE1
Power Supply
32
Output Enable
OE
Pin Description - CSP
Symbol
Description
Symbol
Description
A0 - A17
WE
Address Inputs
Write Enable
NC
No Connection
I/O1 - I/O8
Data Input/Output
Power Supply
Ground
Output Enable
Chip Enable
Chip Enable
VCC
GND
--
OE
CE1
CE2
--
Recommended DC Operating Conditions
(TA = -40°C to + 85°C)
Symbol
VCC
GND
VIH
Parameter
Supply Voltage
Min.
Typ.
Max.
3.6
0
Unit
V
2.7
0
3.0
Ground
0
-
V
Input High Voltage
Input Low Voltage
Output Load
2.0
-0.3
-
VCC + 0.3
V
V
VIL
-
+0.6
30
1
CL
-
pF
-
TTL
Output Load
-
-
(August, 2004, Version 1.2)
3
AMIC Technology, Corp.
LP62S2048A-I Series
Absolute Maximum Ratings*
*Comments
VCC to GND . . . . . . . .. . . . . . . . . . . . . -0.5V to + 4.6V
IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . -40°C to + 85°C
Storage Temperature, Tstg . . .. . . . . . . -55°C to + 125°C
Temperature Under Bias, Tbias .. . . . . . -40°C to + 85°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . . 260°C, 10 sec
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V)
LP62S2048A-55LLI
LP62S2048A-70LLI
Symbol
Parameter
Unit
Conditions
Min.
Max.
Min.
Max.
Input Leakage Current
Output Leakage Current
-
1
-
1
VIN = GND to VCC
⎜ILI⎥
μA
μA
CE1 = VIH or CE2 = VIL
-
-
1
3
-
-
1
3
⎜ILO⎥
or OE = VIH or WE = VIL
VI/O = GND to VCC
Active Power Supply
Current
CE1 = VIL, CE2 = VIH
II/O = 0mA
ICC
mA
mA
Min. Cycle, Duty = 100%
CE1 = VIL, CE2 = VIH
II/O = 0mA
ICC1
-
25
-
20
Dynamic Operating
Current
CE1 = VIL, CE2 = VIH
VIH = VCC, VIL = 0V
f = 1 MHZ, II/O = 0mA
ICC2
ISB
-
-
5
-
-
5
mA
mA
0.5
0.5
CE1 = VIH or CE2 =VIL
CE1 ≥ VCC - 0.2V
VIN ≥ 0V
Standby Power Supply
Current
ISB1
ISB2
-
-
10
10
-
-
10
10
μA
μA
CE2 ≤ 0.2V
VIN ≥ 0V
VOL
VOH
Output Low Voltage
Output High Voltage
-
0.4
-
-
0.4
-
V
V
IOL = 2.1mA
IOH = -1.0mA
2.2
2.2
(August, 2004, Version 1.2)
4
AMIC Technology, Corp.
LP62S2048A-I Series
Truth Table
Mode
CE2
I/O Operation
Supply Current
CE1
H
OE
X
WE
X
X
L
High Z
High Z
High Z
DOUT
ISB, ISB1
Standby
X
X
X
ISB, ISB2
Output Disable
L
H
H
H
H
L
H
ICC, ICC1, ICC2
ICC, ICC1, ICC2
ICC, ICC1, ICC2
Read
Write
L
H
L
X
L
DIN
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
6
8
CI/O*
Input/Output Capacitance
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
(August, 2004, Version 1.2)
5
AMIC Technology, Corp.
LP62S2048A-I Series
AC Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V)
LP62S2048A-55LLI
LP62S2048A-70LLI
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
Read Cycle
tRC
tAA
Read Cycle Time
55
-
-
70
-
-
ns
ns
ns
Address Access Time
55
55
70
70
tACE1
-
-
CE1
CE2
Chip Enable Access Time
tACE2
tOE
-
-
55
25
-
-
-
70
35
-
ns
ns
ns
Output Enable to Output Valid
Chip Enable to Output in Low Z
tCLZ1
10
10
CE1
CE2
tCLZ2
tOLZ
10
5
-
-
10
5
-
-
ns
ns
ns
Output Enable to Output in Low Z
Chip Disable to Output in High Z
tCHZ1
0
20
0
25
CE1
CE2
tCHZ2
tOHZ
tOH
0
0
5
20
20
-
0
0
25
25
-
ns
ns
ns
Output Disable to Output in High Z
Output Hold from Address Change
10
Write Cycle
tWC
Write Cycle Time
55
50
0
-
-
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Enable to End of Write
Address Setup Time
tAS
-
-
tAW
Address Valid to End of Write
Write Pulse Width
50
40
0
-
60
50
0
-
tWP
-
-
tWR
Write Recovery Time
-
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
25
-
0
25
-
25
0
30
0
tDH
-
-
tOW
5
-
5
-
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
(August, 2004, Version 1.2)
6
AMIC Technology, Corp.
LP62S2048A-I Series
Timing Waveforms
Read Cycle 1 (1, 2, 4)
t
RC
Address
t
AA
t
OH
t
OH
D
OUT
Read Cycle 2 (1, 3, 4, 6)
CE1
t
ACE1
5
CLZ1
t
5
CHZ1
t
D
OUT
Read Cycle 3 (1, 4, 7, 8)
CE2
t
ACE2
5
CHZ2
t
5
CLZ2
t
D
OUT
(August, 2004, Version 1.2)
7
AMIC Technology, Corp.
LP62S2048A-I Series
Timing Waveforms (continued)
Read Cycle 4 (1)
tRC
Address
tAA
OE
tOE
tOH
tOLZ
5
CE1
tACE1
5
5
tCHZ1
tCLZ1
CE2
5
tACE2
tOHZ
5
tCHZ2
5
tCLZ2
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
Write Cycle 1 (6)
(Write Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
(4)
(4)
CE1
CE2
1
2
tAS
tWP
WE
tDW
tDH
DIN
tWHZ
tOW
DOUT
(August, 2004, Version 1.2)
8
AMIC Technology, Corp.
LP62S2048A-I Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
t
WC
Address
3
tWR
t
AW
5
CW
t
CE1
CE2
(4)
(4)
1
AS
t
5
CW
t
2
t
WP
WE
t
DW
t
DH
D
IN
7
WHZ
t
D
OUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(August, 2004, Version 1.2)
9
AMIC Technology, Corp.
LP62S2048A-I Series
AC Test Conditions
Input Pulse Levels
0.4V to 2.4V
5 ns
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figures 1 and 2
TTL
TTL
C
L
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = -40°C to 85°C)
Symbol
Parameter
Min.
Max.
Unit
Conditions
VDR1
2.0
3.6
V
CE1 ≥ VCC - 0.2V
CE2 ≤ 0.2V,
VDR2
VCC for Data Retention
2.0
-
3.6
5**
V
VCC = 2.0V,
ICCDR1
μA
CE1 ≥ VCC - 0.2V,
VIN ≥ 0V
Data Retention Current
VCC = 2.0V,
CE2 ≤ 0.2V,
VIN ≥ 0V
ICCDR2
-
5**
μA
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
tRC
5
-
-
-
ns
ns
See Retention Waveform
tVR
VCC Rising Time from Data Retention Voltage
to Operating Voltage
ms
** LP62S2048A-55LLI/70LLI
ICCDR: max. 1μA at TA = 0°C to + 40°C
(August, 2004, Version 1.2)
10
AMIC Technology, Corp.
LP62S2048A-I Series
Low VCC Data Retention Waveform (1) ( CE1 Controlled)
DATA RETENTION MODE
VCC
CE1
2.7V
2.7V
t
CDR
t
R
VDR ≥ 2V
t
VR
V
IH
VIH
CE1
≥ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
2.7V
2.7V
t
CDR
t
R
VDR ≥ 2V
t
VR
VIL
VIL
CE2 ≤ 0.2V
(August, 2004, Version 1.2)
11
AMIC Technology, Corp.
LP62S2048A-I Series
Ordering Information
Part No.
Access Time
(ns)
Operating Current
Max. (mA)
Standby Current
Package
Max. (μA)
LP62S2048AM-55LLI
LP62S2048AM-55LLIF
LP62S2048AV-55LLI
LP62S2048AV-55LLIF
LP62S2048AX-55LLI
LP62S2048AX-55LLIF
LP62S2048AXR-55LLI
LP62S2048AXR-55LLIF
LP62S2048AU-55LLI
LP62S2048AU-55LLIF
LP62S2048AM-70LLI
LP62S2048AM-70LLIF
LP62S2048AV-70LLI
LP62S2048AV-70LLIF
LP62S2048AX-70LLI
LP62S2048AX-70LLIF
LP62S2048AXR-70LLI
LP62S2048AXR-70LLIF
LP62S2048AU-70LLI
LP62S2048AU-70LLIF
25
25
25
25
25
25
25
25
25
25
20
20
20
20
20
20
20
20
20
20
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
32L SOP
32L Pb-Free SOP
32L TSOP
32L Pb-Free TSOP
32L TSSOP (Forward)
32L Pb-Free TSSOP
32L TSSOP (Reverse)
32L Pb-Free TSSOP (Reverse)
36L CSP
55
36L Pb-Free CSP
32L SOP
32L Pb-Free SOP
32L TSOP
32L Pb-Free TSOP
32L TSSOP (Forward)
32L Pb-Free TSSOP
32L TSSOP (Reverse)
32L Pb-Free TSSOP (Reverse)
36L CSP
70
36L Pb-Free CSP
(August, 2004, Version 1.2)
12
AMIC Technology, Corp.
LP62S2048A-I Series
Package Information
SOP (W.B.) 32L Outline Dimensions
unit: inches/mm
32
17
e
1
L
16
1
b
Detail F
e
1
D
L
E
e
s
y
See Detail F
Seating Plane
Symbol
Dimensions in inches
0.118 Max.
Dimensions in mm
3.00 Max.
A
A1
A2
b
0.004 Min.
0.10 Min.
0.106±0.005
0.016 +0.004
-0.002
2.69±0.13
0.41 +0.10
-0.05
c
0.008 +0.004
-0.002
0.20 +0.10
-0.05
D
E
e
0.805 Typ. (0.820 Max.)
0.445±0.010
0.050 ±0.006
20.45 Typ. (20.83 Max.)
11.30±0.25
1.27±0.15
e
1
0.525 NOM.
0.556±0.010
0.031±0.008
0.055±0.008
0.044 Max.
0.004 Max.
0° ~ 10°
13.34 NOM.
14.12±0.25
0.79±0.20
1.40±0.20
1.12 Max.
0.10 Max.
0° ~ 10°
HE
L
LE
S
y
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2004, Version 1.2)
13
AMIC Technology, Corp.
LP62S2048A-I Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
12.0°
GAUGE PLANE
θ
L
L
E
H
D
Detail "A"
Detail "A"
y
S
b
0.10(0.004)
M
Symbol
Dimensions in inches
Dimensions in mm
1.20 Max.
0.10±0.05
1.00±0.05
0.20±0.03
0.15±0.02
18.40±0.10
8.00±0.10
0.50 TYP.
20.00±0.20
0.50±0.10
0.80 TYP.
0.425 TYP.
0.10 Max.
0° ~ 6°
A
A1
A2
b
0.047 Max.
0.004±0.002
0.039±0.002
0.008±0.001
0.006±0.001
0.724±0.004
0.315±0.004
0.020 TYP.
0.787±0.007
0.020±0.004
0.031 TYP.
0.0167 TYP.
0.004 Max.
0° ~ 6°
c
D
E
e
HD
L
LE
S
Y
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2004, Version 1.2)
14
AMIC Technology, Corp.
LP62S2048A-I Series
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions (Forward Type)
unit: inches/mm
1
32
12.0°
GAUGE PLANE
θ
L
16
17
L
E
D
1
D
Detail "A"
Detail "A"
0.10MM
S
b
SEATING PLANE
Symbol
Dimensions in inches
0.049 Max.
Dimensions in mm
1.25 Max.
0.05 Min.
A
A1
A2
b
0.002 Min.
0.039±0.002
0.008±0.001
0.006±0.0003
0.315±0.004
0.020 TYP.
1.00±0.05
0.20±0.03
0.15±0.008
8.00±0.10
0.50 TYP.
13.40±0.20
11.80±0.10
0.50±0.20
0.675 Min.
0.278 TYP.
0.10 Max.
0° ~ 6°
c
E
e
D
D1
L
0.528±0.008
0.465±0.004
0.02±0.008
LE
S
0.0266 Min.
0.0109 TYP.
0.004 Max.
y
θ
0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2004, Version 1.2)
15
AMIC Technology, Corp.
LP62S2048A-I Series
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions (Reverse Type)
unit: inches/mm
L
E
1
32
L
θ
GAUGE PLANE
12.0°
16
17
Detail "A"
D
1
D
Detail "A"
S
b
SEATING PLANE
0.10MM
Symbol
Dimensions in inches
0.049 Max.
Dimensions in mm
A
A1
A2
b
1.25 Max.
0.05 Min.
1.00±0.05
0.20±0.03
0.15±0.008
8.00±0.10
0.50 TYP.
13.40±0.20
11.80±0.10
0.50±0.20
0.675 Min.
0.278 TYP.
0.10 Max.
0° ~ 6°
0.002 Min.
0.039±0.002
0.008±0.001
0.006±0.0003
0.315±0.004
0.020 TYP.
c
E
e
D
D1
L
0.528±0.008
0.465±0.004
0.02±0.008
LE
S
0.0266 Min.
0.0109 TYP.
0.004 Max.
y
θ
0° ~ 6°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2004, Version 1.2)
16
AMIC Technology, Corp.
LP62S2048A-I Series
Package Information
36LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
S
S
0.10
0.25
C
C A B
Ball*A1 CORNER
b (36X)
6
5 4 3 2 1
1
2 3 4 5 6
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
B
e
D1
A
SIDE VIEW
D
0.20(4X)
C
SEATING PLANE
Dimensions in mm
Symbol
MIN. NOM. MAX.
A
A1
A2
D
1.00
0.16
0.48
5.80
7.80
---
1.10
0.21
0.53
6.00
8.00
3.75
5.25
0.75
0.30
1.20
0.26
0.58
6.20
8.20
---
E
D1
E1
e
---
---
---
---
b
0.25
0.35
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS
OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE
SOLDER BALL AND THE BODY EDGE.
(August, 2004, Version 1.2)
17
AMIC Technology, Corp.
相关型号：
LP62S2048AX-55LLTF
Standard SRAM, 256KX8, 55ns, CMOS, PDSO32, 8 X 13.40 MM, LEAD FREE, TSSOP-32
AMICC
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