LP62E16128A-T [AMICC]
128K X 16 BIT LOW VOLTAGE CMOS SRAM; 128K x 16位的低电压CMOS SRAM
| 型号： | LP62E16128A-T |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| 文件： | 总15页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP62E16128A-T Series
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
1.3
Change VCC from 1.8V~2.2V to 1.65V~2.2V
ISB spec. delete
December 9, 2003
Final
(December, 2003, Version 1.3)
1
AMIC Technology, Corp.
LP62E16128A-T Series
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
Operating voltage: 1.65V to 2.2V
Access times: 70 ns (max.)
Current:
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Very low power version: Operating: 25mA (max.)
Data retention voltage: 1.2V (min.)
Available in 44-pin TSOP and 48-ball CSP (6 x 8mm)
packages
Standby: 10µA (max.)
General Description
The LP62E16128A-T is
a
low operating current
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 1.2V.
2,097,152-bit static random access memory organized as
131,072 words by 16 bits and operates on low power
voltage from 1.65V to 2.2V. It is built using AMIC's high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
TSOP
CSP (Chip Size Package)
48-pin Top View
A4
A3
A2
A1
A0
CE
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
2
A6
1
2
3
4
5
6
3
A7
4
OE
A
B
C
D
E
F
LB
OE
A0
A1
A2
NC
5
HB
6
LB
I/O
9
HB
A3
A5
A4
A6
I/O
I/O
1
CE
I/O
I/O
I/O
I/O
1
7
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
2
8
I/O10
I/O11
I/O
I/O
I/O
I/O
2
3
3
9
4
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
GND
GND I/O12
NC
NC
A14
A12
A9
A7
4
5
6
VCC
GND
VCC
I/O15
I/O16
NC
I/O13
I/O14
NC
A16
A15
A13
A10
I/O
I/O
I/O
I/O
5
6
I/O
I/O
7
8
7
8
I/O9
G
H
WE
WE
A16
A15
A14
A13
A12
NC
A8
A8
A11
NC
A9
A10
A11
NC
(December, 2003, Version 1.3)
2
AMIC Technology, Corp.
LP62E16128A-T Series
Block Diagram
VCC
GND
A0
1024 X 2048
DECODER
MEMORY ARRAY
A15
A16
I/O
1
I/O9
COLUMN I/O
INPUT
DATA
INPUT
DATA
CIRCUIT
CIRCUIT
I/O16
I/O
8
CE
LB
HB
OE
WE
CONTROL
CIRCUIT
Pin Descriptions -- TSOP
Pin No.
Symbol
Description
1 - 5, 18 - 22,
24 – 27, 42 - 44
A0 - A16
Address Inputs
6
Chip Enable Input
CE
7 - 10, 13 - 16,
29 - 32, 35 - 38
I/O1 - I/O16
Data Inputs/Outputs
Write Enable Input
17
39
40
41
WE
LB
Lower Byte Enable Input (I/O1 to I/O8)
Higher Byte Enable Input (I/O9 to I/O16)
Output Enable Input
HB
OE
VCC
GND
NC
11, 33
12, 34
23, 28
Power
Ground
No Connection
(December, 2003, Version 1.3)
3
AMIC Technology, Corp.
LP62E16128A-T Series
Pin Description - CSP
Symbol
Description
Symbol
Description
A0 - A16
Address Inputs
Higher Byte Enable Input
(I/O9 - I/O16)
HB
Chip Enable
Output Enable
CE
OE
I/O1 - I/O16
Data Input/Output
Write Enable Input
VCC
GND
Power Supply
Ground
WE
LB
Lower Byte Enable Input
(I/O1 - I/O8)
NC
No Connection
Recommended DC Operating Conditions
(TA = -25°C to + 85°C)
Symbol
VCC
GND
VIH
Parameter
Supply Voltage
Min.
Typ.
Max.
2.2
0
Unit
V
1.65
0
2
0
Ground
V
Input High Voltage
Input Low Voltage
Output Load
1.4
-0.2
-
-
-
-
-
VCC + 0.2
V
VIL
+0.4
30
1
V
CL
pF
-
TTL
Output Load
-
(December, 2003, Version 1.3)
4
AMIC Technology, Corp.
LP62E16128A-T Series
Absolute Maximum Ratings*
*Comments
VCC to GND ............................................... -0.5V to +3.0V
IN, IN/OUT Volt to GND.....................-0.5V to VCC + 0.5V
Operating Temperature, Topr ....................-25°C to +85°C
Storage Temperature, Tstg......................-55°C to +125°C
Power Dissipation, PT ................................................0.7W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 1.65V to 2.2V, GND = 0V)
LP62E16128A-70LLT
Symbol
⏐ILI⏐
Parameter
Unit
Conditions
Min.
Max.
Input Leakage Current
-
1
VIN = GND to VCC
µA
CE = VIH or LB = VIH or
HB = VIH or OE = VIH or
⏐ILO⏐
Output Leakage Current
-
1
µA
WE = VIH
VI/O = GND to VCC
ICC
Active Power Supply Current
-
-
5
mA
mA
CE = VIL , II/O = 0mA
Min. Cycle, Duty = 100%
ICC1
25
Dynamic Operating
Current
CE = VIL, II/O = 0mA
CE = VIL, VIH = VCC,
VIL = 0V, f = 1MHz,
II/O = 0 mA
ICC2
ISB1
-
-
10
10
mA
CE ≥ VCC - 0.2V,
VIN ≥ 0V
Standby Power
µA
VOL
VOH
Output Low Voltage
Output High Voltage
-
0.2
-
V
V
IOL = 0.1 mA
IOH = -0.1 mA
1.4
(December, 2003, Version 1.3)
5
AMIC Technology, Corp.
LP62E16128A-T Series
Truth Table
I/O1 to I/O8 Mode
I/O9 to I/O16 Mode
VCC Current
CE
H
OE
X
WE
X
LB
X
H
L
HB
X
H
L
Not selected
High-Z
Not selected
High-Z
ISB1, ISB
X
X
X
ISB1, ISB
Read
Read
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
L
L
H
L
H
L
Read
High - Z
Read
H
L
High - Z
Write
L
Write
L
L
X
H
L
L
H
L
Write
Not Write/Hi - Z
Write
H
X
L
No Write/Hi - Z
High - Z
High - Z
L
High - Z
High - Z
H
X
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
6
8
CI/O*
Input/Output Capacitance
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
(December, 2003, Version 1.3)
6
AMIC Technology, Corp.
LP62E16128A-T Series
AC Characteristics (TA = -25°C to +85°C, VCC = 1.65V to 2.2V)
LP62E16128A-70LLT
Unit
Symbol
Parameter
Min.
Max.
Read Cycle
tRC
Read Cycle Time
70
-
-
ns
ns
ns
tAA
Address Access Time
70
70
70
35
-
tACE
tBE
Chip Enable Access Time
-
Byte Enable Access Time
-
tOE
Output Enable to Output Valid
Chip Enable to Output in Low Z
Byte Enable to Outupt in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Byte Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
ns
ns
ns
ns
ns
ns
ns
ns
tCLZ
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
tOH
10
10
5
-
-
-
25
25
25
-
-
-
5
Write Cycle
tWC
Write Cycle Time
70
60
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Enable to End of Write
Byte Enable to End of Write
Address Setup Time
tBW
-
tAS
-
tAW
Address Valid to End of Write
Write Pulse Width
60
55
0
-
tWP
-
tWR
Write Recovery Time
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
-
25
-
30
0
tDH
-
tOW
5
-
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
(December, 2003, Version 1.3)
7
AMIC Technology, Corp.
LP62E16128A-T Series
Timing Waveforms
Read Cycle 1(1, 2, 4)
t
RC
Address
t
AA
t
OH
t
OH
D
OUT
Read Cycle 2(1, 2, 3)
t
RC
Address
t
AA
CE
t
ACE
5
CHZ
t
5
t
CLZ
t
BE
HB, LB
5
BLZ
5
t
t
BHZ
OE
5
t
OE
tOHZ
5
OLZ
t
D
OUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL , HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and (HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(December, 2003, Version 1.3)
8
AMIC Technology, Corp.
LP62E16128A-T Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
t
WC
Address
3
t
WR
t
AW
t
t
CW
CE
BW
HB, LB
1
2
tWP
t
AS
WE
t
DH
t
DW
DATA IN
4
WHZ
t
t
OW
DATA OUT
(December, 2003, Version 1.3)
9
AMIC Technology, Corp.
LP62E16128A-T Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
t
WC
Address
t
AW
3
t
WR
1
2
tCW
t
AS
CE
t
BW
HB, LB
t
WP
WE
t
DH
t
DW
DATA IN
4
WHZ
t
t
OW
DATA OUT
(December, 2003, Version 1.3)
10
AMIC Technology, Corp.
LP62E16128A-T Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
t
WC
Address
t
AW
t
CW
CE
3
t
WR
1
2
t
AS
tBW
HB, LB
t
WP
WE
t
DH
t
DW
DATA IN
4
WHZ
t
t
OW
DATA OUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and , or LB ).
3. tWR is measured from the earliest of CE or WE or (HB and , or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(December, 2003, Version 1.3)
11
AMIC Technology, Corp.
LP62E16128A-T Series
AC Test Conditions
Input Pulse Levels
0.2V to VCC - 0.2V
5 ns
Input Rise And Fall Time
Input and Output Timing Reference Levels
Output Load
0.9V
See Figures 1 and 2
TTL
TTL
C
L
CL
30pF
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -25°C to 85°C)
Symbol
Parameter
VCC for Data Retention
Min.
Max.
Unit
Conditions
VDR
1.2
2.2
V
CE ≥ VCC - 0.2V
VCC = 1.2V,
ICCDR
Data Retention Current
-
3*
µA
CE ≥ VCC - 0.2V
VIN ≥ 0V
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
tRC
5
-
-
-
ns
ns
See Retention Waveform
tVR
VCC Rising Time from Data Retention
Voltage to Operating Voltage
ms
* LP62E16128A-70LLT
ICCDR: max. 1µA at TA = 0°C to + 40°C
(December, 2003, Version 1.3)
12
AMIC Technology, Corp.
LP62E16128A-T Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
CE
1.8V
1.8V
t
CDR
t
R
VDR ≥ 1.2V
t
VR
VIH
VIH
CE
≥ VDR - 0.2V
Ordering Information
Part No.
Access Time (ns)
Operating Current
Standby Current
Package
Max. (mA)
Max. (µA)
LP62E16128AV-70LLT
LP62E16128AU-70LLT
25
25
10
10
44L TSOP
48L CSP
70
(December, 2003, Version 1.3)
13
AMIC Technology, Corp.
LP62E16128A-T Series
Package Information
TSOP 44L TYPE II Outline Dimensions
unit: inches/mm
44
23
L
L
1
1
22
D
L
1
L
S
B
y
e
Dimension in inch
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
A
A1
A2
B
-
-
-
0.047
-
-
-
1.20
-
0.002
0.05
-
0.037 0.039 0.041 0.95
0.010 0.014 0.018 0.25
1.00
0.35
0.15
1.05
0.45
-
c
-
0.006
-
-
D
E
0.721 0.725 0.729 18.31 18.41 18.51
0.396 0.400 0.404 10.06 10.16 10.26
e
-
0.031
-
-
0.80
-
HE
L
0.455 0.463 0.471 11.56 11.76 11.96
0.016 0.020 0.024 0.40
0.50
0.60
-
L1
S
-
-
0.031
-
-
-
0.80
-
-
-
0.036
0.004
5°
-
-
-
0.93
0.10
5°
y
-
-
θ
0°
0°
Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
(December, 2003, Version 1.3)
14
AMIC Technology, Corp.
LP62E16128A-T Series
Package Information
48LD CSP (6 x 8 mm) Outline Dimensions
(48TFBGA)
unit: mm
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
S
S
0.10
0.25
C
C A B
Ball*A1 CORNER
b (48X)
6
5 4 3 2 1
1
2 3 4 5 6
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
B
e
D1
A
SIDE VIEW
D
0.20(4X)
C
SEATING PLANE
Dimensions in mm
Symbol
MIN. NOM. MAX.
A
A1
A2
D
1.00
0.20
0.48
5.90
7.90
---
1.10
0.25
0.53
6.00
8.00
3.75
5.25
0.75
0.35
1.20
0.30
0.58
6.10
8.10
---
E
D1
E1
e
---
---
---
---
b
0.30
0.40
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF
THE SOLDER BALL AND THE BODY EDGE.
(December, 2003, Version 1.3)
15
AMIC Technology, Corp.
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