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LP621024DX-55LLI [AMICC]

128K X 8 BIT CMOS SRAM; 128K ×8位CMOS SRAM
LP621024DX-55LLI
型号： LP621024DX-55LLI
厂家： AMIC TECHNOLOGY    AMIC TECHNOLOGY
描述：

128K X 8 BIT CMOS SRAM
128K ×8位CMOS SRAM

静态存储器
文件： 总17页 (文件大小：193K)
中文：  中文翻译
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LP621024D-I Series  
Preliminary  
128K X 8 BIT CMOS SRAM  
Document Title  
128K X 8 BIT CMOS SRAM  
Revision History  
Rev. No. History  
Issue Date  
Remark  
0.0  
Initial issue  
August 9, 2002  
Preliminary  
PRELIMINARY (August, 2002, Version 0.0)  
1
AMIC Technology, Inc.  
LP621024D-I Series  
Preliminary  
128K X 8 BIT CMOS SRAM  
Features  
General Description  
n Single +5V power supply  
n Access times: 55/70 ns (max.)  
n Current:  
The LP621024D-I is a low operating current 1,048,576-bit  
static random access memory organized as 131,072  
words by 8 bits and operates on a single 5V power  
supply.  
Very low power version: Operating: 70mA (max.)  
Inputs and three-state outputs are TTL compatible and  
allow for direct interfacing with common system bus  
structures.  
Two chip enable inputs are provided for POWER-DOWN  
and device enable and an output enable input is included  
for easy interfacing.  
Standby:  
50mA (max.)  
n Full static operation, no clock or refreshing required  
n All inputs and outputs are directly TTL-compatible  
n Common I/O using three-state output  
n Output enable and two chip enable inputs for easy  
application  
Data retention is guaranteed at a power supply voltage  
as low as 2V.  
n Data retention voltage: 2V (min.)  
n Available in 32-pin DIP, SOP TSOP and TSSOP  
(8 X 13.4mm) packages  
Product Family  
Power Dissipation  
Package  
Operating  
Temperature  
VCC  
Range  
Product Family  
Speed  
Data Retention  
(ICCDR, Typ.)  
Standby  
Operating  
(ICC2, Typ.)  
Type  
(ISB1, Typ.)  
32L DIP/  
SOP/TSOP/  
TSSOP  
LP62S1024D  
4.5V~5.5V 55ns / 70ns  
10mA  
-40°C ~ +85°C  
0.5mA  
2mA  
1. Typical values are measured at VCC = 5.0V, TA = 25°C and not 100% tested.  
2. Data retention current VCC = 2.0V.  
Pin Configurations  
n DIP  
n SOP  
n TSOP/(TSSOP)  
1
VCC  
A15  
CE2  
WE  
A13  
A8  
1
VCC  
A15  
CE2  
WE  
A13  
A8  
32  
31  
30  
29  
28  
27  
26  
32  
31  
30  
29  
28  
27  
26  
NC  
A16  
A14  
NC  
A16  
A14  
16  
1
2
3
4
5
6
2
3
4
5
6
A12  
A7  
A12  
A7  
A6  
A6  
A5  
A4  
A3  
A5  
A4  
A3  
A9  
A9  
7
8
7
8
A11  
OE  
A11  
OE  
25  
24  
23  
22  
25  
24  
23  
22  
9
9
A10  
A10  
10  
11  
10  
11  
A2  
A1  
A2  
A1  
CE1  
CE1  
A0  
I/O8  
A0  
I/O8  
12  
13  
14  
15  
16  
21  
20  
19  
18  
17  
12  
13  
14  
15  
16  
21  
20  
19  
18  
17  
I/O1  
I/O1  
I/O7  
I/O6  
I/O5  
I/O4  
I/O7  
I/O6  
I/O5  
I/O4  
I/O2  
I/O3  
I/O2  
I/O3  
32  
17  
GND  
GND  
Pin No.  
1
2
3
4
5
6
7
8
9
10  
A16  
26  
11  
12  
A12  
28  
13  
A7  
14  
A6  
15  
A5  
16  
A4  
32  
Pin  
Name  
A11  
17  
A9  
18  
A2  
A8  
19  
A1  
A13  
20  
WE  
21  
CE2  
22  
A15  
VCC  
24  
NC  
25  
A14  
27  
Pin No.  
23  
29  
30  
31  
Pin  
Name  
I/O3  
I/O8  
A3  
A0  
I/O1  
I/O2  
GND  
I/O4  
I/O5  
I/O6  
I/O7  
CE1  
A10  
OE  
PRELIMINARY (August, 2002, Version 0.0)  
2
AMIC Technology, Inc.  
LP621024D-I Series  
Block Diagram  
A0  
VCC  
GND  
ROW  
512 X 2048  
A14  
A15  
A16  
DECODER  
MEMORY ARRAY  
I/O1  
COLUMN I/O  
INPUT DATA  
CIRCUIT  
I/O8  
CE2  
CE1  
OE  
CONTROL  
CIRCUIT  
WE  
Pin Descriptions - DIP/SOP  
Pin Description - TSOP/TSSOP  
Pin No.  
Symbol  
Description  
Pin No.  
Symbol  
Description  
1
NC  
No Connection  
1 - 4, 7,  
10 - 20, 31  
A0 - A16  
Address Inputs  
Write Enable  
2 - 12, 23,  
25 - 28, 31  
A0 - A16  
Address Inputs  
5
WE  
CE2  
VCC  
NC  
13 - 15,  
17 - 21  
6
8
9
Chip Enable  
I/O1 - I/O8  
Data Input/Outputs  
Power Supply  
No Connection  
16  
22  
GND  
CE1  
OE  
Ground  
Chip Enable  
21 - 23,  
25 - 29  
I/O1 - I/O8  
Data Input/Outputs  
24  
29  
Output Enable  
Write Enable  
24  
30  
GND  
CE1  
OE  
Ground  
WE  
CE2  
VCC  
Chip Enable  
30  
32  
Chip Enable  
32  
Output Enable  
Power Supply (+5V)  
PRELIMINARY (August, 2002, Version 0.0)  
3
AMIC Technology, Inc.  
LP621024D-I Series  
Recommended DC Operating Conditions  
(TA = -40°C to + 85°C)  
Symbol  
Parameter  
Supply Voltage  
Min.  
4.5  
0
Typ.  
Max.  
Unit  
5.0  
5.5  
V
GND  
VIH  
Ground  
0
3.5  
0
0
V
V
Input High Voltage  
Input Low Voltage  
Output Load  
2.2  
-0.3  
-
VCC + 0.3  
VIL  
+0.8  
30  
1
V
CL  
-
pF  
-
TTL  
Output Load  
-
-
Absolute Maximum Ratings*  
*Comments  
VCC to GND ............................................. -0.5V to + 7.0V  
IN, IN/OUT Volt to GND....................-0.5V to VCC + 0.5V  
Operating Temperature, Topr .................. -40°C to + 85°C  
Storage Temperature, Tstg.................... -55°C to + 125°C  
Temperature Under Bias, Tbias............... -10°C to + 85°C  
Power Dissipation, PT .......................................................................0.7W  
Soldering Temp. & Time .............................260°C, 10 sec  
Stresses above those listed under "Absolute Maximum  
Ratings" may cause permanent damage to this device.  
These are stress ratings only. Functional operation of this  
device at these or any other conditions above those  
indicated in the operational sections of this specification  
is not implied or intended. Exposure to the absolute  
maximum rating conditions for extended periods may  
affect device reliability.  
DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 5V ± 10%, GND = 0V)  
LP621024D-55LLI  
LP621024D-70LLI  
Symbol  
Parameter  
Unit  
Conditions  
Min.  
Max.  
Min.  
Max.  
Input Leakage  
Current  
-
1
-
1
VIN = GND to VCC  
çILIú  
mA  
mA  
CE1 = VIH or CE2 = VIL  
Output Leakage  
Current  
-
-
1
-
-
1
çILOú  
ICC  
or OE = VIH or WE = VIL  
VI/O = GND to VCC  
Active Power  
Supply Current  
CE1 = VIL, CE2 = VIH  
II/O = 0mA  
15  
15  
mA  
Min. Cycle, Duty = 100%  
CE1 = VIL, CE2 = VIH  
II/O = 0mA  
ICC1  
ICC2  
-
-
70  
15  
-
-
70  
15  
mA  
mA  
Dynamic  
Operating  
Current  
CE1 = VIL, CE2 = VIH  
VIH = VCC, VIL = 0V  
f = 1MHZ, II/O = 0mA  
PRELIMINARY (August, 2002, Version 0.0)  
4
AMIC Technology, Inc.  
LP621024D-I Series  
DC Electrical Characteristics (continued)  
LP621024D-55LLI  
LP621024D-70LLI  
Symbol  
Parameter  
Unit  
Conditions  
Min.  
Max.  
Min.  
Max.  
ISB  
ISB1  
ISB2  
-
2
-
2
mA  
CE1 = VIH or CE2 =VIL  
CE1 ³ VCC - 0.2V  
CE2 ³ VCC - 0.2V  
VIN ³ 0V  
Standby Power  
Supply Current  
-
-
50  
50  
-
-
50  
50  
mA  
CE2 £ 0.2V  
VIN ³ 0V  
mA  
V
Output Low  
Voltage  
VOL  
VOH  
-
0.4  
-
-
0.4  
-
IOL = 2.1mA  
IOH = -1.0mA  
Output High  
Voltage  
2.4  
2.4  
V
Truth Table  
Mode  
CE2  
X
I/O Operation  
High Z  
High Z  
High Z  
DOUT  
Supply Current  
ISB, ISB1  
CE1  
H
OE  
X
WE  
X
Standby  
X
L
X
X
ISB, ISB2  
Output Disable  
Read  
L
H
H
L
H
ICC, ICC1, ICC2  
ICC, ICC1, ICC2  
ICC, ICC1, ICC2  
L
H
H
Write  
L
H
X
L
DIN  
Note: X = H or L  
Capacitance (TA = 25°C, f = 1.0MHz)  
Symbol  
CIN*  
Parameter  
Min.  
Max.  
Unit  
pF  
Conditions  
VIN = 0V  
Input Capacitance  
6
8
CI/O*  
Input/Output Capacitance  
pF  
VI/O = 0V  
* These parameters are sampled and not 100% tested.  
PRELIMINARY (August, 2002, Version 0.0)  
5
AMIC Technology, Inc.  
LP621024D-I Series  
AC Characteristics (TA = -40°C to + 85°C, VCC = 5V ± 10%)  
LP621024D-55LLI  
LP621024D-70LLI  
Unit  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Read Cycle  
tRC  
tAA  
Read Cycle Time  
55  
-
-
70  
-
-
ns  
ns  
ns  
Address Access Time  
55  
55  
70  
70  
tACE1  
-
-
CE1  
CE2  
Chip Enable Access Time  
tACE2  
tOE  
-
-
55  
30  
-
-
-
70  
35  
-
ns  
ns  
ns  
Output Enable to Output Valid  
Chip Enable to Output in Low Z  
tCLZ1  
10  
10  
CE1  
CE2  
tCLZ2  
tOLZ  
10  
5
-
-
10  
5
-
-
ns  
ns  
ns  
Output Enable to Output in Low Z  
Chip Disable to Output in High Z  
tCHZ1  
0
20  
0
25  
CE1  
CE2  
tCHZ2  
tOHZ  
tOH  
0
0
5
20  
20  
-
0
0
5
25  
25  
-
ns  
ns  
ns  
Output Disable to Output in High Z  
Output Hold from Address Change  
Write Cycle  
tWC  
Write Cycle Time  
55  
50  
0
-
-
70  
60  
0
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCW  
Chip Enable to End of Write  
Address Setup Time  
tAS  
-
-
tAW  
Address Valid to End of Write  
Write Pulse Width  
50  
40  
0
-
60  
50  
0
-
tWP  
-
-
tWR  
Write Recovery Time  
-
-
tWHZ  
tDW  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
0
25  
-
0
30  
-
25  
0
30  
0
tDH  
-
-
tOW  
5
-
5
-
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are  
not referred to output voltage levels.  
PRELIMINARY (August, 2002, Version 0.0)  
6
AMIC Technology, Inc.  
LP621024D-I Series  
Timing Waveforms  
Read Cycle 1(1, 2, 4)  
tRC  
Address  
tAA  
tOH  
tOH  
DOUT  
Read Cycle 2 (1, 3, 4, 6)  
CE1  
tACE1  
5
tCLZ1  
5
tCHZ1  
DOUT  
Read Cycle 3 (1, 4, 7, 8)  
CE2  
tACE2  
5
tCHZ2  
5
tCLZ2  
DOUT  
PRELIMINARY (August, 2002, Version 0.0)  
7
AMIC Technology, Inc.  
LP621024D-I Series  
Timing Waveforms (continued)  
Read Cycle 4 (1)  
tRC  
Address  
tAA  
OE  
tOE  
tOH  
5
tOLZ  
CE1  
tACE1  
5
5
tCHZ1  
tCLZ1  
CE2  
5
tACE2  
tOHZ  
5
tCHZ2  
5
tCLZ2  
DOUT  
Notes: 1. WE is high for Read Cycle.  
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.  
3. Address valid prior to or coincident with CE1 transition low.  
4. OE = VIL.  
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.  
6. CE2 is high.  
7. CE1 is low.  
8. Address valid prior to or coincident with CE2 transition high.  
PRELIMINARY (August, 2002, Version 0.0)  
8
AMIC Technology, Inc.  
LP621024D-I Series  
Timing Waveforms (continued)  
Write Cycle 1(6)  
(Write Enable Controlled)  
tWC  
Address  
3
tAW  
tWR  
5
tCW  
(4)  
(4)  
CE1  
CE2  
1
2
tAS  
tWP  
WE  
tDW  
tDH  
DIN  
tWHZ  
tOW  
DOUT  
PRELIMINARY (August, 2002, Version 0.0)  
9
AMIC Technology, Inc.  
LP621024D-I Series  
Timing Waveforms (continued)  
Write Cycle 2  
(Chip Enable Controlled)  
tWC  
Address  
3
tAW  
tWR  
5
tCW  
CE1  
CE2  
(4)  
(4)  
1
tAS  
5
tCW  
2
tWP  
WE  
tDW  
tDH  
DIN  
7
tWHZ  
DOUT  
Notes: 1. tAS is measured from the address valid to the beginning of Write.  
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .  
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.  
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after  
the WE transition, outputs remain in a high impedance state.  
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.  
6. OE is continuously low. ( OE = VIL)  
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.  
PRELIMINARY (August, 2002, Version 0.0)  
10  
AMIC Technology, Inc.  
LP621024D-I Series  
AC Test Conditions  
Input Pulse Levels  
0V to 3.0V  
5 ns  
Input Rise and Fall Time  
Input and Output Timing Reference Levels  
Output Load  
1.5V  
See Figures 1 and 2  
+5V  
+5V  
1800  
W
1800W  
I/O  
I/O  
30pF*  
5pF*  
990  
W
990W  
* Including scope and jig.  
* Including scope and jig.  
Figure 1. Output Load  
Figure 2. Output Load for tCLZ1,  
tCLZ2, tOHZ, tOLZ, tCHZ1,  
tCHZ2, tWHZ, and tOW  
Data Retention Characteristics (TA = -40°C to 85°C)  
Symbol  
Parameter  
Min.  
Max.  
Unit  
Conditions  
VDR1  
2.0  
5.5  
V
CE1 ³ VCC - 0.2V  
VDR2  
VCC for Data Retention  
2.0  
5.5  
V
CE2 £ 0.2V  
CE1 ³ VCC - 0.2V or  
CE1 £ 0.2V  
VCC = 2.0V,  
CE1 ³ VCC - 0.2V  
CE2 ³ VCC - 0.2V  
VIN ³ 0V  
ICCDR1  
ICCDR2  
LL-Version  
LL-Version  
-
-
20**  
20**  
mA  
mA  
Data Retention Current  
VCC = 2.0V  
CE2 £ 0.2V  
VIN ³ 0V  
tCDR  
tR  
Chip Disable to Data Retention Time  
Operation Recovery Time  
0
5
-
-
ns  
See Retention Waveform  
ms  
** LP621024D-55LLI/70LLI  
ICCDR: Max. 2mA at TA = 0°C to + 40 °C  
PRELIMINARY (August, 2002, Version 0.0)  
11  
AMIC Technology, Inc.  
LP621024D-I Series  
Low VCC Data Retention Waveform (1) ( CE1 Controlled)  
DATA RETENTION MODE  
VCC  
CE1  
4.5V  
4.5V  
tCDR  
tR  
VDR  
³ 2V  
VIH  
VIH  
CE1  
³ VDR - 0.2V  
Low VCC Data Retention Waveform (2) (CE2 Controlled)  
DATA RETENTION MODE  
VCC  
CE2  
4.5V  
4.5V  
tCDR  
tR  
VDR  
³ 2V  
VIL  
VIL  
CE2  
< 0.2V  
PRELIMINARY (August, 2002, Version 0.0)  
12  
AMIC Technology, Inc.  
LP621024D-I Series  
Ordering Information  
Part No.  
Operating Current  
Max. (mA)  
Standby Current  
Access Time (ns)  
Package  
Max. (mA)  
LP621024D-55LLI  
LP621024DM-55LLI  
LP621024DV-55LLI  
LP621024DX-55LLI  
LP621024D-70LLI  
LP621024DM-70LLI  
LP621024DV-70LLI  
LP621024DX-70LLI  
70  
70  
70  
70  
70  
70  
70  
70  
50  
50  
50  
50  
50  
50  
50  
50  
32L DIP  
32L SOP  
32L TSOP  
32L TSSOP  
32L DIP  
55  
32L SOP  
32L TSOP  
32L TSSOP  
70  
PRELIMINARY (August, 2002, Version 0.0)  
13  
AMIC Technology, Inc.  
LP621024D-I Series  
Package Information  
P-DIP 32L Outline Dimensions  
unit: inches/mm  
D
32  
17  
1
16  
E
S
Base Plane  
Seating Plane  
B
e
A
a
e1  
B1  
Symbol  
Dimensions in inches  
0.210 Max.  
Dimensions in mm  
5.33 Max.  
A
A1  
A2  
0.010 Min.  
0.25 Min.  
0.155±0.010  
3.94±0.25  
B
B1  
C
0.018 +0.004  
-0.002  
0.46 +0.10  
-0.05  
0.050 +0.004  
-0.002  
1.27 +0.10  
-0.05  
0.010 +0.004  
-0.002  
0.25 +0.11  
-0.05  
D
E
1.650 Typ. (1.670 Max.)  
0.600±0.010  
41.91 Typ. (42.42 Max.)  
15.24±0.25  
E1  
e1  
L
0.550 Typ. (0.562 Max.)  
0.100±0.010  
13.97 Typ. (14.27 Max.)  
2.54±0.25  
0.130±0.010  
3.30±0.25  
a
0° ~ 15°  
0° ~ 15°  
eA  
S
0.655±0.035  
16.64±0.89  
0.090 Max.  
2.29 Max.  
Notes:  
1. The maximum value of dimension D includes end flash.  
2. Dimension E1 does not include resin fins.  
3. Dimension S includes end flash.  
PRELIMINARY (August, 2002, Version 0.0)  
14  
AMIC Technology, Inc.  
LP621024D-I Series  
Package Information  
SOP (W.B.) 32L Outline Dimensions  
unit: inches/mm  
32  
17  
e1  
L
16  
1
b
Detail F  
e1  
D
LE  
e
s
y
See Detail F  
Seating Plane  
Symbol  
Dimensions in inches  
Dimensions in mm  
3.00 Max.  
A
A1  
A2  
b
0.118 Max.  
0.004 Min.  
0.10 Min.  
0.106±0.005  
0.016 +0.004  
-0.002  
2.69±0.13  
0.41 +0.10  
-0.05  
c
0.008 +0.004  
-0.002  
0.20 +0.10  
-0.05  
D
E
e
0.805 Typ. (0.820 Max.)  
0.445±0.010  
0.050 ±0.006  
0.525 NOM.  
0.556±0.010  
0.031±0.008  
0.055±0.008  
0.044 Max.  
20.45 Typ. (20.83 Max.)  
11.30±0.25  
1.27±0.15  
e1  
13.34 NOM.  
14.12±0.25  
0.79±0.20  
HE  
L
LE  
S
1.40±0.20  
1.12 Max.  
y
0.004 Max.  
0.10 Max.  
q
0° ~ 10°  
0° ~ 10°  
Notes:  
1. The maximum value of dimension D includes end flash.  
2. Dimension E does not include resin fins.  
3. Dimension e is for PC Board surface mount pad pitch design  
1
reference only.  
4. Dimension S includes end flash.  
PRELIMINARY (August, 2002, Version 0.0)  
15  
AMIC Technology, Inc.  
LP621024D-I Series  
Package Information  
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions  
unit: inches/mm  
D
12.0°  
GAUGE PLANE  
q
L
LE  
HD  
Detail "A"  
Detail "A"  
y
S
b
0.10(0.004)  
M
Symbol  
Dimensions in inches  
Dimensions in mm  
1.20 Max.  
0.10±0.05  
1.00±0.05  
0.20±0.03  
0.15±0.02  
18.40±0.10  
8.00±0.10  
0.50 TYP.  
20.00±0.20  
0.50±0.10  
0.80 TYP.  
0.425 TYP.  
0.10 Max.  
0° ~ 6°  
A
A1  
A2  
b
0.047 Max.  
0.004±0.002  
0.039±0.002  
0.008±0.001  
0.006±0.001  
0.724±0.004  
0.315±0.004  
0.020 TYP.  
0.787±0.007  
0.020±0.004  
0.031 TYP.  
0.0167 TYP.  
0.004 Max.  
0° ~ 6°  
c
D
E
e
HD  
L
LE  
S
Y
q
Notes:  
1. The maximum value of dimension D includes end flash.  
2. Dimension E does not include resin fins.  
3. Dimension e is for PC Board surface mount pad pitch design  
1
reference only.  
4. Dimension S includes end flash.  
PRELIMINARY (August, 2002, Version 0.0)  
16  
AMIC Technology, Inc.  
LP621024D-I Series  
Package Information  
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions  
unit: inches/mm  
12.0°  
GAUGE PLANE  
q
L
LE  
D1  
D
Detail "A"  
Detail "A"  
0.10MM  
S
b
SEATING PLANE  
Symbol  
Dimensions in inches  
Dimensions in mm  
1.25 Max.  
A
A1  
A2  
b
0.049 Max.  
0.002 Min.  
0.05 Min.  
0.039±0.002  
0.008±0.001  
0.006±0.0003  
0.315±0.004  
0.020 TYP.  
0.528±0.008  
0.465±0.004  
0.02±0.008  
0.0266 Min.  
0.0109 TYP.  
0.004 Max.  
0° ~ 6°  
1.00±0.05  
0.20±0.03  
0.15±0.008  
8.00±0.10  
0.50 TYP.  
13.40±0.20  
11.80±0.10  
0.50±0.20  
0.675 Min.  
0.278 TYP.  
0.10 Max.  
c
E
e
D
D1  
L
LE  
S
y
q
0° ~ 6°  
Notes:  
1. The maximum value of dimension D includes end flash.  
2. Dimension E does not include resin fins.  
3. Dimension e is for PC Board surface mount pad pitch design  
1
reference only.  
4. Dimension S includes end flash.  
PRELIMINARY (August, 2002, Version 0.0)  
17  
AMIC Technology, Inc.  

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