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FQ245L10PF [AMICC]

FIFO, 4KX18, 6.5ns, Synchronous, CMOS, PQFP64,;
FQ245L10PF
型号： FQ245L10PF
厂家： AMIC TECHNOLOGY    AMIC TECHNOLOGY
描述：

FIFO, 4KX18, 6.5ns, Synchronous, CMOS, PQFP64,

时钟 先进先出芯片 内存集成电路
文件： 总26页 (文件大小：285K)
中文：  中文翻译
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FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
5 Volt Synchronous x18 First-In/First-Out Queue  
Memory Configuration  
4,096 x 18  
Device  
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
2,048 x 18  
1,024 x 18  
512 x 18  
256 x 18  
Key Features:  
•
•
•
•
•
•
•
•
•
Industry leading First-In/First-Out Queues (up to 100MHz)  
Independent Write and Read cycle time  
5V power supply  
Reset clears all previously programmed configurations including Write and Read pointers.  
Preset for Almost Full ( PRAF ) and Almost Empty ( PRAE ) offsets values  
Parallel programming of PRAF and PRAE offset values  
Full, Empty, Almost Full, Almost Empty, and Half Full indicators  
Asynchronous output enable tri-state data output drivers  
Available packages: 64 - pin Plastic Thin Quad Flat Package (TQFP), 64 - pin Slim Thin Quad Flat Package  
(STQFP)  
•
•
(0°C to 70°C) Commercial operating temperature available  
(-40°C to 85°C) Industrial operating temperature available  
Product Description:  
HBA’s FlexQ™ I offers industry leading FIFO queuing bandwidth (up to 1.8 Gbps), with a wide range of memory configurations  
(from 256 x 18 to 4,096 x 18). System designer has full flexibility of implementing deeper and wider queues with Write ( WEXI  
and WEXO ) and Read ( REXI and REXO ) expansion features using Daisy Chain technique. Full, Empty, and Half Full  
indicators allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty  
(Parallel) indicators allow implementation of virtual queue depths.  
Asynchronous Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-  
matching capability.  
Data is written into the queue at the low to high transition of WCLK if WEN is asserted. Data is read from the queue at the low  
to high transition of RCLK if REN is asserted.  
Reset clears all previously programmed configurations by providing a low pulse on RST pin. In addition, Write and Read  
pointers to the queue are initialized to zero.  
These FlexQ™ I devices have low power consumption, hence minimizing system power requirements. In addition, industry  
standard 64 - pin Plastic TQFP and 64 - pin STQFP are offered to save system board space.  
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test  
equipment, network switching, etc.  
MAY 2003  
5F118C  
Page 1 of 26  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Block Diagram of Single Synchronous Queue  
4,096 x 18 / 2 ,048 x 18 / 1,024 x 18 / 512 x 18 / 256 x 18  
RESET (RST )  
READ CLOCK (RCLK)  
READ ENABLE (REN)  
OUTPUT ENABLE (OE )  
WRITE CLOCK (WCLK)  
WRITE ENABLE (WEN )  
LOAD (  
)
LOAD  
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
DATA OUT (Q17 - 0  
)
DATA IN (D17 - 0  
)
EMPTY FLAG (EMPTY)  
PROGRAMMABLE (PRAF)  
WEXO  
FULL FLAG ( FULL)  
PROGRAMMABLE (PRAE)  
HALF  
HALF - FULL FLAG (  
)
REXO  
FIRST LOAD (FIRST )  
WRITE EXPANSION IN (  
)
WEXI  
READ EXPANSION IN (REXI)  
Figure 1. Single Device Configuration Signal Flow Diagram  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 2 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
WEN  
WCLK  
LOAD  
Write Control  
Logic  
FULL  
PRAF  
Offset Register  
EMPTY  
Flag Logic  
PRAE  
(WEXO)/HALF  
Write Pointer  
Output  
Buffer  
Input Register  
Output Register  
D
x18  
SRAM  
Q17-0  
x18  
17-0  
OE  
Read Pointer  
FIRST  
WEXI  
Read Control  
Logic  
Expansion Logic  
(HALF) WEXO  
/
Reset  
REXI  
REXO  
RCLK  
RST  
REN  
Figure 2. Device Architecture  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 3 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
PIN 1  
Q14  
48  
47  
46  
1
2
D15  
Q13  
GND  
Q12  
D14  
D13  
D12  
D11  
3
4
45  
44  
43  
Q11  
Vcc  
5
6
7
D10  
D9  
42  
41  
Q10  
Q9  
D8  
D7  
8
40  
39  
38  
GND  
Q8  
9
D6  
D5  
10  
11  
Q7  
Q6  
Q5  
37  
36  
D4  
D3  
D2  
12  
13  
14  
35  
GND  
Q4  
34  
33  
D1  
D0  
15  
16  
Vcc  
TQFP – 64 (Drw No: PF-01A; Order Code: PF)  
STQFP – 64 (Drw No: TF-01A; Order Code: TF)  
Top View  
Figure 3. Device Pin Out  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 4 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Description  
Pin #  
Pin Name  
Pin Symbol  
Input/Output  
Reset is required to initialize Write and Read pointers  
to the first position of the queue by setting RST low.  
FULL and PRAF will go high; EMPTY and  
PRAE will go low. All data outputs will go low.  
Previous programmed configurations will not be  
maintained.  
Reset  
Input  
57  
RST  
Writes data into queue during low to high transitions  
of WCLK if WEN is set low.  
19  
20  
Write Clock  
Write Enable  
WCLK  
WEN  
Input  
Input  
Controls write operation into queue or offset registers  
during low to high transition of WCLK.  
LOAD controls write/read, to/from offset registers  
during low to high transition of WCLK/RCLK  
respectively. Use in conjunction with WEN / REN .  
Load Enable  
First Load  
Input  
Input  
59  
18  
LOAD  
FIRST  
In single device configuration, FIRST is set low.  
In depth expansion configuration, FIRST is set low  
for the first device and set high for other devices in  
the Daisy Chain.  
In single device configuration, WEXI is set low.  
In depth expansion configuration, WEXI is  
connected to WEXO of previous device in the Daisy  
Chain.  
Write Expansion  
In  
21  
Input  
Input  
WEXI  
D17-0  
63, 64, 1, 2, 3, 4,  
5, 6, 7, 8, 9, 10,  
11, 12, 13, 14, 15,  
16  
Data Inputs  
18 - bit wide input data bus.  
Reads data from queue during low to high transitions  
of RCLK if REN is set low.  
Read Clock  
Read Enable  
RCLK  
REN  
Input  
Input  
61  
60  
Controls read operation from queue or offset registers  
during low to high transition of RCLK.  
In single device configuration, REXI is set low.  
In depth expansion configuration, REXI is connected  
to REXO of previous device in the Daisy Chain.  
Read Expansion  
In  
24  
Input  
Input  
REXI  
OE  
Setting OE low activates the data output drivers.  
Setting OE high deactivates the data output drivers  
(High-Z).  
58  
Output Enable  
Data Outputs  
53, 52, 50, 48, 47,  
45, 44, 42, 41, 39,  
38, 37, 36, 34, 32,  
31, 29, 28  
Q17-0  
REXO  
FULL  
Output  
Output  
Output  
18 - bit wide output data bus.  
In depth expansion configuration, REXO is  
connected to REXI of next device in the Daisy  
Chain.  
Read Expansion  
Out  
27  
Queue is full when FULL goes low during the low to  
high transition of WCLK. This prohibits further  
writes into the queue.  
25  
Full Flag  
Table 1. Pin Descriptions  
MAY 2003  
5F118C  
Page 5 of 26  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Description  
Pin #  
Pin Name  
Pin Symbol  
Input/Output  
Queue is empty when EMPTY goes low during the  
low to high transition of RCLK. This prohibits  
further reads from the queue.  
54  
Empty Flag  
Output  
EMPTY  
Queue is almost full when PRAF goes low during the  
low to high transition of WCLK. Default (Full-offset)  
or programmed offset values determine the status of  
PRAF.  
23  
17  
Almost Full  
Output  
Output  
PRAF  
PRAE  
Queue is almost empty when PRAE goes low during  
the low to high transition of RCLK. Default  
(Empty+offset) or programmed offset values  
determine the status of PRAE .  
Almost Empty  
In single device configuration, queue is more than  
half full when WEXO / HALF goes low.  
In depth expansion configuration, WEXO / HALF is  
connected to WEXI of next device in the Daisy  
Chain.  
Write Expansion  
Out/Half Full  
26  
Output  
WEXO / HALF  
22, 33, 43, 49, 56  
30, 35, 40, 46, 51,  
55, 62  
Power  
Vcc  
N/A  
N/A  
5V power supply.  
0V Ground.  
Ground  
GND  
Table 1. Pin Descriptions (Continued)  
MAY 2003  
5F118C  
Page 6 of 26  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Symbol  
Rating  
Com’l & Ind’l  
Unit  
NOTES:  
Terminal Voltage with  
respect to GND  
Absolute Max Ratings are for reference only. Permanent damage to the  
device may occur if extended period of operation is outside this range.  
Standard operation should fall within the Recommended Operating  
Conditions.  
-0.5 to + 7  
V
VTERM  
Storage Temperature  
DC Output Current  
-55 to +125  
-50 to +50  
°C  
TSTG  
IOUT  
mA  
Table 2. Absolute Maximum Ratings  
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
Commercial  
Industrial  
Clock = 10ns, 15ns, 20ns  
Clock = 10ns, 15ns, 20ns  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Min.  
Typ.  
Max.  
Unit  
Recommended Operating Conditions  
Supply Voltage Com’l/Ind’l  
4.5  
0
5.0  
0
5.5  
0
4.5  
0
5.0  
0
5.5  
0
V
V
V
GND  
CC  
Supply Voltage  
Input High Voltage  
Com’l/Ind’l  
2.0  
-
-
-
-
-
5.5  
0.8  
70  
2.0  
-
-
-
-
-
5.5  
0.8  
70  
V
V
VIH  
Input Low Voltage  
VIL  
TA  
TA  
Com’l/Ind’l  
Operating Temperature  
Commercial  
0
0
°C  
°C  
Operating Temperature  
-40  
85  
-40  
85  
Industrial  
DC Electrical Characteristics  
Input Leakage Current (any  
(1)  
-10  
-10  
2.4  
-
-
-
10  
10  
-
-10  
-10  
2.4  
-
-
-
10  
10  
-
µA  
µA  
V
ILI  
input)  
Output Leakage Current  
ILO  
Output Logic “1” Voltage,  
IOH=-2mA  
VOH  
Output Logic “0” Voltage,  
-
-
0.4  
-
-
0.4  
V
VOL  
IOL = 8mA  
Power Consumption  
Active Power Supply  
Current  
CC1(2,3)  
-
-
-
-
30  
5
-
-
-
-
30  
5
mA  
mA  
I
I
CC2(4)  
Standby Current  
Table 3. DC Specifications  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 7 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Capacitance at 1.0MHz Ambient Temperature (25°C)  
Symbol  
Parameter  
Conditions  
Max.  
Unit  
(2)  
Input Capacitance  
VIN= 0V  
10  
pF  
CIN  
(2,4)  
Output Capacitance  
VOUT= 0V  
10  
pF  
COUT  
NOTES:  
1.  
2.  
3.  
4.  
Measurement with 0.4<=VIN<=Vcc  
With output tri-stated ( OE = High)  
Icc(1,2) is measured with WCLK and RCLK at 20 MHz  
Design simulated, not tested.  
Table 3. DC Specifications (Continued)  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 8 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Commercial & Industrial  
FQ245-10  
FQ235-10  
FQ225-10  
FQ215-10  
FQ205-10  
FQ245-15  
FQ235-15  
FQ225-15  
FQ215-15  
FQ205-15  
FQ245-20  
FQ235-20  
FQ225-20  
FQ215-20  
FQ205-20  
Min.  
-
2
Max.  
Min.  
-
Max.  
66  
Min.  
-
Max.  
50  
Unit  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Symbol  
fs  
Parameter  
Clock Cycle Frequency  
100  
6.5  
-
tA  
Data Access Time  
2
15  
6
10  
-
2
20  
8
12  
-
tWCLK  
tWCLKH  
tWCLKL  
tRCLK  
tRCLKH  
tRCLKL  
tDS  
Write Clock Cycle Time  
Write Clock High Time  
Write Clock Low Time  
Read Clock Cycle Time  
Read Clock High Time  
10  
4.5  
4.5  
10  
4.5  
4.5  
3
-
-
-
-
6
-
8
-
-
15  
6
-
20  
8
-
-
-
-
Read Clock Low Time  
-
6
-
8
-
Data Set-up Time  
-
4
-
5
-
tDH  
Data Hold Time  
0.5  
3
-
1
-
1
-
tENS  
Enable Set-up Time  
-
4
-
5
-
tENH  
tRST  
Enable Hold Time  
Reset Pulse Width(1)  
0.5  
10  
8
-
1
-
1
-
-
15  
10  
10  
-
-
20  
12  
12  
-
-
tRSTS  
tRSTR  
tRSTF  
tOLZ  
Reset Set-up Time  
-
-
-
Reset Recovery Time  
8
-
-
-
Reset to Flag and Output Time  
Output Enable to Output in Low-Z(2)  
Output Enable to Output Valid  
Output Enable to Output in High-Z(2)  
Write Clock to Full Flag  
Read Clock to Empty Flag  
Clock to Programmable Almost-Full Flag  
Clock to Programmable Almost-Empty Flag  
Clock to Half-Full Flag  
Clock to Expansion Out  
Expansion In Pulse Width  
Expansion In Set-Up Time  
-
15  
-
20  
-
20  
-
0
0
0
tOE  
3
6
3
8
3
10  
10  
12  
12  
26  
26  
26  
12  
-
tOHZ  
tFULL  
tEMPTY  
tPRAF  
tPRAE  
tHALF  
tXO  
3
6
3
8
3
-
6.5  
6.5  
17  
17  
17  
6.5  
-
-
10  
10  
24  
24  
24  
10  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tXI  
3
6.5  
5
8
tXIS  
3.5  
-
-
8
-
Skew time between Read Clock & Write  
Clock for Full Flag  
tSKEW1  
tSKEW2  
5
5
-
-
6
6
-
-
8
8
-
-
ns  
ns  
Skew time between Read Clock & Write  
Clock for Empty Flag  
NOTES:  
1.  
2.  
Pulse widths less than minimum values are not allowed.  
Design simulated, not tested.  
Table 4. AC Electrical Characteristics  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 9 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Input Pulse Levels  
GND to 3.0V  
Input Rise/Fall Times  
3ns  
Input Timing Reference Levels  
Output Reference Levels  
1.5V  
1.5V  
Output Load*, clock = 10ns, 15ns, 20ns See Figure 4  
*Include jig and scope capacitances  
Table 5. AC Test Condition  
5V  
1.1k Ω  
D.U.T.  
30pF*  
680Ω  
Figure 4. Output Load  
for clock = 10ns, 15ns, 20ns  
*Includes jig and scope capacitances.  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 10 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Pin Functions  
Reset is required to initialize Write and Read pointers to the first position of the queue by setting RST  
low. FULL and PRAF will go high; EMPTY and PRAE will go low. All data outputs will go low.  
Previous programmed configurations will not be maintained.  
RST  
Writes data into queue during low to high transitions of WCLK if WEN is set low. Synchronizes  
FULL and PRAF flags. WCLK and RCLK are independent of each other.  
WCLK  
Controls write operation into queue or offset registers during low to high transition of WCLK.  
WEN  
LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK  
respectively for parallel programming. Use in conjunction with WEN / REN .  
LOAD  
In single device configuration, FIRST is set low. In depth expansion configuration, FIRST is set low for  
the first device and set high for other devices in the Daisy Chain.  
FIRST  
WEXI  
In single device configuration, WEXI is set low. In depth expansion configuration, WEXI is connected to  
WEXO of previous device in the Daisy Chain.  
18 - bit wide input data bus.  
D17-0  
Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the  
EMPTY and PRAE flags. RCLK and WCLK are independent of each other.  
RCLK  
Reads data from queue during low to high transitions of RCLK if REN is set to low. This also advances  
the Read pointer of the queue.  
REN  
OE  
Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers  
(High-Z). OE does not control advancement of Read pointer.  
18 - bit wide output data bus.  
Q17-0  
In depth expansion configuration, REXO is connected to REXI of next device in the Daisy Chain.  
REXO  
FULL  
Queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further  
writes into the queue and prevents advancement of Write pointer. Refer to Table 8 for behavior of FULL .  
Queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further  
reads from the queue and prevents advancement of Read pointer. Refer to Table 8 for behavior of  
EMPTY .  
EMPTY  
PRAF  
Queue is almost full when PRAF goes low during the low to high transition of WCLK. PRAF goes high  
during the low to high transition of RCLK. Default (Full-offset) or programmed offset values determine  
the status of PRAF. Refer to Table 8 for behavior of PRAF.  
Queue is almost empty when PRAE goes low during the low to high transition of RCLK. PRAE goes  
high during the low to high transition of WCLK. Default (Empty+offset) or programmed offset values  
determine the status of PRAE . Refer to Table 8 for behavior of PRAE .  
PRAE  
In single device configuration, queue is more than half full when HALF goes low during the low to high  
transition of WCLK. Queue is less than half full when HALF goes high during the low to high transition  
of RCLK. Refer to Table 8 for details. In depth expansion configuration, WEXO is connected to  
WEXI of next device in the Daisy Chain  
WEXO / HALF  
In single device configuration, REXI is set low. In depth expansion configuration, REXI is connected to  
REXI  
5F118C  
REXO of previous device in the Daisy Chain.  
MAY 2003  
Page 11 of 26  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
WCLK RCLK  
LOAD  
WEN  
REN  
Selection / Sequence  
Parallel write to  
registers:  
1. PRAE  
2. PRAF  
Parallel write to offset  
registers:  
0
0
0
1
1
0
X
Empty Offset  
Full Offset  
Parallel read  
Parallel read from offset  
registers:  
Empty Offset  
Full Offset  
from registers:  
X
1. PRAE  
2. PRAF  
X
1
1
0
1
X
X
X
No Operation  
Write Memory  
X
1
1
X
1
0
1
X
X
Read Memory  
No Operation  
X
Figure 5. Programmable Flag Offset Programming Sequence  
Device  
PRAF Programming (bits)  
PRAE Programming (bits)  
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
D/Q11-0  
D/Q11-0  
D/Q10-0  
D/Q9-0  
D/Q8-0  
D/Q7-0  
D/Q10-0  
D/Q9-0  
D/Q8-0  
D/Q7-0  
Table 6. Parallel Offset Register Data Mapping Table  
Default  
007FH  
007FH  
007FH  
003FH  
001FH  
Device  
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
Table 7. Default Values of Offset Registers  
MAY 2003  
5F118C  
Page 12 of 26  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
FQ245 4,096 x 18  
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9  
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
PRAE  
PRAF  
1st Cycle  
2nd Cycle  
11  
11  
10  
10  
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
9
9
FQ235 2,048 x 18  
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
PRAE  
PRAF  
1st Cycle  
2nd Cycle  
10  
10  
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
9
9
FQ225 1,024 x 18  
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
PRAE  
PRAF  
1st Cycle  
2nd Cycle  
FQ215 512 x 18  
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
1st Cycle PRAE  
2nd Cycle PRAF  
FQ205 256 x 18  
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
1st Cycle PRAE  
2nd Cycle PRAF  
# of Bits for Offset Registers  
12 bits for FQ245  
11 bits for FQ235  
10 bits for FQ225  
9 bits for FQ215  
8 bits for FQ205  
Note: Don’t Care applies to all unused bits  
Figure 6. Parallel Offset Write/Read Cycles Diagram  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 13 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
FQ245  
0
FULL  
PRAF  
HALF  
PRAE  
EMPTY  
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 2,048  
2,049 to [4,096-(x+1)]  
(4,096 -x(2)) to 4,095  
4,096  
H
H
H
H
L
FQ235  
0
FULL  
PRAF  
HALF  
PRAE  
EMPTY  
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 1,024  
1,025 to [2,048-(x+1)]  
(2,048 -x(2)) to 2,047  
2,048  
H
H
H
H
L
FQ225  
0
FULL  
PRAF  
HALF  
PRAE  
EMPTY  
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 512  
513 to [1,024-(x+1)]  
(1,024 –x(2)) to 1,023  
1,024  
H
H
H
H
L
FQ215  
0
FULL  
PRAF  
HALF  
PRAE  
EMPTY  
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 256  
257 to [512-(x+1)]  
(512 -x(2)) to 511  
512  
H
H
H
H
L
FQ205  
0
FULL  
PRAF  
HALF  
PRAE  
EMPTY  
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 128  
129 to [256-(x+1)]  
(256 –x(2)) to 255  
256  
H
H
H
H
L
NOTES:  
1.  
2.  
y = PRAE offset. Default Values: FQ205 y = 31, FQ215 y = 63, FQ245/FQ235/FQ225 y = 127.  
x = PRAF offset. Default Values: FQ205 x = 31, FQ215 x = 63, FQ245/FQ235/FQ225 x = 127.  
Table 8. Status Flags  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 14 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Timing Diagrams  
tRST  
RST  
REN, WEN, LOAD  
EMPTY, PRAE  
FULL,PRAF,HALF  
Q17 - 0  
tRSTS  
tRSTR  
tRSTF  
tRSTF  
tRSTF  
= 1 (1)  
OE  
= 0  
OE  
NOTES:  
1.  
2.  
After reset, the outputs will be low if OE = 0 or tri-state if OE =1.  
The clocks (RCLK, WCLK) can be free-running during reset.  
Diagram 1. Reset Timing  
MAY 2003  
5F118C  
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Page 15 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
tWCLK  
tWCLKH  
tWCLKL  
WCLK  
D17 - 0  
tDS  
tDH  
Data Valid  
tENH  
tENS  
No Operation  
WEN  
FULL  
RCLK  
tFULL  
tFULL  
tSKEW1(1)  
REN  
NOTES:  
1.  
tSKEW1 is the minimum time between a rising RCLK edge and rising WCLK edge to guarantee that FULL will go high  
during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is equal to or less than  
tSKEW1, then FULL may not change state until the next WCLK edge.  
Diagram 2. Write Cycle Timing  
MAY 2003  
5F118C  
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Page 16 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
tRCLK  
tRCLKH  
tRCLKL  
RCLK  
tENS  
tENH  
REN  
tEMPTY  
tA  
tEMPTY  
EMPTY  
Valid Data  
Q17 - 0  
tOLZ  
tOHZ  
tOE  
OE  
WCLK  
WEN  
1.  
tSKEW2 (1)  
NOTES:  
tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EMPTY will go  
high during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is  
less than tSKEW2, then EMPTY may not change state until the next RCLK edge.  
Diagram 3. Read Cycle Timing  
MAY 2003  
5F118C  
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Page 17 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
WCLK  
D17 - 0  
tDS  
DW1  
DW3  
DW2  
DW4  
DW5  
tENS  
WEN  
tFRL(1)  
tSKEW2  
RCLK  
tEMPTY  
EMPTY  
REN  
tENS  
tA  
tA  
DW1  
DW2  
Q17 - 0  
OE  
tOLZ  
tOE  
NOTES:  
1.  
tFRL is the latency from first write to first Read. When tSKEW2 is greater than or equal to minimum specification, tFRL (maximum) = tRCLK +  
tSKEW2. When tSKEW2 is less than minimum specification, tFRL (maximum) equals either 2* tRCLK + tSKEW2 or tRCLK + tSKEW2.  
The Latency Timing applies only at the Empty Boundary ( EMPTY = Low).  
Diagram 4. First Data Word Latency after Reset with Simultaneous Read and Write  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 18 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
No Write  
No Write  
WCLK  
D17 - 0  
(1)  
(1)  
tDS  
tSKEW 1  
tDS  
tSKEW 1  
Data Write  
Data Write  
tFULL  
tFULL  
tFULL  
FULL  
WEN  
RCLK  
tENS  
tENH  
tENS  
tENH  
REN  
OE  
LOW  
tA  
tA  
Q17 - 0  
Output Register Data  
Data Read  
Next Data Read  
NOTES:  
1.  
tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FULL will go  
high during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less  
than tSKEW1, then FULL may not change state until the next WCLK edge.  
Diagram 5. Full Flag Timing  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 19 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
WCLK  
D17 - 0  
tDS  
tDS  
DW1  
tENH  
DW2  
tENH  
tENS  
tENS  
WEN  
(1)  
(1)  
tFRL  
tFRL  
tSKEW2  
tSKEW2  
RCLK  
tEMPTY  
tEMPTY  
tEMPTY  
EMPTY  
REN  
LOW  
OE  
tA  
Output Register Data  
DW1  
Q17 - 0  
NOTES:  
1.  
tFRL is the latency from first write to first Read. When tSKEW2 is greater than or equal to minimum specification, tFRL (maximum) = tRCLK + t SKEW2.  
When tSKEW2 less than minimum specification, tFRL (maximum) equals either 2 * tRCLK + tSKEW2, or tRCLK + tSKEW2. The Latency Timing  
applies only at the Empty Boundary ( EMPTY = Low).  
Diagram 6. Empty Flag Timing  
MAY 2003  
5F118C  
Page 20 of 26  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
tWCLK  
tWCLKH  
tWCLKL  
tENS  
WCLK  
LOAD  
tENH  
tENS  
tDS  
WEN  
D11 - 0  
tDH  
PRAE offset  
offset  
offset  
offset  
PRAF  
PRAE  
PRAF  
Diagram 7. Write Programmable Registers  
tRCLK  
tRCLKH  
tRCLKL  
RCLK  
tENS  
tENH  
LOAD  
REN  
tENS  
tA  
PRAF  
PRAEoffset  
offset  
Q11 - 0  
PRAEoffset  
PRAF  
offset  
Diagram 8. Read Programmable Registers  
tWCLKH  
tWCLKL  
WCLK  
tENH  
tENS  
WEN  
tPRAE  
y + 1 words in Queue  
PRAE  
y words in Queue  
y words in Queue  
tPRAE  
RCLK  
tENS  
tENH  
REN  
NOTES:  
1.  
y = PRAE offset.  
Diagram 9. Programmable Almost-Empty Flag Timing  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 21 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
tWCLKH  
tWCLKL  
WCLK  
WEN  
PRAF  
RCLK  
tENH  
tENS  
tPRAF  
D - x words in Queue  
memory(2)  
D - (x+1) words in Queue memory(1)  
D - (x+1) words in Queue  
memory(1)  
tPRAF  
tENH  
tENS  
REN  
NOTES:  
1.  
x = PRAF offset.  
2.  
D = maximum queue depth = 256 words for FQ205; 512 words for FQ215; 1,024 words for FQ225; 2,048 words for FQ235; and 4,096 words for FQ245.  
Diagram 10. Programmable Almost-Full Flag Timing  
tWCLKH  
tWCLKL  
WCLK  
WEN  
tENH  
tENS  
tHALF  
D/2 + 1 words in  
Queue memory(1)  
D/2 words in Queue memory(1)  
D/2 words in Queue  
memory(1)  
HALF  
tHALF  
RCLK  
REN  
tENH  
tENS  
NOTES:  
1.  
D = maximum queue depth = 256 words for FQ205; 512 words for FQ215; 1,024 words for FQ225; 2,048 words for FQ235; and 4,096 words for FQ245.  
Diagram 11. Half-Full Flag Timing  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 22 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
WCLK  
WEXO  
Note 1  
tXO  
tXO  
tENS  
WEN  
NOTES:  
1.  
Write to Last Physical Location.  
Diagram 12. Write Expansion Out Timing  
RCLK  
REXO  
Note 1  
tXO  
tXO  
tENS  
REN  
NOTES:  
1.  
Read from Last Physical Location.  
Diagram 13. Read Expansion Out Timing  
tXI  
WEXI  
tXIS  
WCLK  
Diagram 14. Write Expansion in Timing  
tXI  
REXI  
tXIS  
RCLK  
Diagram 15. Read Expansion in Timing  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 23 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Width Expansion Configuration  
Simply connecting together the control signals of multiple devices may increase word width. Status flags can be detected  
from any one device. The exceptions are the Empty Flag and Full Flag. Because of variations in skew between RCLK and  
WCLK, it is possible for flag assertion and de-assertion to vary by one cycle between FIFOs. To avoid problems the user  
must create composite flags by ANDing the Empty Flags of every FIFO, and separately ANDing all Full Flags. Figure 7  
demonstrates a 36-bit width by using two FQ245 / 235 / 225 / 215 / 205s. Any word width can be attained by adding  
additional FQ245 / 235 / 225 / 215 / 205s.  
Block Diagram of Synchronous Queue  
4,096 x 36 / 2,048 x 36 / 1,024 x 36 / 512 x 36 / 256 x 36  
RESET (RST )  
RESET (RST )  
18  
36  
18  
DATA IN (D)  
READ CLOCK (RCLK)  
READ ENABLE (REN )  
OUTPUT ENABLE (OE )  
WRITE CLOCK (WCLK)  
WRITE ENABLE (WEN )  
LOAD ( LOAD )  
PRAF  
PROGRAMMABLE (  
)
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
PROGRAMMABLE (PRAE )  
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
HALF- FULL (HALF)  
EMPTY  
36  
EMPTY FLAG (  
18 DATA OUT (Q)  
)
FULL  
FULL  
EMPTY  
EMPTY  
FULL  
(
)
FULL  
18  
FIRST LOAD (  
)
FIRST  
WRITE EXPANSION IN (WEXI)  
READ EXPANSION IN ( REXI )  
NOTES:  
1. Do not connect any output control signals directly together.  
Figure 7. Width Expansion Configuration  
MAY 2003  
5F118C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 24 of 26  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Depth Expansion Configuration (with Programmable Flags)  
These devices can easily be adapted to applications requiring more than 4,096 / 2,048 / 1,024 / 512 / 256 words of buffering.  
Figure 8 shows Depth Expansion using three FQ245 / 235 / 225 / 215 / 205s. Maximum depth is limited only by signal loading.  
Follow these steps:  
•
•
•
•
•
•
•
The first device must be designated by grounding the First Load ( FIRST ) control input.  
All other devices must have FIRST in the high state.  
The Write Expansion Out ( WEXO ) pin of each device must be tied to the Write Expansion In ( WEXI ) pin of the next device.  
The Read Expansion Out ( REXO ) pin of each device must be tied to the Read Expansion In ( REXI ) pin of the next device.  
All Load ( LOAD ) pins are tied together.  
The Half-Full Flag ( HALF ) is not available in this Depth Expansion Configuration.  
EMPTY , FULL , PRAF , and PRAE are created with composite flags by ORing together every respective flags for  
monitoring. The composite PRAF and PRAE flags are not precise.  
Block Diagram of Synchronous Queue  
12,288 x 18 / 6,144 x 18 / 3,072 x 18 / 1,536 x 18 / 768 x 18  
WEXO  
WCLK  
REXO  
WEN  
RST  
RCLK  
REN  
OE  
Q
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
LOAD  
D
Vcc  
FIRST  
FULL  
PRAF  
EMPTY  
PRAE  
WEXI  
REXI  
WEXO  
WCLK  
REXO  
WEN  
RST  
RCLK  
REN  
OE  
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
LOAD  
DATA IN  
D
Q
DATA OUT  
Vcc  
FIRST  
FULL  
PRAF  
EMPTY  
PRAE  
REXI  
WEXI  
WEXO  
WCLK  
REXO  
RCLK  
WRITE CLOCK  
WRITE ENABLE  
RESET  
WEN  
RST  
READ CLOCK  
REN  
OE  
Q
READ ENABLE  
OUTPUT ENABLE  
FQ245  
FQ235  
FQ225  
FQ215  
FQ205  
D
LOAD  
FULL  
LOAD  
EMPTY  
PRAE  
FULL  
PRAF  
EMPTY  
PRAE  
PRAF  
WEXI REXI  
FIRST LOAD (FIRST)  
Figure 8. Block Diagram of Multiple Devices with Programmable Flags used in Depth Expansion Configuration  
MAY 2003  
5F118C  
Page 25 of 26  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQ245 · FQ235 · FQ225 · FQ215 · FQ205  
FlexQTMI  
Order Information:  
HBA  
Device Family  
Device Type  
Power†  
Speed (ns)*  
Package** Temperature Range  
XX  
FQ  
XXX  
245 (4,096 x 18)  
X
Low  
XX  
XX  
PF  
X
10 – 100 MHz  
Blank – Commercial (0°C to 70°C)  
235 (2,048 x 18)  
225 (1,024 x 18)  
215 (512 x 18)  
205 (256 x 18)  
15 – 66 MHz  
20 – 50 MHz  
TF  
I – Industrial (-40° to 85°C)  
†Power – Low (LB)  
*Speed – Slower speeds available upon request.  
**Package – 64 pin Plastic Thin Quad Flat Pack (TQFP), 64 pin Slim Thin Quad Flat Pack (STQFP)  
Example:  
FQ235LB15TF  
FQ225LB10PFI  
(32k x 18, 15ns, Commercial temp)  
(16k x 18, 10ns, Industrial temp)  
Document Revision History:  
4/29/03 pg. 3, 5, 6, 7, 8, 9, 11, 14, 15, 16, 17, 18, 22, 24  
USA  
2107 North First Street, Suite 415  
San Jose, CA 95131, USA  
www.hba.com  
Taiwan  
Tel: 408.453.8885  
Fax: 408.453.8886  
No. 81, Suite 8F-9, Shui-Lee Rd.  
Hsinchu, Taiwan, R.O.C.  
www.hba.com  
Tel: 886.3.516.9118  
Fax: 886.3.516.9181  
MAY 2003  
5F118C  
Page 26 of 26  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  

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