A67P0618E-3.2IF_技术文档

A67P0618/A67P9336 Series

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL^TMSRAM

Document Title

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL^TMSRAM

Revision History

Rev. No. History

Issue Date

Remark

0.0

Initial issue

September, 20, 2004

Preliminary

0.1

0.2

Add Pb-Free package type.

January 27, 2006

March 2, 2006

Modify DC specification to exact value

1.0

Add –I grade

June 1, 2007

Final

(June, 2007, Version 1.0)

AMIC Technology, Corp.

A67P0618/A67P9336 Series

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL^TMSRAM

Three separate chip enables allow wide range of

Features

Fast access time:

2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)

Zero Bus Latency between READ and WRITE cycles

allows 100% bus utilization

Signal +2.5V ± 5% power supply

Individual Byte Write control capability

options for CE control, address pipelining

Internally self-timed write cycle

Selectable BURST mode (Linear or Interleaved)

SLEEP mode (ZZ pin) provided

Available in 100 pin LQFP package

Industrial operating temperature range: -25°C to +85°C

for -I series

Clock enable (

) pin to enable clock and suspend

CEN

operations

All Pb-free (lead-free) product are RoHS compliant

Clock-controlled and registered address, data and

control signals

Registered output for pipelined applications

General Description

The AMIC Zero Bus Latency (ZeBL^TM) SRAM family

employs high-speed, low-power CMOS designs using an

advanced CMOS process.

Write cycles are internally self-time and synchronous with

the rising edge of the clock input and when R/

is Low.

W

The feature simplified the write interface. Individual Byte

The A67P0618, A67P9336 SRAMs integrate a 1M X 18,

512K X 36 SRAM core with advanced synchronous

peripheral circuitry and a 2-bit burst counter. These SRAMs

are optimized for 100 percent bus utilization without the

insertion of any wait cycles during Write-Read alternation.

The positive edge triggered single clock input (CLK) controls

all synchronous inputs passing through the registers. The

synchronous inputs include all address, all data inputs,

enables allow individual bytes to be written. controls

BW1

controls I/Oc pins;

I/Oa pins;

controls I/Ob pins;

BW3

BW2

and

controls I/Od pins. Cycle types can only be

BW4

defined when an address is loaded.

The SRAM operates from a +2.5V power supply, and all

inputs and outputs are LVTTL-compatible. The device is

ideally suited for high bandwidth utilization systems.

active low chip enable (

), two additional chip enables for

CE

easy depth expansion (CE2,

), cycle start input

CE2

(ADV/

LD

enables (

), synchronous clock enable (

), byte write

CEN

) and read/write (R/ ).

,

BW4

W

BW1 BW2

BW3

Asynchronous inputs include the output enable (

), clock

OE

(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst

mode (MODE). Burst Mode can provide either interleaved or

linear operation, burst operation can be initiated by

synchronous address Advance/Load (ADV/

) pin in Low

LD

state. Subsequent burst address can be internally

generated by the chip and controlled by the same input pin

ADV/

in High state.

LD

(June, 2007, Version 1.0)

2

AMIC Technology, Corp.

A67P0618/A67P9336 Series

Pin Configuration

512K x 36

1M x 18

I/Oc⁸

I/Oc0

NC

1

2

3

4

5

6

80

A10

NC

I/Ob8

I/Ob⁷

I/Ob6

VCCQ

79

I/Oc1

VCCQ

VSSQ

I/Oc2

I/Oc3

I/Oc4

NC

78

77

NC

VCCQ

VSSQ

NC

76

75

74

VSSQ

NC

VSSQ

I/Ob5

7

I/Oa⁰

I/Ob4

NC

I/Ob⁸

8

I/Ob3

I/Oa1

73

72

9

I/Ob7

I/Oc5

VSSQ

VCCQ

I/Oa2

I/Ob2

VSSQ

VCCQ

10

11

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VSSQ

VCCQ

VSSQ

VCCQ

12

13

14

15

16

I/Oa3

I/Oa4

VSS

VCC

I/Ob1

I/Ob0

VSS

VCC

I/Oc6

I/Oc7

VCC

I/Ob6

I/Ob5

A67P0618E

A67P9336E

VCC

VSS

VCC

VSS

ZZ

17

18

I/Ob₄

I/Ob3

VCCQ

VSSQ

I/Ob2

I/Ob1

I/Ob0

NC

I/Od0

I/Od1

VCCQ

VSSQ

I/Od2

I/Od3

I/Od4

I/Oa5

I/Oa6

VCCQ

I/Oa7

I/Oa6

VCCQ

VSSQ

19

20

21

22

23

24

25

26

27

28

29

30

VSSQ

I/Oa7

I/Oa8

NC

I/Oa5

I/Oa4

I/Oa3

I/Oa2

NC

I/Od5

VSSQ

VCCQ

I/Od6

I/Od7

I/Od8

VCCQ

NC

VCCQ

NC

VCCQ

I/Oa1

I/Oa0

I/Oa8

NC

(June, 2007, Version 1.0)

3

AMIC Technology, Corp.

A67P0618/A67P9336 Series

Block Diagram (512K X 36)

ZZ

MODE

LOGIC

MODE

ADV/LD

CLK

CEN

LOGIC

CLK

BURST

LOGIC

ADDRESS

COUNTER

CLR

WRITE

ADDRESS

REGISTER

ADDRESS

REGISTER

ADDRESS

REGISTERS

A0-A18

9

BYTEa

WRITE

DRIVER

9

BYTEb

WRITE

DRIVER

OUTPUT

REGISTERS

&

OUTPUT

BUFFERS

512K x 9 x 4

MEMORY

ARRAY

WRITE

REGISTRY

&

CONTROL

LOGIC

ADV/LD

R/W

BW1

I/Os

SENSE

AMPS

BYTEc

WRITE

DRIVER

BW2

BW3

BW4

BYTEd

WRITE

DRIVER

DATA-IN

REGISTERS

DATA-IN

REGISTERS

CE

CHIP

ENABLE

LOGIC

PIPELINED

ENABLE

LOGIC

CE2

OUTPUT

ENABLE

LOGIC

OE

(June, 2007, Version 1.0)

4

AMIC Technology, Corp.

A67P0618/A67P9336 Series

Block Diagram (1M X 18)

ZZ

MODE

LOGIC

MODE

ADV/LD

CLK

CEN

BURST

LOGIC

CLK

ADDRESS

COUNTER

CLR

WRITE

ADDRESS

REGISTER

ADDRESS

REGISTER

ADDRESS

REGISTERS

A0-A19

9

BYTEa

WRITE

DRIVER

9

WRITE

REGISTRY

&

CONTROL

LOGIC

1M X 9 X 2

MEMORY

ARRAY

OUTPUT

REGISTERS

&

OUTPUT

BUFFERS

ADV/LD

R/W

I/OS

SENSE

AMPS

BYTEb

WRITE

DRIVER

BW1

BW2

DATA-IN

REGISTERS

DATA-IN

REGISTERS

CE

CHIP

ENABLE

LOGIC

PIPELINED

ENABLE

LOGIC

CE2

OUTPUT

ENABLE

LOGIC

OE

(June, 2007, Version 1.0)

5

AMIC Technology, Corp.

A67P0618/A67P9336 Series

Pin Description

LQFP (X18)

Pin No.

Symbol

Description

LQFP (X36)

37

36

37

36

A0

A1

A2 - A9

Synchronous Address Inputs : These inputs are registered

and must meet the setup and hold times around the rising

edge of CLK. A0 and A1 are the two lest significant bits

(LSB) of the address field and set the internal burst counter if

burst is desired.

35, 34, 33, 32,

100, 99, 82, 81,

44, 45, 46, 47,

48, 49, 50, 83

84

35, 34, 33, 32,

100, 99, 82, 81,

45, 46, 47, 48,

49, 50, 83, 84

A11 - A18

A19

A10

80

44

93 (

94 (

)

93 (

94 (

95 (

)

Synchronous Byte Write Enables : These active low inputs

allow individual bytes to be written when a WRITE cycle is

active and must meet the setup and hold times around the

rising edge of CLK. BYTE WRITEs need to be asserted on

the same cycle as the address, BWs are associated with

BW1

BW2

BW3

BW1

BW2

BW3

BW2

96 (

)

BW4

addresses and apply to subsequent data.

controls I/Oa

BW1

pins;

controls I/Ob pins;

BW3

controls I/Oc pins;

BW2

controls I/Od pins.

BW4

89

Clock: This signal registers the address, data, chip enables,

byte write enables and burst control inputs on its rising edge.

All synchronous inputs must meet setup and hold times

around the clock are rising edge.

CLK

98

92

98

92

CE

Synchronous Chip Enable : This active low input is used to

enable the device. This input is sampled only when a new

external address is loaded (ADV/

LOW).

LD

CE2

Synchronous Chip Enable : This active low input is used to

enable the device and is sampled only when a new external

address is loaded (ADV/ LOW). This input can be used

LD

for memory depth expansion.

97

CE2

OE

Synchronous Chip Enable : This active high input is used to

enable the device and is sampled only when a new external

address is loaded (ADV/ LOW). This input can be used

LD

for memory depth expansion.

86

85

86

85

Output Enable : This active low asynchronous input enables

the data I/O output drivers.

ADV/

Synchronous Address Advance/Load : When HIGH, this

input is used to advance the internal burst counter,

controlling burst access after the external address is loaded.

LD

When HIGH, R/ is ignored. A LOW on this pin permits a

W

new address to be loaded at CLK rising edge.

87

CEN

Synchronous Clock Enable : This active low input permits

CLK to propagate throughout the device. When HIGH, the

device ignores the CLK input and effectively internally

extends the previous CLK cycle. This input must meet setup

and hold times around the rising edge of CLK.

(June, 2007, Version 1.0)

6

AMIC Technology, Corp.

A67P0618/A67P9336 Series

Pin Description (continued)

Pin No.

Symbol

Description

LQFP (X18)

LQFP (X36)

64

ZZ

Snooze Enable : This active high asynchronous input causes

the device to enter a low-power standby mode in which all

data in the memory array is retained. When active, all other

inputs are ignored.

88

R/

Read/Write : This active input determines the cycle type

W

when ADV/

is LOW. This is the only means for

LD

determining READs and WRITEs. READ cycles may not be

converted into WRITEs (and vice versa) other than by

loading a new address. A LOW on this pin permits BYTE

WRITE operations and must meet the setup and hold times

around the rising edge of CLK. Full bus width WRITEs occur

if all byte write enables are LOW.

74, 73, 72, 69, 68,

63, 62, 59, 58,

24, 23, 22, 19, 18

13, 12, 9, 8

51, 52, 53, 56, 57,

58, 59, 62, 63

68, 69, 72, 73, 74,

75, 78, 79, 80

1, 2, 3, 6, 7, 8, 9,

12, 13,

I/Oa

I/Ob

I/Oc

I/Od

SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins;

Byte “c” is I/Oc pins; Byte “d” is I/Od pins. Input data must

meet setup and hold times around CLK rising edge.

18, 19, 22, 23, 24,

25, 28, 29, 30

31

MODE

NC

Mode : This input selects the burst sequence. A LOW on this

pin selects linear burst. NC or HIGH on this pin selects

interleaved burst. Do not alter input state while device is

operating.

1, 2, 3, 6, 7, 25, 28,

29, 30, 38, 39,

42,43 51, 52, 53,

56, 57, 75, 78, 79,

95, 96

38,39,42,43

No Connect : These pins can be left floating or connected to

GND to minimize thermal impedance.

15, 41, 65, 91

14, 16, 66

VCC

Power Supply : See DC Electrical Characteristics and

Operating Conditions for range.

14, 16, 66

These pins do not have to be connected directly to VCC as

long as the input voltage is ≥ VIH. This input is not connected

to VCC bus internally.

4, 11, 20, 27,

54, 61, 70, 77

4, 11, 20, 27, 54,

61, 70, 77

VCCQ

Isolated Output Buffer Supply : See DC Electrical

Characteristics and Operating Conditions for range.

17, 40, 67, 90

VSS

Ground : GND.

5,10,21,26,

55,60,71,76

5,10,21,26,

55,60,71,76

VSSQ

Isolated Output Buffer Ground

(June, 2007, Version 1.0)

7

AMIC Technology, Corp.

A67P0618/A67P9336 Series

Truth Table (Notes 5 - 7)

Address

Used

CE2 ZZ ADV/ R/

LD

OE

X

L

CLK

I/O

Notes

CE CE2

W

BWx

X

CEN

L

Operation

Deselected Cycle,

Power-down

None

H

X

L

X

H

X

L

X

L

H

L

X

L→H High-Z

Deselected Cycle,

Power-down

None

L

X

H

X

H

X

L

X

L

Deselected Cycle,

Power-down

L

X

L

Continue Deselect

Cycle

None

X

H

X

H

X

H

X

H

X

H

L

X

L

1

READ Cycle

(Begin Burst)

External

L

L→H

Q

READ Cycle

X

L

X

L

H

L

X

L

1,7

2

(Continue Burst)

NOP/Dummy READ

(Begin Burst)

External

H

X

L

L→H High-Z

Dummy READ

(Continue Burst)

WRITE Cycle

(Begin Burst)

X

L

X

L

H

L

X

L

1,2,7

3

External

L

L→H

D

WRITE Cycle

(Continue Burst)

NOP/WRITE Abort

(Begin Burst)

X

L

X

L

H

L

X

L

1,3,7

2,3

None

H

X

L

L→H High-Z

WRITE Abort

(Continue Burst)

IGNORE Clock Edge

(Stall)

X

H

X

L

L→H High-Z 1,2,3,7

Current

None

H

X

L→H

-

4

SLEEP Mode

X

High-Z

Notes:

1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or

WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is

executed first.

2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE

Abort means a WRITE command is given, but no operation is performed.

3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the

output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their

requirements.

4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs

during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock

Edge cycle.

5. X means “Don’t Care.” H means logic HIGH. L means logic LOW.

= H means all byte write signals (

,

BWx

BW1 BW2

BW3

and

) are HIGH.

BWx

= L means one or more byte write signals are LOW.

BW4

6.

enables WRITEs to Byte “a” (I/Oa pins);

enables WRITEs to Byte “b” (I/Ob pins);

BW3

enables WRITEs to

BW1

BW2

Byte “c” (I/Oc pins);

enables WRITEs to Byte “d” (I/Od pins).

BW4

7. The address counter is incremented for all Continue Burst cycles.

(June, 2007, Version 1.0)

8

AMIC Technology, Corp.

A67P0618/A67P9336 Series

Partial Truth Table for READ/WRITE Commands (X18)

Operation

R/

W

BW1

BW2

READ

H

X

WRITE Byte “a”

WRITE Byte “b”

WRITE all bytes

WRITE Abort/NOP

L

H

L

H

L

H

Note : Using and BYTE WRITE(s), any one or more bytes may be written.

Partial Truth Table for READ/WRITE Commands (X36)

Operation

R/

BW3

X

W

BW1

BW2

BW4

READ

H

X

WRITE Byte “a”

WRITE Byte “b”

WRITE Byte “c”

WRITE Byte “d”

WRITE all bytes

WRITE Abort/NOP

L

H

L

H

L

H

L

H

L

H

L

H

Note : Using R/ and BYTE WRITE(s), any one or more bytes may be written.

W

Linear Burst Address Table (MODE = LOW)

First Address (External)

X . . . X00

Second Address (Internal)

X . . . X01

Third Address (Internal)

X . . . X10

Fourth Address (Internal)

X . . . X11

X . . . X01

X . . . X10

X . . . X11

X . . . X00

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X00

X . . . X01

X . . . X10

Interleaved Burst Address Table (MODE = HIGH or NC)

First Address (External)

X . . . X00

Second Address (Internal)

X . . . X01

Third Address (Internal)

X . . . X10

Fourth Address (Internal)

X . . . X11

X . . . X01

X . . . X00

X . . . X11

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X10

X . . . X01

X . . . X00

(June, 2007, Version 1.0)

9

AMIC Technology, Corp.

A67P0618/A67P9336 Series

Absolute Maximum Ratings*

*Comments

Power Supply Voltage (VCC) . . . . . . . . . . -0.3V to +3.6V

Voltage Relative to GND for any Pin Except VCC (Vin,

Vout) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V

Commercial Devices ( F ) Operating Temperature (Topr)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Industrial Devices ( I ) Operating Temperature (Topr) . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to 85°C

Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C

Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C

Storage Temperature (Tstg) . . . . . . . . . . -55°C to 125°C

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device.

These are stress ratings only. Functional operation of

this device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied or intended. Exposure to the absolute

maximum rating conditions for extended periods may

affect device reliability.

DC Electrical Characteristics and Operating Conditions

(0°C ≤ TA ≤ 70°C, -25°C ≤ TA ≤ 85°C, VCC, VCCQ = +2.5V± 5% unless otherwise noted)

Symbol

VIH

Parameter

Input High Voltage

Conditions

Min.

1.7

Max.

VCC+0.3

0.7

Unit

V

Note

1,2

VIL

Input Low Voltage

-0.3

-2.0

V

1,2

ILI

Input Leakage Current

Output Leakage Current

0V ≤ VIH ≤ VCC

4.0

μA

ILO

Output(s) disabled,

4.0

0V ≤ VIN≤ VCC

VOH

VOL

Output High Voltage

Output Low Voltage

Supply Voltage

IOH = -1.0mA

IOL = 1.0mA

2.0

V

1,3

1

0.4

VCC

VCCQ

2.375

2.625

VCC

Isolated Output Buffer Supply

1,4

Capacitance

Symbol

CI

Parameter

Conditions

T^A= 25°C; f = 1MHz

VCC = 2.5V

Typ.

Max.

4

Unit

pF

Note

Control Input Capacitance

Input/Output Capacitance (I/O)

Address Capacitance

3

4

3

6

CO

5

pF

CA

3.5

pF

Note : 1. All voltages referenced to VSS (GND).

2. Overshoot : VIH ≤ +3.6V for t ≤ tKHKH/2 for I ≤ 20mA

Undershoot : V^IL≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA

Power-up : V^IH≤ +2.675V and VCC ≤ 2.375V for t ≤ 200ms

3. The load used for V^OH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values.

AC I/O curves are available upon request.

4. VCC and VCCQ can be externally wired together to the same power supply.

5. This parameter is sampled.

(June, 2007, Version 1.0)

10

AMIC Technology, Corp.

A67P0618/A67P9336 Series

ICC Operating Condition and Maximum Limits

Max.

Symbol

Parameter

Unit

Conditions

-2.6

-2.8

-3.2

-3.5

-3.8

-4.2

Device selected; All inputs ≤ VIL

or ≥ VIH; Cycle time ≥ tKC (MIN);

VCC = MAX; Outputs open

Power Supply

Current : Operating

ICC

460

440

410

80

360

330

310

mA

Device deselected; VCC = MAX;

All inputs ≤ VSS+0.2 or ≥ VCC-

0.2; Cycle time ≥ tKC (MIN)

mA

ISB

Standby

80

Device deselected; VCC = MAX;

All inputs ≤ VIL; or ≥ VIH;

All inputs static;

I^SB1

120

CLK frequency=MAX

ZZ ≥ VCC-0.2V

Device deselected; VCC = MAX;

All inputs ≤VSS+0.2 or ≥ VCC-

0.2; All inputs static; CLK

frequency=0

ISB2

70

mA

Standby

ZZ ≤ 0.2V

ISB2Z

SLEEP Mode

ZZ ≥ VIH

(June, 2007, Version 1.0)

11

AMIC Technology, Corp.

A67P0618/A67P9336 Series

AC Characteristics (Note 4)

(0°C ≤ TA ≤ 70°C, -25°C ≤ TA ≤ 85°C, VCC = +2.5V± 5%)

-2.6

-2.8

-3.2

-3.5

-3.8

-4.2

Symbol

Parameter

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Clock

tKHKH

tKF

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

4.0

-

4.4

-

5.0

-

6.0

-

6.7

-

7.5

-

ns

MH

ns

250

227

200

166

150

133

tKHKL

tKLKH

1.7

-

2.0

-

2.0

-

2.2

-

2.5

-

3.0

-

ns

Output Times

tKHQV

tKHQX

tKHQX1

tKHQZ

tGLQV

tGLQX

tGHQZ

Clock to output valid

-

1.5

-

2.6

-

1.5

-

2.8

-

1.5

-

3.2

-

1.5

-

3.5

-

1.5

-

3.8

-

1.5

-

4.2

-

ns

Clock to output invalid

Clock to output in Low-Z

Clock to output in High-Z

OE to output valid

-

ns

1,2,3

4

2.6

-

2.8

-

3.0

3.2

-

3.0

3.5

-

3.0

3.8

-

3.5

4.2

-

0

1,2,3

OE to output in Low-Z

OE to output in High-Z

-

2.6

-

2.8

-

3.0

-

3.0

-

3.0

-

3.5

Setup Times

tAVKH

Address

1.2

-

1.4

-

1.4

-

1.5

-

1.5

-

1.5

-

ns

5

Clock enable (

)

CEN

tEVKH

tCVKH

Control signals

Data-in

tDVKH

Hold Times

tKHAX

Address

0.3

-

0.4

-

0.4

-

0.5

-

0.5

-

0.5

-

ns

5

Clock enable (

)

CEN

tKHEX

tKHCX

Control signals

Data-in

tKHDX

Notes: 1. This parameter is sampled.

2. Output loading is specified with C1=5pF as in Figure 2.

3. Transition is measured ±200mV from steady state voltage.

4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for

turnaround timing.

5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of

CLK when ADV/

is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with

LD

stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each

rising edge of CLK (when ADV/ is LOW) to remain enabled.

LD

(June, 2007, Version 1.0)

12

AMIC Technology, Corp.

A67P0618/A67P9336 Series

AC Test Conditions

Input Pulse Levels

GND to 2.5V

1.0ns

Input Rise and Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

1.25V

See Figures 1 and 2

+2.5V

1667Ω

Q

ZO=50Ω

50Ω

5pF

1538Ω

V^T=1.25V

Figure 1

Figure 2

Output Load Equivalent

(June, 2007, Version 1.0)

13

AMIC Technology, Corp.

A67P0618/A67P9336 Series

SLEEP Mode

SLEEP Mode is a low current “Power-down” mode in which

the device is deselected and current is reduced to I^SB2Z. This

duration of SLEEP Mode is dictated by the length of time the

ZZ is in a HIGH state. After entering SLEEP Mode, all inputs

except ZZ become disabled and all outputs go to High-Z.

The ZZ pin is asynchronous, active high input that causes the

device to enter SLEEP Mode. When the ZZ pin becomes

logic HIGH, ISB2Z is guaranteed after the time t^ZZIis met.

Any operation pending when entering SLEEP Mode is not

guaranteed to successfully complete. Therefore, SLEEP

Mode (READ or WRITE) must not be initiated until valid

pending operations are completed. Similarly, when exiting

SLEEP Mode during t^RZZ, only a DESELECT or READ cycle

should be given while the SRAM is transitioning out of

SLEEP Mode.

SLEEP Mode Electrical Characteristics

(VCC, VCCQ = +2.5V±5%)

Symbol

ISB2Z

tZZ

Parameter

Conditions

Min.

Max.

70

Unit

mA

ns

Note

Current during SLEEP Mode

ZZ active to input ignored

ZZ inactive to input sampled

ZZ active to snooze current

ZZ inactive to exit snooze current

ZZ ≥ VIH

-

0

-

2(tKHKH)

1

tRZZ

ns

tZZI

ns

tRZZI

0

ns

Note : 1. This parameter is sampled.

SLEEP Mode Waveform

CLK

t

ZZ

t

RZZ

ZZ

t

ZZI

I

SUPPLY

IISB2Z

tRZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Output

(Q)

High-Z

: Don't Care

(June, 2007, Version 1.0)

14

AMIC Technology, Corp.

A67P0618/A67P9336 Series

READ/WRITE Timing

1

2

3

4

5

6

7

8

9

10

t

KHKH

CLK

t

KHKL

t

EVKH

t

KHEX

tKLKH

CEN

t

CVKH

tKHCX

CE

ADV/

LD

R/W

BWx

ADDRESS

A2

A3

A4

t

A5

A6

A7

A1

t

AVKH

tKHAX

t

KHQV

KHQX1

t

KHQX

t

GLQV

t

KHQZ

t

DVKH

tKHDX

Q(A4+1)

I/O

D(A1)

D(A2)

D(A2+1)

Q(A3)

Q(A4)

D(A5)

Q(A6)

t

KHQX

t

GHQZ

t

GLQX

OE

COMMAND

BURST

WRITE

D(A2+1)

BURST

READ

Q(A4+1)

READ

Q(A4)

WRITE

D(A1)

WRITE

D(A2)

READ

Q(A3)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

: Don't Care

: Undefined

Note : 1. For this waveform, ZZ is tied LOW.

2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional.

3. represents three signals. When = 0, it represents = 0, = 0, CE2 = 1.

CE

CE2

4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The

most recent data may be from the input data register.

(June, 2007, Version 1.0)

15

AMIC Technology, Corp.

A67P0618/A67P9336 Series

NOP, STALL and Deselect Cycles

1

2

3

4

5

6

7

8

9

10

CLK

CEN

CE

ADV/

LD

R/W

BWx

ADDRESS

I/O

A1

A2

A3

A4

A5

t

KHQZ

D(A1)

Q(A2)

Q(A3)

D(A4)

Q(A5)

tKHQX

COMMAND

WRITE

D(A4)

CONTINUE

DESELECT

WRITE

D(A1)

READ

Q(A2)

READ

Q(A3)

READ

Q(A5)

STALL

NOP

DESELECT

: Don't Care

: Undefined

Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates

being used to create a “pause.” A WRITE is

= 0, CE2 = 1.

CEN

CE2

not performed during this cycle.

2. For this waveform, ZZ and

are tied LOW.

OE

represents three signals. When

3.

= 0, it represents

= 0,

CE

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The

most recent data may be from the input data register.

(June, 2007, Version 1.0)

16

AMIC Technology, Corp.

A67P0618/A67P9336 Series

Ordering Information

Part No.

Configure

Cycle Time / Access Time

Package

A67P0618E-4.2IF

A67P0618E-4.2F

A67P0618E-3.8IF

A67P0618E-3.8F

A67P0618E-3.5IF

A67P0618E-3.5F

A67P0618E-3.2IF

A67P0618E-3.2F

A67P0618E-2.8IF

A67P0618E-2.8F

A67P0618E-2.6IF

A67P0618E-2.6F

A67P9336E-4.2IF

A67P9336E-4.2F

A67P9336E-3.8IF

A67P9336E-3.8F

A67P9336E-3.5IF

A67P9336E-3.5F

A67P9336E-3.2IF

A67P9336E-3.2F

A67P9336E-2.8IF

A67P9336E-2.8F

A67P9336E-2.6IF

A67P9336E-2.6F

7.5ns / 4.2ns

6.7ns / 3.8ns

6.0ns / 3.5ns

5.0ns / 3.2ns

4.4ns / 2.8ns

4.0ns / 2.6ns

7.5ns / 4.2ns

6.7ns / 3.8ns

6.0ns / 3.5ns

5.0ns / 3.2ns

4.4ns / 2.8ns

4.0ns / 2.6ns

100L Pb-Free LQFP

1M X 18

512K X 36

Note: -I is for industrial operating temperature range -25ºC to +85ºC.

(June, 2007, Version 1.0)

17

AMIC Technology, Corp.

A67P0618/A67P9336 Series

Package Information

LQFP 100L Outline Dimensions

unit: inches/mm

H

E

A

2

A1

E

y

80

51

81

50

31

100

1

30

b

c

e

θ

Dimensions in inches

Dimensions in mm

Symbol

Min.

0.002

0.053

0.009

0.004

Nom.

-

Max.

Min.

0.05

1.35

0.22

0.09

Nom.

-

Max.

0.15

1.45

0.38

0.20

A1

A2

b

0.006

0.057

0.015

0.008

0.055

1.40

0.012

0.30

c

-

HE

E

0.866 BSC

0.787 BSC

0.630 BSC

0.551 BSC

0.026 BSC

0.024

22.00 BSC

20.00 BSC

16.00 BSC

14.00 BSC

0.65 BSC

0.60

HD

D

e

L

0.018

0.030

0.45

0.75

L1

y

0.039 REF

-

1.00 REF

-

0.004

-

0.10

θ

0°

3.5°

7°

0°

3.5°

7°

Notes:

1. Dimensions D and E do not include mold protrusion.

2. Dimensions b does not include dambar protrusion.

Total in excess of the b dimension at maximum material condition.

Dambar cannot be located on the lower radius of the foot.

(June, 2007, Version 1.0)

18

AMIC Technology, Corp.


型号：	A67P0618E-3.2IF
厂家：	AMIC TECHNOLOGY
描述：	ZBT SRAM, 1MX18, 3.2ns, CMOS, PQFP100, ROHS COMPLIANT, LQFP-100 时钟静态存储器内存集成电路
文件：	总18页 (文件大小：197K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A67P0618E-3.2IF [AMICC]

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