A67L06361E-7.5IF [AMICC]
ZBT SRAM, 1MX36, 7.5ns, CMOS, PQFP100;
| 型号： | A67L06361E-7.5IF |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | ZBT SRAM, 1MX36, 7.5ns, CMOS, PQFP100 存储 静态存储器 |
| 文件： | 总18页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A67L16181/A67L06361 Series
Preliminary
2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM
Document Title
2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
Initial issue
July 26, 2004
Preliminary
Change speed grade from cycle time to access time
February 17, 2005
PRELIMINARY (February, 2005, Version 0.1)
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Preliminary
2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM
Features
ꢀFast access time: 6.5/7.5/8.5 ns
ꢀ Clock-controlled and registered address, data and control
(153, 133, 117 MHz)
signals
ꢀZero Bus Latency between READ and WRITE cycles ꢀ Registered output for pipelined applications
allows 100% bus utilization
ꢀSignal +3.3V ± 5% power supply
ꢀIndividual Byte Write control capability
ꢀThree separate chip enables allow wide range of options
for CE control, address pipelining
ꢀInternally self-timed write cycle
ꢀSelectable BURST mode (Linear or Interleaved)
ꢀSLEEP mode (ZZ pin) provided
ꢀAvailable in 100 pin LQFP package
ꢀClock enable (
) pin to enable clock and suspend
CEN
operations
General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs
high-speed, low-power CMOS designs using an advanced
CMOS process.
by the chip and controlled by the same input pin ADV/
High state.
Write cycles are internally self-time and synchronous with the
in
LD
The A67L16181, A67L06361 SRAMs integrate a 2M X 18,
1M X 36 SRAM core with advanced synchronous peripheral
circuitry and a 2-bit burst counter. These SRAMs are
optimized for 100 percent bus utilization without the insertion
of any wait cycles during Write-Read alternation. The positive
edge triggered single clock input (CLK) controls all
synchronous inputs passing through the registers. The
synchronous inputs include all address, all data inputs, active
rising edge of the clock input and when R/ is Low. The
feature simplified the write interface. Individual Byte enables
W
allow individual bytes to be written. controls I/Oa pins;
BW1
controls I/Oc pins; and
controls I/Ob pins;
BW2
BW4
BW3
controls I/Od pins. Cycle types can only be defined when an
address is loaded.
The SRAM operates from a +3.3V power supply, and all
inputs and outputs are LVTTL-compatible. The device is
ideally suited for high bandwidth utilization systems.
low chip enable (
), two additional chip enables for easy
CE
depth expansion (CE2,
), cycle start input (ADV/
),
LD
), byte write enables
CE2
synchronous clock enable (
CEN
) and read/write (R/ ).
(
,
,
,
BW4
W
BW1 BW2
BW3
Asynchronous inputs include the output enable (
), clock
OE
(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst
mode (MODE). Burst Mode can provide either interleaved or
linear operation, burst operation can be initiated by
synchronous address Advance/Load (ADV/
) pin in Low
LD
state. Subsequent burst address can be internally generated
PRELIMINARY (February, 2005, Version 0.1)
2
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Pin Configuration
1M X 36
2M X 18
I/Oc8
I/Oc0
I/Oc1
NC
NC
NC
1
80
A10
NC
I/Ob8
I/Ob7
I/Ob6
VCCQ
2
79
3
78
77
NC
VCCQ
VSSQ
VCCQ
VSSQ
I/Oc2
I/Oc3
I/Oc4
4
VCCQ
5
76
75
74
VSSQ
NC
VSSQ
I/Ob5
I/Ob4
I/Ob3
I/Ob2
VSSQ
VCCQ
NC
6
7
I/Oa0
NC
I/Ob8
8
I/Oa1
73
72
9
I/Ob7
I/Oc5
VSSQ
VCCQ
I/Oa2
VSSQ
VCCQ
10
11
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSSQ
VCCQ
12
13
I/Oa3
I/Oa4
VSS
VSS
VCC
I/Ob1
I/Ob0
VSS
VSS
VCC
I/Oc6
I/Oc7
VSS
I/Ob6
I/Ob5
VSS
VCC
14
15
16
A67L16181E
A67L06361E
VCC
VCC
VCC
VSS
VSS
ZZ
ZZ
17
18
I/Od0
I/Od1
VCCQ
VSSQ
I/Od2
I/Od3
I/Od4
I/Ob4
I/Ob3
VCCQ
VSSQ
I/Ob2
I/Ob1
I/Ob0
NC
I/Oa5
I/Oa7
I/Oa6
VCCQ
VSSQ
19
20
21
22
23
24
25
26
27
28
29
30
I/Oa6
VCCQ
VSSQ
I/Oa7
I/Oa5
I/Oa4
I/Oa3
I/Oa2
I/Oa8
NC
NC
I/Od5
VSSQ
VSSQ
VSSQ
VSSQ
VCCQ
I/Od6
I/Od7
I/Od8
VCCQ
NC
VCCQ
I/Oa1
I/Oa0
I/Oa8
VCCQ
NC
NC
NC
NC
NC
PRELIMINARY (February, 2005, Version 0.1)
3
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Block Diagram (1M X 36)
ZZ
MODE
LOGIC
MODE
ADV/LD
CLK
LOGIC
CEN
CLK
BURST
LOGIC
ADDRESS
COUNTER
CLR
WRITE
ADDRESS
REGISTER
ADDRESS
REGISTERS
A0-A19
9
BYTEa
WRITE
DRIVER
9
9
9
9
9
9
9
BYTEb
WRITE
DRIVER
1MX9X4
WRITE
REGISTRY
&
CONTROL
LOGIC
I/Os
SENSE
AMPS
OUTPUT
BUFFERS
ADV/LD
R/W
MEMORY
ARRAY
BYTEc
WRITE
DRIVER
BW1
BW2
BW3
BW4
BYTEd
WRITE
DRIVER
DATA-IN
REGISTERS
CE
CHIP
ENABLE
LOGIC
FLOW-THROUGH
ENABLE
CE2
CE2
LOGIC
OUTPUT
ENABLE
LOGIC
OE
PRELIMINARY
(February, 2005, Version 0.1)
4
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Block Diagram (2M X 18)
ZZ
MODE
LOGIC
MODE
ADV/LD
CLK
LOGIC
CEN
CLK
BURST
LOGIC
ADDRESS
COUNTER
CLR
WRITE
ADDRESS
REGISTER
ADDRESS
REGISTERS
A0- A20
9
9
BYTEa
WRITE
DRIVER
9
9
2MX9X2
SENSE
WRITE
REGISTRY
&
CONTROL
LOGIC
ADV/LD
R/W
I/O
OUTPUT
BUFFERS
S
MEMORY
AMPS
ARRAY
BYTEb
WRITE
DRIVER
BW1
BW2
DATA-IN
REGISTERS
CE
CHIP
ENABLE
LOGIC
FLOW-
THROUGH
ENABLE LOGIC
CE2
CE2
OUTPUT
ENABLE
LOGIC
OE
PRELIMINARY
(February, 2005, Version 0.1)
5
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Pin Description
Pin No.
Symbol
Description
LQFP (X18)
LQFP (X36)
37
36
37
36
A0
A1
A2 – A9
Synchronous Address Inputs : These inputs are registered and
must meet the setup and hold times around the rising edge of
CLK. Pins 83 and 84 are reserved as address bits for higher-
density 9Mb and 18Mb DBA SRAMs, respectively. A0 and A1 are
the two lest significant bits (LSB) of the address field and set the
internal burst counter if burst is desired.
35,34,33,32,
100,99,82,81
44,45,46,47,
48,49,50,83,84
43
35,34,33,32,
100,99,82,81
45,46,47,48,
49,50,83,84,43
A11-A19
A20
A10
80
44
93 (
94 (
)
)
93 (
94 (
95 (
)
)
)
Synchronous Byte Write Enables : These active low inputs allow
individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of
CLK. BYTE WRITEs need to be asserted on the same cycle as
BW1
BW1
BW2
BW3
BW1
BW2
BW3
BW2
96 (
)
BW4
BW4
the address,
are associated with addresses and apply to
BWs
subsequent data.
controls I/Oa pins;
controls I/Ob pins;
BW1
BW2
controls I/Oc pins;
controls I/Od pins.
BW4
BW3
89
89
Clock : This signal registers the address, data, chip enables, byte
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
CLK
98
92
98
92
CE
Synchronous Chip Enable : This active low input is used to enable
the device. This input is sampled only when a new external
address is loaded (ADV/
LOW).
LD
CE2
Synchronous Chip Enable : This active low input is used to enable
the device and is sampled only when a new external address is
loaded (ADV/
expansion.
LOW). This input can be used for memory depth
LD
97
97
CE2
OE
Synchronous Chip Enable : This active high input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/
LD
memory depth expansion.
LOW). This input can be used for
86
85
86
85
Output Enable : This active low asynchronous input enables the
data I/O output drivers.
ADV/
Synchronous Address Advance/Load : When HIGH, this input is
used to advance the internal burst counter, controlling burst
LD
access after the external address is loaded. When HIGH, R/ is
W
ignored. A LOW on this pin permits a new address to be loaded at
CLK rising edge.
87
87
CEN
Synchronous Clock Enable : This active low input permits CLK to
propagate throughout the device. When HIGH, the device ignores
the CLK input and effectively internally extends the previous CLK
cycle. This input must meet setup and hold times around the
rising edge of CLK.
PRELIMINARY
(February, 2005, Version 0.1)
6
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Pin Description (continued)
Pin No.
Symbol
Description
LQFP (X18)
LQFP (X36)
64
64
ZZ
Snooze Enable : This active high asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When active, all other inputs are
ignored.
88
88
R/
Read/Write : This active input determines the cycle type when
W
ADV/
is LOW. This is the only means for determining READs
LD
and WRITEs. READ cycles may not be converted into WRITEs
(and vice versa) other than by loading a new address. A LOW on
this pin permits BYTE WRITE operations and must meet the setup
and hold times around the rising edge of CLK. Full bus width
WRITEs occur if all byte write enables are LOW.
52, 53, 56, 57,
58, 59, 62, 63, 51
68, 69, 72, 73, 74,
75, 78, 79, 80
2, 3, 6, 7, 8, 9, 12,
13,1
I/Oa
I/Ob
I/Oc
I/Od
SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins; Byte
“c” is I/Oc pins; Byte “d” is I/Od pins. Input data must meet setup
and hold times around CLK rising edge.
74, 73, 72, 69, 68
63, 62, 59, 58
24, 23, 22, 19, 18
13, 12, 9, 8
18, 19, 22, 23, 24,
25, 28, 29, 30
31
31
MODE
Mode: This input selects the burst sequence. A LOW on this pin
selects linear burst. NC or HIGH on this pin selects interleaved
burst. Do not alter input state while device is operating.
1, 2, 3, 6, 7, 25, 28,
29, 30, 38, 39, 42,
51, 52, 53, 56, 57,
75, 78, 79, 95, 96
38,39,42
NC
No Connect : These pins can be left floating or connected to GND
to minimize thermal impedance.
15, 16, 41, 65, 91
15, 16, 41, 65, 91
VCC
Power Supply
4, 11, 20, 27,
54, 61, 70, 77
4, 11, 20, 27,
54, 61, 70, 77
VCCQ
Isolated Output Buffer Supply
14, 17, 40, 66, 90
14, 17, 40, 66, 90
VSS
Ground : GND.
5,10,21,26,
55,60,71,76
5,10,21,26,
55,60,71,76
VSSQ
Isolated Output Buffer Ground
PRELIMINARY
(February, 2005, Version 0.1)
7
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Truth Table (Notes 5 - 7)
Address
Used
CE2 ZZ ADV/ R/
LD
OE
X
X
X
X
L
CLK
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
X
I/O
High-Z
High-Z
High-Z
High-Z
Q
Notes
CE
H
X
X
X
L
CE2
X
H
X
X
L
W
BWx
X
CEN
L
Operation
Deselected Cycle,
Power-down
None
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
X
Deselected Cycle,
Power-down
None
None
L
X
X
X
H
X
H
X
L
X
L
Deselected Cycle,
Power-down
L
X
L
Continue Deselect
Cycle
None
X
H
X
H
X
H
X
H
X
X
X
H
L
X
L
1
READ Cycle
(Begin Burst)
External
Next
X
L
READ Cycle
X
L
X
L
H
L
X
L
L
Q
1,7
2
(Continue Burst)
NOP/Dummy READ
(Begin Burst)
External
Next
X
H
H
X
X
X
X
X
X
L
High-Z
High-Z
D
Dummy READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
X
L
X
L
H
L
X
L
1,2,7
3
External
Next
L
L
WRITE Cycle
(Continue Burst)
NOP/WRITE Abort
(Begin Burst)
X
L
X
L
H
L
X
L
L
L
D
1,3,7
2,3
None
H
H
X
L
High-Z
High-Z
-
WRITE Abort
(Continue Burst)
IGNORE Clock Edge
(Stall)
Next
X
X
X
X
X
X
H
X
X
X
X
X
L
1,2,3,7
4
Current
None
H
X
SLEEP Mode
X
High-Z
Notes:
1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is
executed first.
2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE
Abort means a WRITE command is given, but no operation is performed.
3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the
output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their
requirements.
4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs during
a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock Edge cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
= H means all byte write signals (
,
,
BWx
BW1 BW2
BW3
and
) are HIGH.
BWx
= L means one or more byte write signals are LOW.
BW4
6.
enables WRITEs to Byte “a” (I/Oa pins);
BW1
enables WRITEs to Byte “b” (I/Ob pins);
BW3
enables WRITEs to Byte
BW2
“c” (I/Oc pins);
enables WRITEs to Byte “d” (I/Od pins).
BW4
7. The address counter is incremented for all Continue Burst cycles.
PRELIMINARY
(February, 2005, Version 0.1)
8
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Partial Truth Table for READ/WRITE Commands (X18)
Operation
R/
W
BW1
BW2
READ
H
X
X
WRITE Byte “a”
WRITE Byte “b”
WRITE all bytes
WRITE Abort/NOP
L
L
L
L
L
H
L
H
L
L
H
H
Note : Using R/ W and BYTE WRITE(s), any one or more bytes may be written.
Partial Truth Table for READ/WRITE Commands (X36)
Operation
R/
BW3
X
W
BW1
BW2
BW4
READ
H
X
X
X
WRITE Byte “a”
WRITE Byte “b”
WRITE Byte “c”
WRITE Byte “d”
WRITE all bytes
WRITE Abort/NOP
L
L
L
L
L
L
L
H
H
H
L
H
L
H
H
H
H
L
H
H
H
L
L
H
L
L
H
H
H
H
Note : Using R/ and BYTE WRITE(s), any one or more bytes may be written.
W
Linear Burst Address Table (MODE = LOW)
First Address (External)
X . . . X00
Second Address (Internal)
X . . . X01
Third Address (Internal)
X . . . X10
Fourth Address (Internal)
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External)
X . . . X00
Second Address (Internal)
X . . . X01
Third Address (Internal)
X . . . X10
Fourth Address (Internal)
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
PRELIMINARY
(February, 2005, Version 0.1)
9
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Absolute Maximum Ratings*
*Comments
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except VCC (Vin,
Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C
Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C
Storage Temperature (Tstg) . . . . . . . . . . -55°C to 125°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics and Operating Conditions
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = +3.3V± 5% unless otherwise noted)
Symbol
VIH
Parameter
Input High Voltage
Conditions
Min.
2.0
Max.
VCC+0.3
0.8
Unit
V
Note
1,2
VIL
Input Low Voltage
-0.3
-2.0
-2.0
V
1,2
ILI
Input Leakage Current
Output Leakage Current
0V ≤ VIH ≤ VCC
2.0
µA
µA
ILO
Output(s) disabled,
2.0
0V ≤ VIN≤ VCC
VOH
VOL
Output High Voltage
Output Low Voltage
Supply Voltage
IOH = -4.0mA
IOL = 8.0mA
2.4
V
V
V
V
1,3
1,3
1
0.4
VCC
VCCQ
3.135
3.135
3.465
VCC
Isolated Output Buffer Supply
1,4
Capacitance
Symbol
CI
Parameter
Conditions
TA = 25°C; f = 1MHz
VCC = 3.3V
Typ.
Max.
4
Unit
pF
Note
Control Input Capacitance
Input/Output Capacitance (I/O)
Address Capacitance
3
4
3
6
6
6
CO
5
pF
CA
3.5
pF
Note : 1. All voltages referenced to VSS (GND).
2. Overshoot : VIH ≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA
Undershoot : VIL ≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA
Power-up : VIH ≤ +3.465V and VCC ≤ 3.135 for t ≤ 200ms
3. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values.
AC I/O curves are available upon request.
4. VCC and VCCQ can be externally wired together to the same power supply.
5. This parameter is sampled.
PRELIMINARY (February, 2005, Version 0.1)
10
AMIC Technology, Corp.
A67L16181/A67L06361 Series
ICC Operating Condition and Maximum Limits
Max.
-7.5
Symbol
Parameter
Unit
Conditions
-6.5
-8.5
Device selected; All inputs ≤ VIL or ≥
VIH; Cycle time ≥ tKC (MIN); VCC =
MAX; Output open
Power Supply Current :
Operating
ICC
400
400
TBD
TBD
400
mA
Device deselected; VCC = MAX; All
inputs ≤ VSS+0.2 or ≥ VCC-0.2;
Cycle time ≥ tKC (MIN)
mA
mA
ISB
Standby
Standby
TBD
TBD
TBD
TBD
Device deselected; VCC = MAX; All
inputs ≤VSS+0.2 or ≥ VCC-0.2; All
inputs static; CLK frequency=MAX; ZZ
≥ VCC-0.2V
ISB
Device deselected; VCC = MAX; All
mA
mA
ISB2
Standby
TBD
TBD
TBD
TBD
TBD
TBD
inputs ≤ VIL; or ≥ VIH;
All
inputs static; CLK frequency=0
ISB2Z
SLEEP Mode
ZZ ≥ VIH
PRELIMINARY (February, 2005, Version 0.1)
11
AMIC Technology, Corp.
A67L16181/A67L06361 Series
AC Characteristics (Note 4)
(0°C ≤ TA ≤ 70°C, VCC = +3.3V± 5%)
-6.5
-7.5
-8.5
Symbol
Parameter
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
Clock
tKHKH
tKF
Clock cycle time
7.5
-
-
-8.5
-
-
10
-
-
ns
MHz
ns
Clock frequency
Clock HIGH time
Clock LOW time
133
117
100
tKHKL
tKLKH
2.5
2.5
-
-
2.8
2.8
-
-
3.0
3.0
-
-
ns
Output Times
tKHQV
tKHQX
tKHQX1
tKHQZ
tGLQV
tGLQX
tGHQZ
Clock to output valid
-
3.0
2.5
1.5
-
6.5
-
-
3.0
2.5
1.5
-
7.5
-
-
3.0
2.5
1.5
-
8.5
-
ns
ns
ns
ns
ns
ns
ns
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE to output valid
-
-
-
1,2,3
1,2,3
4
3.8
3.5
-
4.0
3.5
-
5.0
4.0
-
0
0
0
1,2,3
1,2,3
OE to output in Low-Z
OE to output in High-Z
-
3.5
-
3.5
-
4.0
Setup Times
tAVKH
tEVKH
Address
Clock enable (
1.5
1.5
1.5
1.5
-
-
-
-
2.0
2.0
2.0
2.0
-
-
-
-
2.0
2.0
2.0
2.0
-
-
-
-
ns
ns
ns
ns
5
5
5
5
)
)
CEN
tCVKH
Control signals
Data-in
tDVKH
Hold Times
tKHAX
Address
0.5
0.5
0.5
0.5
-
-
-
-
0.5
0.5
0.5
0.5
-
-
-
-
0.5
0.5
0.5
0.5
-
-
-
-
ns
ns
ns
ns
5
5
5
5
Clock enable (
tKHEX
CEN
tKHCX
Control signals
Data-in
tKHDX
Notes: 1. This parameter is sampled.
2. Output loading is specified with C1=5pF as in Figure 2.
3. Transition is measured ±200mV from steady state voltage.
4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for
turnaround timing.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when ADV/
is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with stable logic
LD
levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of
CLK (when ADV/ is LOW) to remain enabled.
LD
PRELIMINARY
(February, 2005, Version 0.1)
12
AMIC Technology, Corp.
A67L16181/A67L06361 Series
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.0ns
1.5V
1.5V
See Figures 1 and 2
+3.3V
Ω
319
Q
Q
O
Ω
Ω
50
Z =50
5pF
Ω
353
T
V =1.5V
Figure 1
Output Load Equivalent
Figure 2
Output Load Equivalent
PRELIMINARY
(February, 2005, Version 0.1)
13
AMIC Technology, Corp.
A67L16181/A67L06361 Series
SLEEP Mode
SLEEP Mode is a low current “Power-down” mode in which the
device is deselected and current is reduced to ISB2Z. This
duration of SLEEP Mode is dictated by the length of time the
ZZ is in a HIGH state. After entering SLEEP Mode, all inputs
except ZZ become disabled and all outputs go to High-Z.
The ZZ pin is asynchronous, active high input that causes the
device to enter SLEEP Mode. When the ZZ pin becomes
logic HIGH, ISB2Z is guaranteed after the time tZZI is met.
Any operation pending when entering SLEEP Mode is not
guaranteed to successfully complete. Therefore, SLEEP
Mode (READ or WRITE) must not be initiated until valid
pending operations are completed. Similarly, when exiting
SLEEP Mode during tRZZ, only a DESELECT or READ cycle
should be given while the SRAM is transitioning out of SLEEP
Mode.
SLEEP Mode Electrical Characteristics
(VCC, VCCQ = +3.3V±5%)
Symbol
ISB2Z
tZZ
Parameter
Conditions
Min.
Max.
TBD
Unit
mA
ns
Note
Current during SLEEP Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
ZZ ≥ VIH
-
0
0
-
2(tKHKH)
2(tKHKH)
2(tKHKH)
1
1
1
1
tRZZ
ns
tZZI
ns
tRZZI
0
ns
Note : 1. This parameter is sampled.
SLEEP Mode Waveform
CLK
tZZ
tRZZ
ZZ
tZZI
I
SUPPLY
IISB2Z
tRZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Output
(Q)
High-Z
: Don't Care
PRELIMINARY
(February, 2005, Version 0.1)
14
AMIC Technology, Corp.
A67L16181/A67L06361 Series
READ/WRITE Timing
1
2
3
4
5
6
7
8
9
10
tKHKH
CLK
CEN
tKHKL
t
EVK
H
t
KHE
X
tKLKH
tCVKH
tKHCX
CE
ADV/
LD
R/W
BWx
ADDRESS
A2
A3
t
A4
t
A5
A6
A7
A1
tAVKH
tKHAX
t
KHQV
KHQX1
KHQX
tGLQV
t
KHQZ
t
DVKH
tKHDX
Q(A4+1)
I/O
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
D(A5)
Q(A6)
D(A7)
tKHQX
tGHQZ
tGLQX
OE
COMMAND
BURST
WRITE
D(A2+1)
BURST
READ
Q(A4+1)
READ
Q(A4)
WRITE
D(A1)
WRITE
D(A2)
READ
Q(A3)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
: Don't Care
: Undefined
Note : 1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional.
3. represents three signals. When = 0, it represents = 0, = 0, CE2 = 1.
CE
CE
CE
CE2
4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The most
recent data may be from the input data register.
PRELIMINARY
(February, 2005, Version 0.1)
15
AMIC Technology, Corp.
A67L16181/A67L06361 Series
NOP, STALL and Deselect Cycles
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
I/O
A1
A2
A3
A4
A5
t
KHQZ
D(A1)
Q(A2)
Q(A3)
D(A4)
NOP
Q(A5)
t
KHQX
COMMAND
WRITE
D(A4)
CONTINUE
DESELECT
WRITE
D(A1)
READ
Q(A2)
READ
Q(A3)
READ
Q(A5)
STALL
STALL
DESELECT
: Don't Care
: Undefined
Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates
being used to create a “pause.” A WRITE is not
= 0, CE2 = 1.
CEN
CE2
performed during this cycle.
2. For this waveform, ZZ and
are tied LOW.
OE
represents three signals. When
3.
= 0, it represents
= 0,
CE
CE
CE
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
PRELIMINARY
(February, 2005, Version 0.1)
16
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Ordering Information
Part No.
Configure
Cycle Time / Access Time
Package
A67L16181E-6.5
A67L16181E-7.5
A67L16181-8.5
A67L06361E-6.5
A67L06361E-7.5
A67L06361E-8.5
7.5ns / 6.5ns
8.5ns / 7.5ns
10ns / 8.5ns
7.5ns / 6.5ns
8.5ns / 7.5ns
10ns / 8.5ns
100L LQFP
2M X 18
100L LQFP
1M X 36
PRELIMINARY
(February, 2005, Version 0.1)
17
AMIC Technology, Corp.
A67L16181/A67L06361 Series
Package Information
LQFP 100L Outline Dimensions
unit: inches/mm
H
E
A2
A1
E
y
80
51
81
50
31
100
1
30
b
c
e
θ
Dimensions in inches
Dimensions in mm
Symbol
Min.
0.002
0.053
0.011
0.005
0.860
0.783
0.624
0.547
Nom.
-
Max.
-
Min.
Nom.
-
Max.
A1
A2
b
0.05
1.35
-
0.055
0.013
-
0.057
0.015
0.008
0.872
0.791
0.636
0.555
1.40
1.45
0.27
0.32
0.37
c
0.12
-
0.20
HE
E
0.866
0.787
0.630
0.551
0.026 BSC
0.024
0.039 REF
-
21.85
19.90
15.85
13.90
22.00
20.00
16.00
14.00
0.65 BSC
0.60
22.15
20.10
16.15
14.10
HD
D
e
L
0.018
0.030
0.45
0.75
L1
y
1.00 REF
-
-
0.004
-
0.1
θ
0°
3.5°
7°
0°
3.5°
7°
Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
PRELIMINARY (February, 2005, Version 0.1)
18
AMIC Technology, Corp.
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