A63L8336E-3.2F
更新时间:2024-09-18 02:07:41
品牌:AMICC
描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output
A63L8336E-3.2F 概述
256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output 256K X 36位同步高速SRAM突发计数器和流水线数据输出 SRAM
A63L8336E-3.2F 规格参数
是否Rohs认证: | 符合 | 生命周期: | Obsolete |
包装说明: | QFP, QFP100,.63X.87 | Reach Compliance Code: | unknown |
风险等级: | 5.84 | Is Samacsys: | N |
最长访问时间: | 3.2 ns | 最大时钟频率 (fCLK): | 200 MHz |
I/O 类型: | COMMON | JESD-30 代码: | R-PQFP-G100 |
内存密度: | 9437184 bit | 内存集成电路类型: | STANDARD SRAM |
内存宽度: | 36 | 端子数量: | 100 |
字数: | 262144 words | 字数代码: | 256000 |
工作模式: | SYNCHRONOUS | 最高工作温度: | 70 °C |
最低工作温度: | 组织: | 256KX36 | |
输出特性: | 3-STATE | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | QFP | 封装等效代码: | QFP100,.63X.87 |
封装形状: | RECTANGULAR | 封装形式: | FLATPACK |
并行/串行: | PARALLEL | 电源: | 3.3 V |
认证状态: | Not Qualified | 最大待机电流: | 0.15 A |
最小待机电流: | 3.14 V | 子类别: | SRAMs |
最大压摆率: | 0.4 mA | 标称供电电压 (Vsup): | 3.3 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | COMMERCIAL | 端子形式: | GULL WING |
端子节距: | 0.635 mm | 端子位置: | QUAD |
Base Number Matches: | 1 |
A63L8336E-3.2F 数据手册
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PDF下载A63L8336
256K X 36 Bit Synchronous High Speed SRAM
with Burst Counter and Pipelined Data Output
Preliminary
Document Title
256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined
Data Output
Revision History
Rev. No. History
Issue Date
Remark
0.0
Initial issue
July 11, 2005
Preliminary
PRELIMINARY (July, 2005, Version 0.0)
AMIC Technology, Corp.
A63L8336
256K X 36 Bit Synchronous High Speed SRAM
with Burst Counter and Pipelined Data Output
Preliminary
Features
Fast access times: 2.6/2.8/3.2/3.5/3.8/4.2 ns
(250/227/200/166/150/133 MHZ)
Single +3.3V+10% or +3.3V-5% power supply
Synchronous burst function
Three separate chip enables allow wide range of
options for CE control, address pipelining
Selectable BURST mode
SLEEP mode (ZZ pin) provided
Individual Byte Write control and Global Write
Registered output for pipelined applications
Available in 100-pin LQFP package
General Description
The A63L8336 is a high-speed SRAM containing 9M bits
of bit synchronous memory, organized as 256K words by
36 bits.
The A63L8336 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output registers and a 256KX36 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A17), all data inputs (I/O1 - I/O36), active LOW chip enable
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63L8336
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1 controls
I/O1 - I/O9, BW2 controls I/O10 - I/O18, BW3 controls
I/O19 - I/O27, and BW4 controls I/O28 - I/O36, all on the
( CE ), two additional chip enables (CE2, CE2 ), burst
control inputs ( ADSC , ADSP , ADV ), byte write enables
( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write
condition that BWE is LOW. GW LOW causes all bytes
to be written.
( GW ). Asynchronous inputs include output enable ( OE ),
clock (CLK), BURST mode (MODE) and SLEEP mode
(ZZ).
PRELIMINARY
(July, 2005, Version 0.0)
1
AMIC Technology, Corp.
A63L8336
Pin Configuration
I/O19
I/O20
1
80
79
NC
2
I/O17
I/O16
VCCQ
GNDQ
I/O15
I/O14
I/O13
I/O12
GNDQ
VCCQ
I/O11
I/O10
GND
NC
I/O21
3
78
77
VCCQ
GNDQ
I/O22
4
5
76
75
74
6
7
I/O23
I/O24
8
73
72
9
I/O25
GNDQ
VCCQ
I/O26
10
11
12
13
14
15
16
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O27
NC
VCC
NC
A63L8336E
VCC
ZZ
GND
I/O28
17
18
I/O8
I/O29
19
20
21
22
23
24
25
26
27
28
29
30
I/O7
VCCQ
GNDQ
VCCQ
GNDQ
I/O6
I/O30
I/O31
I/O5
I/O4
I/O32
I/O33
I/O3
GNDQ
GNDQ
VCCQ
I/O2
VCCQ
I/O34
I/O35
I/O36
I/O1
I/O9
PRELIMINARY
(July, 2005, Version 0.0)
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AMIC Technology, Corp.
A63L8336
Block Diagram
ZZ
MODE
LOGIC
MODE
ADV
CLK
LOGIC
BURST
LOGIC
ADDRESS
COUNTER
CLR
CLK
ADSC
ADSP
ADDRESS
REGISTERS
A0-A17
18
8
BYTE1
WRITE
DRIVER
9
9
9
8
8
8
BYTE2
WRITE
DRIVER
GW
BWE
BW1
BW2
BW3
BW4
256KX9X4
MEMORY
ARRAY
OUTPUT
36
BYTE
WRITE
ENABLE
LOGIC
BYTE3
WRITE
DRIVER
REGISTERS
BYTE4
WRITE
DRIVER
9
36
4
DATA-IN
REGISTERS
4
CHIP
ENABLE
LOGIC
PIPELINED
ENABLE
LOGIC
CE
CE2
CE2
OUTPUT
ENABLE
LOGIC
OE
I/O1 - I/O36
PRELIMINARY
(July, 2005, Version 0.0)
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AMIC Technology, Corp.
A63L8336
Pin Description
Pin No.
Symbol
Description
32 – 37, 43 - 50, 81, 82,
99, 100
A0 - A17
Address Inputs
89
CLK
BWE , BW1 - BW4
GW
Clock
87, 93 - 96
Byte Write Enables
Global Write
88
86
Output Enable
OE
92, 97, 98
Chip Enables
CE2 ,CE2, CE
ADV
83
84
85
31
Burst Address Advance
Processor Address Status
Controller Address Status
ADSP
ADSC
MODE
Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
64
ZZ
Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
1,2, 3, 6 - 9, 12, 13, 18,
19, 22 - 25, 28, 29,
30,51,52, 53,
I/O1- I/O36
Data Inputs/Outputs
56 - 59, 62, 63, 68, 69, 72
- 75, 78, 79,80
15, 41, 65, 91
17, 40, 67, 90
VCC
GND
Power Supply
Ground
4, 11, 20, 27,
54, 61, 70, 77
VCCQ
Isolated Output Buffer Supply
5, 10, 21, 26,
55, 60, 71, 76
GNDQ
Isolated Output Buffer Ground
PRELIMINARY
(July, 2005, Version 0.0)
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AMIC Technology, Corp.
A63L8336
Synchronous Truth Table (See Notes 1 Through 5)
Address
I/O
Operation
Operation
CE2
CLK
ADSC
CE2
WRITE
CE
ADV
OE
ADSP
Used
Deselected Cycle,
Power-down
NONE
H
X
X
X
L
X
X
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
High-Z
Deselected Cycle,
Power-down
NONE
NONE
NONE
NONE
External
External
External
External
External
Next
L
L
X
H
X
H
L
L
X
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
Dout
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
L
H
H
L
Deselected Cycle,
Power-down
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
READ Cycle,
Begin Burst
L
X
X
L
READ Cycle,
Begin Burst
L
L
L
H
X
L
High-Z
Din
WRITE Cycle,
Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
READ Cycle,
Begin Burst
L
L
L
H
H
H
H
H
H
L
Dout
READ Cycle,
Begin Burst
L
L
L
H
L
High-Z
Dout
READ Cycle,
Continue Burst
READ Cycle,
Continue Burst
READ Cycle,
Continue Burst
READ Cycle,
Continue Burst
WRITE Cycle,
Continue Burst
WRITE Cycle,
Continue Burst
READ Cycle,
Suspend Burst
READ Cycle,
Suspend Burst
READ Cycle,
Suspend Burst
READ Cycle,
Suspend Burst
WRITE Cycle,
Suspend Burst
WRITE Cycle,
Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Dout
Next
L
Next
L
H
X
X
L
High-Z
Din
Next
L
Next
L
L
Din
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Dout
H
L
High-Z
Dout
H
X
X
High-Z
Din
L
Din
PRELIMINARY
(July, 2005, Version 0.0)
5
AMIC Technology, Corp.
A63L8336
Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.
2. WRITE = L means:
1) Any BWx (BW1,BW2 ,BW3 , or BW4 ) and BWE are low or
2) GW is low.
3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK.
4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held
HIGH throughout the input data hold time.
5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to
the Write timing diagram for clarification.
Write Truth Table
Operation
GW
H
BWE
BW1
BW2
X
BW3
X
BW4
X
READ
READ
H
L
L
L
X
X
H
L
H
H
H
H
WRITE Byte 1
WRITE all bytes
WRITE all bytes
H
H
H
H
H
L
L
L
L
L
X
X
X
X
PRELIMINARY
(July, 2005, Version 0.0)
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AMIC Technology, Corp.
A63L8336
Linear Burst Address Table (MODE = LOW)
First Address (External)
X . . . X00
Second Address (Internal)
Third Address (Internal)
X . . . X10
Fourth Address (Internal)
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X10
X . . . X00
X . . . X01
X . . . X11
X . . . X01
X . . . X10
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External)
X . . . X00
Second Address (Internal)
X . . . X01
Third Address (Internal)
X . . . X10
Fourth Address (Internal)
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
Absolute Maximum Ratings*
*Comments
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except VCC (Vin,
Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 2W
Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C
Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C
Storage Temperature (Tstg) . . . . . . . . . . . -55°C to 125°C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
Recommended DC Operating Conditions
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted)
Symbol
VCC
VCCQ
GND
VIH
Parameter
Supply Voltage (Operating Voltage Range)
Isolated Input Buffer Supply
Supply Voltage to GND
Min.
3.1
3.1
0.0
2.0
2.0
-0.3
Typ.
Max.
3.6
Unit
V
Note
3.3
3.3
VCC
V
-
-
-
-
0.0
V
Input High Voltage
VCC+0.3
VCC+0.3
0.8
V
1, 2
1, 2
VIHQ
Input High Voltage (I/O Pins)
Input Low Voltage
V
VIL
V
PRELIMINARY
(July, 2005, Version 0.0)
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AMIC Technology, Corp.
A63L8336
DC Electrical Characteristics
(0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted)
Symbol
⏐ILI⏐
Parameter
Min.
Max.
±2.0
±2.0
Unit
µA
Test Conditions
All inputs VIN = GND to VCC
OE = VIH, Vout = GND to VCC
Device selected; VCC = max.
Note
Input Leakage Current
Output Leakage Current
-
-
⏐ILO⏐
µA
ICC1
Supply Current
Standby Current
-
-
400
180
mA
mA
Iout = 0mA, all inputs = VIH or VIL
Cycle time = tKC min.
3, 11
Device deselected; VCC = max.
All inputs are fixed.
All inputs ≥ VCC - 0.2V
or ≤ GND + 0.2V
ISB1
11
Cycle time = tKC min.
ISB2
VOL
VOH
-
-
150
0.4
-
mA
V
ZZ ≥ VCC - 0.2V
IOL = 8 mA
Output Low Voltage
Output High Voltage
2.4
V
IOH = -4 mA
Capacitance
Symbol
CIN
Parameter
Input Capacitance
Input/Output Capacitance
Typ.
Max.
Unit
pF
Conditions
3
4
4
5
TA = 25 C; f = 1MHz
VCC = 3.3V
CI/O
pF
* These parameters are sampled and not 100% tested.
PRELIMINARY
(July, 2005, Version 0.0)
8
AMIC Technology, Corp.
A63L8336
AC Characteristics (0°C ≤ TA ≤ 70°C, VCC = 3.3V+10% or 3.3V-5%)
Symbol
Parameter
-2.6
-2.8
-3.2
-3.5
-3.8
-4.2
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
7.5
3.0
3.0
-
Max
tKC
tKH
4.0
1.7
1.7
-
-
4.4
2.0
2.0
-
-
5.0
2.0
2.0
-
-
6.0
2.2
2.2
-
-
6.7
2.5
2.5
-
-
-
ns
ns
ns
ns
ns
Clock Cycle Time
-
-
-
-
-
-
-
-
-
-
-
Clock High Time
tKL
-
3.5
-
Clock Low Time
tKQ
2.6
-
2.8
-
3.2
-
3.8
-
4.2
-
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock to Output in High-Z
OE to Output Valid
OE to Output in Low-Z
OE to Output in High-Z
tKQX
tKQLZ
tKQHZ
tOEQ
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
-
-
-
-
-
-
ns
ns
ns
ns
ns
5, 6
5, 6
8
1.5 2.6 1.5 2.8 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.5
-
0
-
2.6
-
-
0
-
2.8
-
-
0
-
3.2
-
-
0
-
3.5
-
-
0
-
3.8
-
-
0
-
4.2
-
tOELZ
tOEHZ
5, 6
5, 6
2.6
2.8
3.2
3.5
3.8
4.2
Setup Times
tAS
Address
1.2
1.2
-
-
1.4
1.4
-
-
1.4
1.4
-
-
1.5
1.5
-
-
1.5
1.5
-
-
1.5
1.5
-
-
ns
ns
7, 9
7, 9
tADSS
Address Status
( ADSC , ADSP )
tADVS
tWS
Address Advance
( ADV )
1.2
1.2
-
-
1.4
1.4
-
-
1.4
1.4
-
-
1.5
1.5
-
-
1.5
1.5
-
-
1.5
1.5
-
-
ns
ns
7, 9
7, 9
Write Signals
(BW1, BW2 , BW3 ,
BW4 , BWE , GW )
tDS
Data-in
1.2
1.2
-
-
1.4
1.4
-
-
1.4
1.4
-
-
1.5
1.5
-
-
1.5
1.5
-
-
1.5
1.5
-
-
ns
ns
7, 9
7, 9
tCES
Chip Enable ( CE , CE2,
CE2 )
PRELIMINARY
(July, 2005, Version 0.0)
9
AMIC Technology, Corp.
A63L8336
AC Characteristics (continued)
Symbol
Parameter
-2.6
-2.8
-3.2
-3.5
-3.8
-4.2
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Hold Times
tAH
Address
0.3
0.3
-
-
0.4
0.4
-
-
0.5
0.5
-
-
0.5
0.5
-
-
0.5
0.5
-
-
0.5
0.5
-
-
ns
ns
7, 9
7, 9
tADVH
Address Status
( ADSC , ADSP )
tAAH
tWH
Address Advance
( ADV )
0.3
0.3
-
-
0.4
0.4
-
-
0.5
0.5
-
-
0.5
0.5
-
-
0.5
0.5
-
-
0.5
0.5
-
-
ns
ns
7, 9
7, 9
Write Signal
(BW1, BW2 , BW3 ,
BW4 , BWE , GW )
tDH
Data-in
0.3
0.3
-
-
0.4
0.4
-
-
0.5
0.5
-
-
0.5
0.5
-
-
0.5
0.5
-
-
0.5
0.5
-
-
ns
ns
7, 9
7, 9
tCEH
Chip Enable
( CE , CE2, CE2 )
Notes:
1. All voltages refer to GND.
2. Overshoot: VIH ≤ +4.6V for t ≤ tKC/2.
Undershoot: VIH ≥ -0.7V for t ≤ tKC/2.
Power-up: VIH ≤ +3.6 and VCC ≤ 3.1V
for t ≤ 200ms
3. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified.
5. For output loading, CL = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage.
6. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tQELZ.
7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and ( ADSC or ADV LOW) or ADSP LOW for the
required setup and hold times.
8. OE has no effect when a Byte Write enable is sampled LOW.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and
hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be
valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.
10. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values.
AC I/O curves are available upon request.
11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means
device is active (not in POWER-DOWN mode).
12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage
current of 10µA.
13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to
emerge from SLEEP mode to ensure no data is lost.
PRELIMINARY
(July, 2005, Version 0.0)
10
AMIC Technology, Corp.
A63L8336
Timing Waveforms
tKC
CLK
t
KH
tKL
t
ADSS
t
ADSH
ADSP
ADSC
t
ADSS
tADSH
tAS
tAH
A1
A2
A3
Burst continued with
ADDRESS
t
WS
tWH
new base address
GW,BWE
BW1-BW4
Delselected
cycle
tCES
tCEH
CE
(NOTE *2)
(NOTE *4)
t
ADVS
tADVH
ADV
ADV suspends
burst
OE
t
OEHZ
tKQHZ
(NOTE *3)
t
OEQ
tKQ
t
OELZ
t
KQX
t
KQLZ
High-Z
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A3)
DOUT
Q(A2+1)
Burst wraps around
to its initial state
(NOTE *1)
t
KQ
Single READ
BURST READ
Read Timing
Notes:
*1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the internal burst address immediately
following A2.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. Timing shown assumes that the device was not enabled before entering this sequence. OE does not cause Q to
be driven until after the rising edge of the following clock.
PRELIMINARY
(July, 2005, Version 0.0)
11
AMIC Technology, Corp.
A63L8336
Timing Waveforms (continued)
t
KC
CLK
ADSP
t
KH
tKL
t
ADSS
tADSH
ADSC extends burst
t
ADSS
tADSH
t
ADSH
t
ADSS
ADSC
t
AS
tAH
A1
A2
A3
ADDRESS
BYTE WRITE signals are ignored
t
WS
t
WH
for first cycle when ADSP initiates burst
BWE,BW1-BW4
(NOTE *5)
t
WS
tWH
GW
t
CES
tCEH
CE
(NOTE *2)
t
ADVS
t
ADVH
ADV
(NOTE *4)
ADV suspends burst
OE
(NOTE *3)
t
DS
tDH
D(A3+2)
High-Z
D(A1)
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
DIN
t
OEHZ
(NOTE *1)
DOUT
BURST READ
Single WRITE
Extended BURST WRITE
Write Timing
Notes: *1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately
following A2.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in the above diagram, when CE is LOW, CE2
is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
*4. ADV must be HIGH to permit a Write to the loaded address.
*5. Byte Write enables are decided by means of a Write truth table.
PRELIMINARY
(July, 2005, Version 0.0)
12
AMIC Technology, Corp.
A63L8336
Timing Waveforms (continued)
tKC
CLK
ADSP
t
KH
tKL
tADSS
tADSH
ADSC
t
AS
t
AH
A1
A2
A3
A4
A5
A6
ADDRESS
tWS
tWH
GW,BWE,
BW1-BW4
(NOTE *3)
tCES
tCEH
CE
(NOTE *2)
ADV
OE
t
DS
tDH
tOELZ
tKQ
High-Z
High-Z
D(A3)
D(A6)
DIN
D(A5)
t
KQLZ
t
OEHZ
t
KQ
(NOTE *1)
Q(A4)
DOUT
Q(A4+3)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A3)
Q(A4+1)
Q(A4+2)
Back-to-Back
WRITEs
Pass-through
READ
Single WRITE
BURST READ
(NOTE *4)
Read/Write Timing
Notes:
*1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the internal burst address immediately
following A4.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. Byte Write enables are decided by means of a Write truth table.
*4. Pass-through occurs when data is first written, then Read in sequence.
PRELIMINARY
(July, 2005, Version 0.0)
13
AMIC Technology, Corp.
A63L8336
AC Test Conditions
Q
R
L=50
Ω
ZO=50Ω
Input Pulse Levels
GND to 3V
1.5ns
V
T=1.5V
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
Figure 1. Output Load Equivalent
+3.3V
1.5V
320
Ω
1.5V
Q
5pF
350
Ω
See Figures 1 and 2
Figure 2. Output Load Equivalent
PRELIMINARY
(July, 2005, Version 0.0)
14
AMIC Technology, Corp.
A63L8336
Ordering Information
Part No.
Access Times (ns)
Frequency (MHz)
Package
A63L8336E-2.6
A63L8336E-2.6F
A63L8336E-2.8
A63L8336E-2.8F
A63L8336E-3.2
A63L8336E-3.2F
A63L8336E-3.5
A63L8336E-3.5F
A63L8336E-3.8
A63L8336E-3.8F
A63L8336E-4.2
A63L8336E-4.2F
2.6
2.6
2.8
2.8
3.2
3.2
3.5
3.5
3.8
3.8
4.2
4.2
250
250
225
225
200
200
166
166
150
150
133
133
100L LQFP
100L Pb-Free LQFP
100L LQFP
100L Pb-Free LQFP
100L LQFP
100L Pb-Free LQFP
100L LQFP
100L Pb-Free LQFP
100L LQFP
100L Pb-Free LQFP
100L LQFP
100L Pb-Free LQFP
PRELIMINARY
(July, 2005, Version 0.0)
15
AMIC Technology, Corp.
A63L8336
Package Information
LQFP 100L Outline Dimensions
unit: inches/mm
H
E
A
2
A1
E
y
80
51
81
50
31
100
1
30
b
c
e
θ
Dimensions in inches
Dimensions in mm
Symbol
Min.
0.002
0.053
0.011
0.005
0.860
0.783
0.624
0.547
Nom.
-
Max.
-
Min.
0.05
Nom.
-
Max.
-
A1
A2
b
0.055
0.013
-
0.057
0.015
0.008
0.872
0.791
0.636
0.555
1.35
1.40
1.45
0.37
0.20
22.15
20.10
16.15
14.10
0.27
0.32
c
0.12
-
HE
E
0.866
0.787
0.630
0.551
0.026 BSC
0.024
0.039 REF
-
21.85
19.90
15.85
13.90
22.00
20.00
16.00
14.00
0.65 BSC
0.60
HD
D
e
L
0.018
0.030
0.45
0.75
L1
y
1.00 REF
-
-
0.004
-
0.1
θ
0°
3.5°
7°
0°
3.5°
7°
Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
PRELIMINARY
(July, 2005, Version 0.0)
16
AMIC Technology, Corp.
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