A623308-70SF 概述
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A623308-70SF 数据手册
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PDF下载A623308 Series
8K X 8 BIT CMOS SRAM
Document Title
8K X 8 BIT CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
0.2
0.3
1.0
1.1
1.2
Initial issue
July 2, 1999
Preliminary
Erase 55ns part
December 14, 2000
December 11, 2002
December 23, 2002
July 4, 2003
Add –SI/SU part no. and change ICC1, Isb1
Erase 28-pin TSOP reverse type package
Final version release
Final
Add Pb-Free package type
Add 28-pin DIP type package
August 19, 2004
December 14, 2004
(December, 2004, Version 1.2)
AMIC Technology, Corp.
A623308 Series
8K X 8 BIT CMOS SRAM
Features
ꢀExternal Operating Voltage: 4.5V to 5.5V
ꢀAccess times: 70 ns (max.)
ꢀCurrent:
ꢀExtended operating temperature range: 0°C to 70°C for -
S series, -25°C to 85°C for -SI series, -40°C to 85°C for
-SU series.
ꢀFull static operation, no clock or refreshing required
ꢀAll inputs and outputs are directly TTL compatible
ꢀCommon I/O using three-state output
ꢀData retention voltage: 2.0V (min.)
A623308-S series:
Operating: 35mA (max.)
Standby: 10µA (max.)
A623308-SI/SU series: Operating: 35mA (max.)
Standby: 15µA (max.)
ꢀAvailable in 28-pin DIP/SOP and TSOP (forward type)
packages
General Description
Minimum standby power is drawn by this device when CE is
at a high level, independent of the other input levels.
Data retention is guaranteed at a power supply voltage as
low as 2.0V.
The A623308 is a low operating current 65,536-bit static
random access memory organized as 8,192 words by 8 bits
and operates on a single 5V power supply.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Pin Configurations
ꢀDIP/SOP
ꢀTSOP
1
VCC
WE
NC
A8
28
27
26
25
24
23
22
NC
A12
A7
OE
A11
A9
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
2
3
4
5
6
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A6
A5
A4
A3
A2
A1
A0
A8
NC
WE
VCC
NC
A12
A7
A6
A5
A4
A3
A9
A11
A623308V
OE
7
8
9
A10
21
20
19
18
10
11
12
13
14
CE
9
I/O7
10
11
12
A1
A2
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
17
16
15
13
14
GND
(December, 2004, Version 1.2)
1
AMIC Technology, Corp.
A623308 Series
Block Diagram
VCC
GND
A5
ROW
128 X 512
A9
A11
A12
DECODER
MEMORY ARRAY
I/O
0
COLUMN I/O
INPUT
DATA
CIRCUIT
COLUMN DECODER
I/O
7
A0
A4 A10
CE
OE
WE
CONTORL
CIRCUIT
Pin Descriptions – SOP
Pin Description-TSOP
Pin No.
1,26
Symbol
Description
Pin No.
Symbol
Description
No Connection
Output Enable
NC
No Connection
Address Input
Data Inputs/Outputs
Ground
5,8
1
NC
2-10, 21, 23-25
11-13, 15-19
14
A0 – A12
I/O0 – I/O7
GND
OE
A0 – A12
VCC
2-4, 9-17, 28
Address Input
Power Supply
Write Enable
7
6
20
Chip Enable
CE
OE
WE
I/O0 – I/O7
GND
22
27
28
Output Enable
Write Enable
Power Supply
18-20, 22-26
Data Inputs/Outputs
Ground
21
27
WE
Chip Enable
VCC
CE
(December, 2004, Version 1.2)
2
AMIC Technology, Corp.
A623308 Series
Recommended DC Operating Conditions
(TA = 0°C to +70°C, -25°C to +85°C or –40°C to +85°C)
Symbol
VCC
Parameter
Supply Voltage
Ground
Min.
4.5
0
Typ.
5.0
0
Max.
5.5
0
Unit
V
GND
VIH
V
Input High Voltage
Input Low Voltage
2.2
-0.3
3.5
0
VCC + 0.3
+0.8
V
V
VIL
Absolute Maximum Ratings*
*Comments
VCC to GND . . . . . . . . . . . . . . . . . . . . . –0.5V to +7.0V
IN, IN/OUT Volt to GND . . . . . . . . . –0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 0°C to +70°C or –40°C to +85°C
Storage Temperature, Tstg . . . . . . . . . –55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . . 260°C, 10 sec
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied and exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DC Electrical Characteristics (TA = 0°C to +70°C, -25°C to +85°C or –40°C to +85°C, VCC = 5.0V ± 10%, GND = 0V)
A623308-70S
Min. Max.
A623308-70SI/SU
Symbol
Parameter
Unit
Conditions
Min.
Max.
Input Leakage
Current
-
1
-
1
VIN = GND to VCC
⏐ILI⏐
µA
µA
CE = VIH or OE = VIH or
Output Leakage
Current
-
1
-
1
⏐ILO⏐
WE = VIH ,
VI/O = GND to VCC
Active Power Supply
Current
ICC
-
-
5
-
-
5
mA
mA
CE = VIL, II/O = 0mA
Dynamic Operating
Current
Min. Cycle, Duty = 100%
ICC1
35
35
CE = VIL, II/O = 0mA
CE = VIL, VIH = VCC
VIL = 0V, f = 1 MHz
II/O = 0 mA
Dynamic Operating
Current
ICC2
-
-
mA
5
5
ISB
-
-
0.5
10
-
-
0.5
15
mA
CE = VIH
Supply Current
Standby Power
CE ≥ VCC – 0.2V
VIN ≥ 0V
ISB1
µA
Output Low Voltage
Output High Voltage
VOL
VOH
-
0.4
-
-
0.4
-
V
V
IOL = 2.1mA
IOH = -1.0mA
2.4
2.4
(December, 2004, Version 1.2)
3
AMIC Technology, Corp.
A623308 Series
Truth Table
Mode
I/O Operation
Supply Current
CE
H
L
OE
X
WE
X
Standby
Output Disable
Read
High Z
High Z
DOUT
ISB, ISB1
H
H
ICC, ICC1, ICC2
ICC, ICC1, ICC2
ICC, ICC1, ICC2
L
L
H
Write
L
X
L
DIN
Note: X: H or L
Capacitance (TA = 25°C, f = 1.0 MHz)
Symbol
CIN*
Parameter
Input Capacitance
Min.
Max.
Unit
pF
Conditions
VIN = 0V
6
8
CI/O*
Input/Output Capacitance
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
(December, 2004, Version 1.2)
4
AMIC Technology, Corp.
A623308 Series
AC Characteristics (TA = 0°C to +70°C, -25°C to +85°C or –40°C to +85°C, VCC = 5.0V ± 10%)
A623308-70S/SI/SU
Symbol
Parameter
Unit
Min.
Max.
Read Cycle
tRC
Read Cycle Time
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
70
70
35
-
tACE
tOE
Chip Enable Access Time
-
Output Enable to Output Valid
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
tCLZ
10
5
-
tOLZ
-
tCHZ
tOHZ
tOH
25
25
-
-
5
Write Cycle
tWC
Write Cycle Time
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Chip Enable to End of Write
Address Set up Time
tAS
-
tAW
Address Valid to End of Write
Write Pulse Width
60
50
0
-
tWP
-
tWR
Write Recovery Time
-
tWHZ
tDW
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
-
30
-
30
0
tDH
-
tOW
5
-
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
(December, 2004, Version 1.2)
5
AMIC Technology, Corp.
A623308 Series
Timing Waveforms
Read Cycle 1 (1)
t
RC
Address
t
AA
OE
t
OE
t
OH
5
OLZ
t
CE
5
OHZ
t
t
ACE
5
t
CHZ
5
CLZ
t
D
OUT
Read Cycle 2 (1, 2, 4)
t
RC
Address
t
AA
t
OH
t
OH
D
OUT
(December, 2004, Version 1.2)
6
AMIC Technology, Corp.
A623308 Series
Timing Waveforms (continued)
Read Cycle 3 (1, 3, 4)
CE
t
ACE
5
CLZ
t
5
CHZ
t
D
OUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
Write Cycle 1 (6)
(Write Enable Controlled)
t
WC
Address
3
WR
t
AW
t
5
CW
t
CE
(4)
1
2
tWP
t
AS
WE
t
DW
tDH
D
IN
7
WHZ
t
7
OW
t
D
OUT
(December, 2004, Version 1.2)
7
AMIC Technology, Corp.
A623308 Series
Timing Waveforms (continued)
Write Cycle 2 (6)
(Chip Enable Controlled)
t
WC
Address
3
tWR
t
AW
5
CW
t
CE
(4)
1
AS
t
2
t
WP
WE
t
DW
t
DH
D
IN
7
t
WHZ
D
OUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE .
3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle.
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE level is high or low.
7. Transition is measured ±500mV from steady. This parameter is sampled and not 100% tested.
(December, 2004, Version 1.2)
8
AMIC Technology, Corp.
A623308 Series
AC Test Conditions
Input Pulse Levels
0V, 3.0V
5 ns
Input Rise And Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See Figure 1,2
+5V
+5V
1800
Ω
1800Ω
I/O
I/O
C
L
990
Ω
C
L
990
Ω
30pF
*
5pF*
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ
tOLZ , tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to +70°C, -25°C to +85°C or –40°C to +85°C)
Symbol
Parameter
VCC for Data Retention
Min.
Max.
Unit
Conditions
VDR
2.0
5.5
V
CE ≥ VCC – 0.2V
VCC = 2.0V,
ICCDR
Data Retention Current
-
3
µA
CE ≥ VCC – 0.2V
VIN ≥ 0V
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
-
-
ns
ns
See Retention Waveform
tRC
Low VCC Data Retention Waveform
DATA RETENTION MODE
4.5V
4.5V
VCC
t
CDR
t
R
VDR
≥ 2.0V
V
IH
V
IH
CE
CE
≥ VDR - 0.2V
(December, 2004, Version 1.2)
9
AMIC Technology, Corp.
A623308 Series
Ordering Information
Part No.
Operating Current
Max. (mA)
Standby Current
Access Time (ns)
Package
Max. (µA)
A623308-70S
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
10
10
10
10
15
15
15
15
15
15
15
15
15
15
15
15
28L DIP
A623308-70SF
A623308M-70S
A623308M-70SF
A623308V-70S
A623308V-70SF
A623308-70SI
28L Pb-Free DIP
28L SOP
28L Pb-Free SOP
28L TSOP (Forward)
28L Pb-Free TSOP (Forward)
28L DIP
A623308-70SIF
A623308M-70SI
A623308M-70SIF
A623308V-70SI
A623308V-70SIF
A623308-70SU
A623308-70SUF
A623308M-70SU
A623308M-70SUF
A623308V-70SU
A623308V-70SUF
28L Pb-Free DIP
28L SOP
28L Pb-Free SOP
28L TSOP (Forward)
28L Pb-Free TSOP (Forward)
28L DIP
70
28L Pb-Free DIP
28L SOP
28L Pb-Free SOP
28L TSOP (Forward)
28L Pb-Free TSOP (Forward)
(December, 2004, Version 1.2)
10
AMIC Technology, Corp.
A623308 Series
Package Information
SOP (W.B.) 28L Outline Dimensions
unit: inches/mm
28
15
θ
L
Detail F
1
B
14
D
y
L1
S
e
y
See Detail F
Seating Plane
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
Min
Nom
-
Max
A
A1
A2
B
0.112
2.85
-
0.10
2.36
0.36
0.20
-
0.004
0.093
0.014
0.008
-
-
-
-
-
0.098
0.016
0.010
0.713
0.331
0.050
0.465
0.036
0.067
-
0.103
0.020
0.012
0.728
0.336
0.056
0.477
0.044
0.075
0.047
0.004
8°
2.49
0.41
0.25
18.11
8.41
1.27
11.81
0.91
1.70
-
2.62
0.51
0.30
18.49
8.53
1.42
12.12
1.12
1.91
1.19
0.10
8°
C
D
E
0.326
0.044
0.453
0.028
0.059
-
8.28
1.12
11.51
0.71
1.50
-
e
H
L
L1
S
y
-
-
-
-
0°
0°
-
-
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(December, 2004, Version 1.2)
11
AMIC Technology, Corp.
A623308 Series
Package Information
P-DIP 28L Outline Dimensions
unit: inches/mm
D
28
15
1
14
E
S
Base Plane
Seating Plane
B
e
A
α
e
1
B
1
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
0.210
-
Min
Nom
Max
5.33
A
-
-
-
-
-
A1
A2
0.010
0.150
0.25
3.81
-
0.155
0.160
3.94
4.06
B
0.016
0.058
0.018
0.060
0.022
0.064
0.41
1.47
0.46
1.52
0.56
1.63
0.36
B1
C
D
0.008
-
0.010
1.460
0.014
1.470
0.20
-
0.25
37.08
37.34
15.49
13.97
2.79
E
E1
e1
L
0.590
0.540
0.090
0.120
0°
0.600
0.545
0.100
0.130
-
0.610
0.550
0.110
0.140
15°
14.99
13.72
2.29
3.05
0°
15.24
13.84
2.54
3.30
-
3.56
15°
α
eA
S
0.630
-
0.650
-
0.670
0.090
16.00
-
16.51
-
17.02
2.29
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension S includes end flash.
(December, 2004, Version 1.2)
12
AMIC Technology, Corp.
A623308 Series
Package Information
TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
D
1
Detail "A"
1
28
θ
L
14
15
D
Detail "A"
y
S
b
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
0.049
-
Min
Nom
Max
1.25
A
A1
A2
b
-
-
-
0.002
0.037
0.007
0.005
0.311
0.012
0.520
0.461
-
0.039
0.009
-
0.05
0.95
0.17
0.12
7.90
0.30
13.20
11.70
-
1.00
0.22
-
-
0.041
0.011
0.008
0.319
0.028
0.536
0.469
1.05
0.27
0.21
8.10
0.70
13.60
11.90
c
E
L
0.315
0.020
0.528
0.465
0.022 BSC
0.017 TYP
-
8.00
0.50
13.40
11.80
0.55 BSC
0.425 TYP
-
D
D1
e
S
y
-
0.004
-
0.10
-
-
θ
0°
5°
0°
5°
Notes:
1. The maximum value of dimension D1 includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(December, 2004, Version 1.2)
13
AMIC Technology, Corp.
A623308-70SF 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
A623308-70SI | AMICC | SRAM | 获取价格 | |
A623308-70SIF | AMICC | SRAM | 获取价格 | |
A623308-70SU | AMICC | SRAM | 获取价格 | |
A623308-70SUF | AMICC | SRAM | 获取价格 | |
A623308A | AMICC | 8K X 8 BIT CMOS SRAM | 获取价格 | |
A623308A-70S | AMICC | 暂无描述 | 获取价格 | |
A623308A-70SF | AMICC | 8K X 8 BIT CMOS SRAM | 获取价格 | |
A623308A-70SI | AMICC | SRAM | 获取价格 | |
A623308A-70SIF | AMICC | 8K X 8 BIT CMOS SRAM | 获取价格 | |
A623308A-70SU | AMICC | SRAM | 获取价格 |
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